1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 289 h_div = H_TIMING_DIV_BY2; 290 291 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { 292 uint32_t data_fmt = 0; 293 294 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 295 data_fmt = 1; 296 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 297 data_fmt = 2; 298 299 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 300 } 301 302 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 303 if (optc1->opp_count == 4) 304 h_div = H_TIMING_DIV_BY4; 305 306 REG_UPDATE(OTG_H_TIMING_CNTL, 307 OTG_H_TIMING_DIV_MODE, h_div); 308 } else { 309 REG_UPDATE(OTG_H_TIMING_CNTL, 310 OTG_H_TIMING_DIV_BY2, h_div); 311 } 312 } 313 314 void optc1_set_vtg_params(struct timing_generator *optc, 315 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2) 316 { 317 struct dc_crtc_timing patched_crtc_timing; 318 uint32_t asic_blank_end; 319 uint32_t v_init; 320 uint32_t v_fp2 = 0; 321 int32_t vertical_line_start; 322 323 struct optc *optc1 = DCN10TG_FROM_TG(optc); 324 325 patched_crtc_timing = *dc_crtc_timing; 326 apply_front_porch_workaround(&patched_crtc_timing); 327 328 /* VCOUNT_INIT is the start of blank */ 329 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 330 331 /* end of blank = v_init - active */ 332 asic_blank_end = v_init - 333 patched_crtc_timing.v_border_bottom - 334 patched_crtc_timing.v_addressable - 335 patched_crtc_timing.v_border_top; 336 337 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 338 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 339 if (vertical_line_start < 0) 340 v_fp2 = -vertical_line_start; 341 342 /* Interlace */ 343 if (REG(OTG_INTERLACE_CONTROL)) { 344 if (patched_crtc_timing.flags.INTERLACE == 1) { 345 v_init = v_init / 2; 346 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 347 v_fp2 = v_fp2 / 2; 348 } 349 } 350 351 if (program_fp2) 352 REG_UPDATE_2(CONTROL, 353 VTG0_FP2, v_fp2, 354 VTG0_VCOUNT_INIT, v_init); 355 else 356 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); 357 } 358 359 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 360 { 361 struct optc *optc1 = DCN10TG_FROM_TG(optc); 362 363 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 364 365 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 366 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 367 } 368 369 /** 370 * optc1_set_timing_double_buffer() - DRR double buffering control 371 * 372 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 373 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 374 * 375 * Options: any time, start of frame, dp start of frame (range timing) 376 */ 377 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 378 { 379 struct optc *optc1 = DCN10TG_FROM_TG(optc); 380 uint32_t mode = enable ? 2 : 0; 381 382 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 383 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 384 } 385 386 /** 387 * unblank_crtc 388 * Call ASIC Control Object to UnBlank CRTC. 389 */ 390 static void optc1_unblank_crtc(struct timing_generator *optc) 391 { 392 struct optc *optc1 = DCN10TG_FROM_TG(optc); 393 394 REG_UPDATE_2(OTG_BLANK_CONTROL, 395 OTG_BLANK_DATA_EN, 0, 396 OTG_BLANK_DE_MODE, 0); 397 398 /* W/A for automated testing 399 * Automated testing will fail underflow test as there 400 * sporadic underflows which occur during the optc blank 401 * sequence. As a w/a, clear underflow on unblank. 402 * This prevents the failure, but will not mask actual 403 * underflow that affect real use cases. 404 */ 405 optc1_clear_optc_underflow(optc); 406 } 407 408 /** 409 * blank_crtc 410 * Call ASIC Control Object to Blank CRTC. 411 */ 412 413 static void optc1_blank_crtc(struct timing_generator *optc) 414 { 415 struct optc *optc1 = DCN10TG_FROM_TG(optc); 416 417 REG_UPDATE_2(OTG_BLANK_CONTROL, 418 OTG_BLANK_DATA_EN, 1, 419 OTG_BLANK_DE_MODE, 0); 420 421 optc1_set_blank_data_double_buffer(optc, false); 422 } 423 424 void optc1_set_blank(struct timing_generator *optc, 425 bool enable_blanking) 426 { 427 if (enable_blanking) 428 optc1_blank_crtc(optc); 429 else 430 optc1_unblank_crtc(optc); 431 } 432 433 bool optc1_is_blanked(struct timing_generator *optc) 434 { 435 struct optc *optc1 = DCN10TG_FROM_TG(optc); 436 uint32_t blank_en; 437 uint32_t blank_state; 438 439 REG_GET_2(OTG_BLANK_CONTROL, 440 OTG_BLANK_DATA_EN, &blank_en, 441 OTG_CURRENT_BLANK_STATE, &blank_state); 442 443 return blank_en && blank_state; 444 } 445 446 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 447 { 448 struct optc *optc1 = DCN10TG_FROM_TG(optc); 449 450 if (enable) { 451 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 452 OPTC_INPUT_CLK_EN, 1, 453 OPTC_INPUT_CLK_GATE_DIS, 1); 454 455 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 456 OPTC_INPUT_CLK_ON, 1, 457 1, 1000); 458 459 /* Enable clock */ 460 REG_UPDATE_2(OTG_CLOCK_CONTROL, 461 OTG_CLOCK_EN, 1, 462 OTG_CLOCK_GATE_DIS, 1); 463 REG_WAIT(OTG_CLOCK_CONTROL, 464 OTG_CLOCK_ON, 1, 465 1, 1000); 466 } else { 467 REG_UPDATE_2(OTG_CLOCK_CONTROL, 468 OTG_CLOCK_GATE_DIS, 0, 469 OTG_CLOCK_EN, 0); 470 471 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 472 OPTC_INPUT_CLK_GATE_DIS, 0, 473 OPTC_INPUT_CLK_EN, 0); 474 } 475 } 476 477 /** 478 * Enable CRTC 479 * Enable CRTC - call ASIC Control Object to enable Timing generator. 480 */ 481 static bool optc1_enable_crtc(struct timing_generator *optc) 482 { 483 /* TODO FPGA wait for answer 484 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 485 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 486 */ 487 struct optc *optc1 = DCN10TG_FROM_TG(optc); 488 489 /* opp instance for OTG. For DCN1.0, ODM is remoed. 490 * OPP and OPTC should 1:1 mapping 491 */ 492 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 493 OPTC_SRC_SEL, optc->inst); 494 495 /* VTG enable first is for HW workaround */ 496 REG_UPDATE(CONTROL, 497 VTG0_ENABLE, 1); 498 499 REG_SEQ_START(); 500 501 /* Enable CRTC */ 502 REG_UPDATE_2(OTG_CONTROL, 503 OTG_DISABLE_POINT_CNTL, 3, 504 OTG_MASTER_EN, 1); 505 506 REG_SEQ_SUBMIT(); 507 REG_SEQ_WAIT_DONE(); 508 509 return true; 510 } 511 512 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 513 bool optc1_disable_crtc(struct timing_generator *optc) 514 { 515 struct optc *optc1 = DCN10TG_FROM_TG(optc); 516 517 /* disable otg request until end of the first line 518 * in the vertical blank region 519 */ 520 REG_UPDATE_2(OTG_CONTROL, 521 OTG_DISABLE_POINT_CNTL, 3, 522 OTG_MASTER_EN, 0); 523 524 REG_UPDATE(CONTROL, 525 VTG0_ENABLE, 0); 526 527 /* CRTC disabled, so disable clock. */ 528 REG_WAIT(OTG_CLOCK_CONTROL, 529 OTG_BUSY, 0, 530 1, 100000); 531 532 return true; 533 } 534 535 536 void optc1_program_blank_color( 537 struct timing_generator *optc, 538 const struct tg_color *black_color) 539 { 540 struct optc *optc1 = DCN10TG_FROM_TG(optc); 541 542 REG_SET_3(OTG_BLACK_COLOR, 0, 543 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 544 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 545 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 546 } 547 548 bool optc1_validate_timing( 549 struct timing_generator *optc, 550 const struct dc_crtc_timing *timing) 551 { 552 uint32_t v_blank; 553 uint32_t h_blank; 554 uint32_t min_v_blank; 555 struct optc *optc1 = DCN10TG_FROM_TG(optc); 556 557 ASSERT(timing != NULL); 558 559 v_blank = (timing->v_total - timing->v_addressable - 560 timing->v_border_top - timing->v_border_bottom); 561 562 h_blank = (timing->h_total - timing->h_addressable - 563 timing->h_border_right - 564 timing->h_border_left); 565 566 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 567 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 568 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 569 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 570 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 571 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 572 return false; 573 574 /* Temporarily blocking interlacing mode until it's supported */ 575 if (timing->flags.INTERLACE == 1) 576 return false; 577 578 /* Check maximum number of pixels supported by Timing Generator 579 * (Currently will never fail, in order to fail needs display which 580 * needs more than 8192 horizontal and 581 * more than 8192 vertical total pixels) 582 */ 583 if (timing->h_total > optc1->max_h_total || 584 timing->v_total > optc1->max_v_total) 585 return false; 586 587 588 if (h_blank < optc1->min_h_blank) 589 return false; 590 591 if (timing->h_sync_width < optc1->min_h_sync_width || 592 timing->v_sync_width < optc1->min_v_sync_width) 593 return false; 594 595 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 596 597 if (v_blank < min_v_blank) 598 return false; 599 600 return true; 601 602 } 603 604 /* 605 * get_vblank_counter 606 * 607 * @brief 608 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 609 * holds the counter of frames. 610 * 611 * @param 612 * struct timing_generator *optc - [in] timing generator which controls the 613 * desired CRTC 614 * 615 * @return 616 * Counter of frames, which should equal to number of vblanks. 617 */ 618 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 619 { 620 struct optc *optc1 = DCN10TG_FROM_TG(optc); 621 uint32_t frame_count; 622 623 REG_GET(OTG_STATUS_FRAME_COUNT, 624 OTG_FRAME_COUNT, &frame_count); 625 626 return frame_count; 627 } 628 629 void optc1_lock(struct timing_generator *optc) 630 { 631 struct optc *optc1 = DCN10TG_FROM_TG(optc); 632 uint32_t regval = 0; 633 634 regval = REG_READ(OTG_CONTROL); 635 636 /* otg is not running, do not need to be locked */ 637 if ((regval & 0x1) == 0x0) 638 return; 639 640 REG_SET(OTG_GLOBAL_CONTROL0, 0, 641 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 642 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 643 OTG_MASTER_UPDATE_LOCK, 1); 644 645 /* Should be fast, status does not update on maximus */ 646 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 647 648 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 649 UPDATE_LOCK_STATUS, 1, 650 1, 10); 651 } 652 } 653 654 void optc1_unlock(struct timing_generator *optc) 655 { 656 struct optc *optc1 = DCN10TG_FROM_TG(optc); 657 658 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 659 OTG_MASTER_UPDATE_LOCK, 0); 660 } 661 662 bool optc1_is_locked(struct timing_generator *optc) 663 { 664 struct optc *optc1 = DCN10TG_FROM_TG(optc); 665 uint32_t locked; 666 667 REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked); 668 669 return (locked == 1); 670 } 671 672 void optc1_get_position(struct timing_generator *optc, 673 struct crtc_position *position) 674 { 675 struct optc *optc1 = DCN10TG_FROM_TG(optc); 676 677 REG_GET_2(OTG_STATUS_POSITION, 678 OTG_HORZ_COUNT, &position->horizontal_count, 679 OTG_VERT_COUNT, &position->vertical_count); 680 681 REG_GET(OTG_NOM_VERT_POSITION, 682 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 683 } 684 685 bool optc1_is_counter_moving(struct timing_generator *optc) 686 { 687 struct crtc_position position1, position2; 688 689 optc->funcs->get_position(optc, &position1); 690 optc->funcs->get_position(optc, &position2); 691 692 if (position1.horizontal_count == position2.horizontal_count && 693 position1.vertical_count == position2.vertical_count) 694 return false; 695 else 696 return true; 697 } 698 699 bool optc1_did_triggered_reset_occur( 700 struct timing_generator *optc) 701 { 702 struct optc *optc1 = DCN10TG_FROM_TG(optc); 703 uint32_t occurred_force, occurred_vsync; 704 705 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 706 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 707 708 REG_GET(OTG_VERT_SYNC_CONTROL, 709 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 710 711 return occurred_vsync != 0 || occurred_force != 0; 712 } 713 714 void optc1_disable_reset_trigger(struct timing_generator *optc) 715 { 716 struct optc *optc1 = DCN10TG_FROM_TG(optc); 717 718 REG_WRITE(OTG_TRIGA_CNTL, 0); 719 720 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 721 OTG_FORCE_COUNT_NOW_CLEAR, 1); 722 723 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 724 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 725 } 726 727 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 728 { 729 struct optc *optc1 = DCN10TG_FROM_TG(optc); 730 uint32_t falling_edge; 731 732 REG_GET(OTG_V_SYNC_A_CNTL, 733 OTG_V_SYNC_A_POL, &falling_edge); 734 735 if (falling_edge) 736 REG_SET_3(OTG_TRIGA_CNTL, 0, 737 /* vsync signal from selected OTG pipe based 738 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 739 */ 740 OTG_TRIGA_SOURCE_SELECT, 20, 741 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 742 /* always detect falling edge */ 743 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 744 else 745 REG_SET_3(OTG_TRIGA_CNTL, 0, 746 /* vsync signal from selected OTG pipe based 747 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 748 */ 749 OTG_TRIGA_SOURCE_SELECT, 20, 750 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 751 /* always detect rising edge */ 752 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 753 754 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 755 /* force H count to H_TOTAL and V count to V_TOTAL in 756 * progressive mode and V_TOTAL-1 in interlaced mode 757 */ 758 OTG_FORCE_COUNT_NOW_MODE, 2); 759 } 760 761 void optc1_enable_crtc_reset( 762 struct timing_generator *optc, 763 int source_tg_inst, 764 struct crtc_trigger_info *crtc_tp) 765 { 766 struct optc *optc1 = DCN10TG_FROM_TG(optc); 767 uint32_t falling_edge = 0; 768 uint32_t rising_edge = 0; 769 770 switch (crtc_tp->event) { 771 772 case CRTC_EVENT_VSYNC_RISING: 773 rising_edge = 1; 774 break; 775 776 case CRTC_EVENT_VSYNC_FALLING: 777 falling_edge = 1; 778 break; 779 } 780 781 REG_SET_4(OTG_TRIGA_CNTL, 0, 782 /* vsync signal from selected OTG pipe based 783 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 784 */ 785 OTG_TRIGA_SOURCE_SELECT, 20, 786 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 787 /* always detect falling edge */ 788 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 789 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 790 791 switch (crtc_tp->delay) { 792 case TRIGGER_DELAY_NEXT_LINE: 793 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 794 OTG_AUTO_FORCE_VSYNC_MODE, 1); 795 break; 796 case TRIGGER_DELAY_NEXT_PIXEL: 797 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 798 /* force H count to H_TOTAL and V count to V_TOTAL in 799 * progressive mode and V_TOTAL-1 in interlaced mode 800 */ 801 OTG_FORCE_COUNT_NOW_MODE, 2); 802 break; 803 } 804 } 805 806 void optc1_wait_for_state(struct timing_generator *optc, 807 enum crtc_state state) 808 { 809 struct optc *optc1 = DCN10TG_FROM_TG(optc); 810 811 switch (state) { 812 case CRTC_STATE_VBLANK: 813 REG_WAIT(OTG_STATUS, 814 OTG_V_BLANK, 1, 815 1, 100000); /* 1 vupdate at 10hz */ 816 break; 817 818 case CRTC_STATE_VACTIVE: 819 REG_WAIT(OTG_STATUS, 820 OTG_V_ACTIVE_DISP, 1, 821 1, 100000); /* 1 vupdate at 10hz */ 822 break; 823 824 default: 825 break; 826 } 827 } 828 829 void optc1_set_early_control( 830 struct timing_generator *optc, 831 uint32_t early_cntl) 832 { 833 /* asic design change, do not need this control 834 * empty for share caller logic 835 */ 836 } 837 838 839 void optc1_set_static_screen_control( 840 struct timing_generator *optc, 841 uint32_t event_triggers, 842 uint32_t num_frames) 843 { 844 struct optc *optc1 = DCN10TG_FROM_TG(optc); 845 846 // By register spec, it only takes 8 bit value 847 if (num_frames > 0xFF) 848 num_frames = 0xFF; 849 850 /* Bit 8 is no longer applicable in RV for PSR case, 851 * set bit 8 to 0 if given 852 */ 853 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 854 != 0) 855 event_triggers = event_triggers & 856 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 857 858 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 859 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 860 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 861 } 862 863 static void optc1_setup_manual_trigger(struct timing_generator *optc) 864 { 865 struct optc *optc1 = DCN10TG_FROM_TG(optc); 866 867 REG_SET(OTG_GLOBAL_CONTROL2, 0, 868 MANUAL_FLOW_CONTROL_SEL, optc->inst); 869 870 REG_SET_8(OTG_TRIGA_CNTL, 0, 871 OTG_TRIGA_SOURCE_SELECT, 22, 872 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 873 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 874 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 875 OTG_TRIGA_POLARITY_SELECT, 0, 876 OTG_TRIGA_FREQUENCY_SELECT, 0, 877 OTG_TRIGA_DELAY, 0, 878 OTG_TRIGA_CLEAR, 1); 879 } 880 881 static void optc1_program_manual_trigger(struct timing_generator *optc) 882 { 883 struct optc *optc1 = DCN10TG_FROM_TG(optc); 884 885 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 886 MANUAL_FLOW_CONTROL, 1); 887 888 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 889 MANUAL_FLOW_CONTROL, 0); 890 } 891 892 893 /** 894 ***************************************************************************** 895 * Function: set_drr 896 * 897 * @brief 898 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 899 * 900 ***************************************************************************** 901 */ 902 void optc1_set_drr( 903 struct timing_generator *optc, 904 const struct drr_params *params) 905 { 906 struct optc *optc1 = DCN10TG_FROM_TG(optc); 907 908 if (params != NULL && 909 params->vertical_total_max > 0 && 910 params->vertical_total_min > 0) { 911 912 if (params->vertical_total_mid != 0) { 913 914 REG_SET(OTG_V_TOTAL_MID, 0, 915 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 916 917 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 918 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 919 OTG_VTOTAL_MID_FRAME_NUM, 920 (uint8_t)params->vertical_total_mid_frame_num); 921 922 } 923 924 REG_SET(OTG_V_TOTAL_MAX, 0, 925 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 926 927 REG_SET(OTG_V_TOTAL_MIN, 0, 928 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 929 930 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 931 OTG_V_TOTAL_MIN_SEL, 1, 932 OTG_V_TOTAL_MAX_SEL, 1, 933 OTG_FORCE_LOCK_ON_EVENT, 0, 934 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 935 OTG_SET_V_TOTAL_MIN_MASK, 0); 936 937 // Setup manual flow control for EOF via TRIG_A 938 optc->funcs->setup_manual_trigger(optc); 939 940 } else { 941 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 942 OTG_SET_V_TOTAL_MIN_MASK, 0, 943 OTG_V_TOTAL_MIN_SEL, 0, 944 OTG_V_TOTAL_MAX_SEL, 0, 945 OTG_FORCE_LOCK_ON_EVENT, 0); 946 947 REG_SET(OTG_V_TOTAL_MIN, 0, 948 OTG_V_TOTAL_MIN, 0); 949 950 REG_SET(OTG_V_TOTAL_MAX, 0, 951 OTG_V_TOTAL_MAX, 0); 952 } 953 } 954 955 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) 956 { 957 struct optc *optc1 = DCN10TG_FROM_TG(optc); 958 959 REG_SET(OTG_V_TOTAL_MAX, 0, 960 OTG_V_TOTAL_MAX, vtotal_max); 961 962 REG_SET(OTG_V_TOTAL_MIN, 0, 963 OTG_V_TOTAL_MIN, vtotal_min); 964 } 965 966 static void optc1_set_test_pattern( 967 struct timing_generator *optc, 968 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 969 * because this is not DP-specific (which is probably somewhere in DP 970 * encoder) */ 971 enum controller_dp_test_pattern test_pattern, 972 enum dc_color_depth color_depth) 973 { 974 struct optc *optc1 = DCN10TG_FROM_TG(optc); 975 enum test_pattern_color_format bit_depth; 976 enum test_pattern_dyn_range dyn_range; 977 enum test_pattern_mode mode; 978 uint32_t pattern_mask; 979 uint32_t pattern_data; 980 /* color ramp generator mixes 16-bits color */ 981 uint32_t src_bpc = 16; 982 /* requested bpc */ 983 uint32_t dst_bpc; 984 uint32_t index; 985 /* RGB values of the color bars. 986 * Produce two RGB colors: RGB0 - white (all Fs) 987 * and RGB1 - black (all 0s) 988 * (three RGB components for two colors) 989 */ 990 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 991 0x0000, 0x0000}; 992 /* dest color (converted to the specified color format) */ 993 uint16_t dst_color[6]; 994 uint32_t inc_base; 995 996 /* translate to bit depth */ 997 switch (color_depth) { 998 case COLOR_DEPTH_666: 999 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 1000 break; 1001 case COLOR_DEPTH_888: 1002 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1003 break; 1004 case COLOR_DEPTH_101010: 1005 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 1006 break; 1007 case COLOR_DEPTH_121212: 1008 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 1009 break; 1010 default: 1011 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1012 break; 1013 } 1014 1015 switch (test_pattern) { 1016 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 1017 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 1018 { 1019 dyn_range = (test_pattern == 1020 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 1021 TEST_PATTERN_DYN_RANGE_CEA : 1022 TEST_PATTERN_DYN_RANGE_VESA); 1023 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1024 1025 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1026 OTG_TEST_PATTERN_VRES, 6, 1027 OTG_TEST_PATTERN_HRES, 6); 1028 1029 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1030 OTG_TEST_PATTERN_EN, 1, 1031 OTG_TEST_PATTERN_MODE, mode, 1032 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1033 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1034 } 1035 break; 1036 1037 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1038 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1039 { 1040 mode = (test_pattern == 1041 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1042 TEST_PATTERN_MODE_VERTICALBARS : 1043 TEST_PATTERN_MODE_HORIZONTALBARS); 1044 1045 switch (bit_depth) { 1046 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1047 dst_bpc = 6; 1048 break; 1049 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1050 dst_bpc = 8; 1051 break; 1052 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1053 dst_bpc = 10; 1054 break; 1055 default: 1056 dst_bpc = 8; 1057 break; 1058 } 1059 1060 /* adjust color to the required colorFormat */ 1061 for (index = 0; index < 6; index++) { 1062 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1063 * (srcBpc - dstBpc); 1064 */ 1065 dst_color[index] = 1066 src_color[index] >> (src_bpc - dst_bpc); 1067 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1068 * lowest 6 are hardwired to ZERO 1069 * color bits should be left aligned aligned to MSB 1070 * XXXXXXXXXX000000 for 10 bit, 1071 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1072 */ 1073 dst_color[index] <<= (16 - dst_bpc); 1074 } 1075 1076 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1077 1078 /* We have to write the mask before data, similar to pipeline. 1079 * For example, for 8 bpc, if we want RGB0 to be magenta, 1080 * and RGB1 to be cyan, 1081 * we need to make 7 writes: 1082 * MASK DATA 1083 * 000001 00000000 00000000 set mask to R0 1084 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1085 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1086 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1087 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1088 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1089 * 100000 11111111 00000000 B1 255, 0xFF00 1090 * 1091 * we will make a loop of 6 in which we prepare the mask, 1092 * then write, then prepare the color for next write. 1093 * first iteration will write mask only, 1094 * but each next iteration color prepared in 1095 * previous iteration will be written within new mask, 1096 * the last component will written separately, 1097 * mask is not changing between 6th and 7th write 1098 * and color will be prepared by last iteration 1099 */ 1100 1101 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1102 * is B1, G1, R1, B0, G0, R0 1103 */ 1104 pattern_data = 0; 1105 for (index = 0; index < 6; index++) { 1106 /* prepare color mask, first write PATTERN_DATA 1107 * will have all zeros 1108 */ 1109 pattern_mask = (1 << index); 1110 1111 /* write color component */ 1112 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1113 OTG_TEST_PATTERN_MASK, pattern_mask, 1114 OTG_TEST_PATTERN_DATA, pattern_data); 1115 1116 /* prepare next color component, 1117 * will be written in the next iteration 1118 */ 1119 pattern_data = dst_color[index]; 1120 } 1121 /* write last color component, 1122 * it's been already prepared in the loop 1123 */ 1124 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1125 OTG_TEST_PATTERN_MASK, pattern_mask, 1126 OTG_TEST_PATTERN_DATA, pattern_data); 1127 1128 /* enable test pattern */ 1129 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1130 OTG_TEST_PATTERN_EN, 1, 1131 OTG_TEST_PATTERN_MODE, mode, 1132 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1133 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1134 } 1135 break; 1136 1137 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1138 { 1139 mode = (bit_depth == 1140 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1141 TEST_PATTERN_MODE_DUALRAMP_RGB : 1142 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1143 1144 switch (bit_depth) { 1145 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1146 dst_bpc = 6; 1147 break; 1148 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1149 dst_bpc = 8; 1150 break; 1151 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1152 dst_bpc = 10; 1153 break; 1154 default: 1155 dst_bpc = 8; 1156 break; 1157 } 1158 1159 /* increment for the first ramp for one color gradation 1160 * 1 gradation for 6-bit color is 2^10 1161 * gradations in 16-bit color 1162 */ 1163 inc_base = (src_bpc - dst_bpc); 1164 1165 switch (bit_depth) { 1166 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1167 { 1168 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1169 OTG_TEST_PATTERN_INC0, inc_base, 1170 OTG_TEST_PATTERN_INC1, 0, 1171 OTG_TEST_PATTERN_HRES, 6, 1172 OTG_TEST_PATTERN_VRES, 6, 1173 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1174 } 1175 break; 1176 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1177 { 1178 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1179 OTG_TEST_PATTERN_INC0, inc_base, 1180 OTG_TEST_PATTERN_INC1, 0, 1181 OTG_TEST_PATTERN_HRES, 8, 1182 OTG_TEST_PATTERN_VRES, 6, 1183 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1184 } 1185 break; 1186 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1187 { 1188 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1189 OTG_TEST_PATTERN_INC0, inc_base, 1190 OTG_TEST_PATTERN_INC1, inc_base + 2, 1191 OTG_TEST_PATTERN_HRES, 8, 1192 OTG_TEST_PATTERN_VRES, 5, 1193 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1194 } 1195 break; 1196 default: 1197 break; 1198 } 1199 1200 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1201 1202 /* enable test pattern */ 1203 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1204 1205 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1206 OTG_TEST_PATTERN_EN, 1, 1207 OTG_TEST_PATTERN_MODE, mode, 1208 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1209 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1210 } 1211 break; 1212 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1213 { 1214 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1215 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1216 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1217 } 1218 break; 1219 default: 1220 break; 1221 1222 } 1223 } 1224 1225 void optc1_get_crtc_scanoutpos( 1226 struct timing_generator *optc, 1227 uint32_t *v_blank_start, 1228 uint32_t *v_blank_end, 1229 uint32_t *h_position, 1230 uint32_t *v_position) 1231 { 1232 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1233 struct crtc_position position; 1234 1235 REG_GET_2(OTG_V_BLANK_START_END, 1236 OTG_V_BLANK_START, v_blank_start, 1237 OTG_V_BLANK_END, v_blank_end); 1238 1239 optc1_get_position(optc, &position); 1240 1241 *h_position = position.horizontal_count; 1242 *v_position = position.vertical_count; 1243 } 1244 1245 static void optc1_enable_stereo(struct timing_generator *optc, 1246 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1247 { 1248 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1249 1250 if (flags) { 1251 uint32_t stereo_en; 1252 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1253 1254 if (flags->PROGRAM_STEREO) 1255 REG_UPDATE_3(OTG_STEREO_CONTROL, 1256 OTG_STEREO_EN, stereo_en, 1257 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1258 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1259 1260 if (flags->PROGRAM_POLARITY) 1261 REG_UPDATE(OTG_STEREO_CONTROL, 1262 OTG_STEREO_EYE_FLAG_POLARITY, 1263 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1264 1265 if (flags->DISABLE_STEREO_DP_SYNC) 1266 REG_UPDATE(OTG_STEREO_CONTROL, 1267 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1268 1269 if (flags->PROGRAM_STEREO) 1270 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1271 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1272 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1273 1274 } 1275 } 1276 1277 void optc1_program_stereo(struct timing_generator *optc, 1278 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1279 { 1280 if (flags->PROGRAM_STEREO) 1281 optc1_enable_stereo(optc, timing, flags); 1282 else 1283 optc1_disable_stereo(optc); 1284 } 1285 1286 1287 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1288 { 1289 bool ret = false; 1290 uint32_t left_eye = 0; 1291 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1292 1293 REG_GET(OTG_STEREO_STATUS, 1294 OTG_STEREO_CURRENT_EYE, &left_eye); 1295 if (left_eye == 1) 1296 ret = true; 1297 else 1298 ret = false; 1299 1300 return ret; 1301 } 1302 1303 bool optc1_get_hw_timing(struct timing_generator *tg, 1304 struct dc_crtc_timing *hw_crtc_timing) 1305 { 1306 struct dcn_otg_state s = {0}; 1307 1308 if (tg == NULL || hw_crtc_timing == NULL) 1309 return false; 1310 1311 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1312 1313 hw_crtc_timing->h_total = s.h_total + 1; 1314 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1315 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1316 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1317 1318 hw_crtc_timing->v_total = s.v_total + 1; 1319 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1320 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1321 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1322 1323 return true; 1324 } 1325 1326 1327 void optc1_read_otg_state(struct optc *optc1, 1328 struct dcn_otg_state *s) 1329 { 1330 REG_GET(OTG_CONTROL, 1331 OTG_MASTER_EN, &s->otg_enabled); 1332 1333 REG_GET_2(OTG_V_BLANK_START_END, 1334 OTG_V_BLANK_START, &s->v_blank_start, 1335 OTG_V_BLANK_END, &s->v_blank_end); 1336 1337 REG_GET(OTG_V_SYNC_A_CNTL, 1338 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1339 1340 REG_GET(OTG_V_TOTAL, 1341 OTG_V_TOTAL, &s->v_total); 1342 1343 REG_GET(OTG_V_TOTAL_MAX, 1344 OTG_V_TOTAL_MAX, &s->v_total_max); 1345 1346 REG_GET(OTG_V_TOTAL_MIN, 1347 OTG_V_TOTAL_MIN, &s->v_total_min); 1348 1349 REG_GET(OTG_V_TOTAL_CONTROL, 1350 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1351 1352 REG_GET(OTG_V_TOTAL_CONTROL, 1353 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1354 1355 REG_GET_2(OTG_V_SYNC_A, 1356 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1357 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1358 1359 REG_GET_2(OTG_H_BLANK_START_END, 1360 OTG_H_BLANK_START, &s->h_blank_start, 1361 OTG_H_BLANK_END, &s->h_blank_end); 1362 1363 REG_GET_2(OTG_H_SYNC_A, 1364 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1365 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1366 1367 REG_GET(OTG_H_SYNC_A_CNTL, 1368 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1369 1370 REG_GET(OTG_H_TOTAL, 1371 OTG_H_TOTAL, &s->h_total); 1372 1373 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1374 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1375 1376 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1377 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1378 1379 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1380 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1381 } 1382 1383 bool optc1_get_otg_active_size(struct timing_generator *optc, 1384 uint32_t *otg_active_width, 1385 uint32_t *otg_active_height) 1386 { 1387 uint32_t otg_enabled; 1388 uint32_t v_blank_start; 1389 uint32_t v_blank_end; 1390 uint32_t h_blank_start; 1391 uint32_t h_blank_end; 1392 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1393 1394 1395 REG_GET(OTG_CONTROL, 1396 OTG_MASTER_EN, &otg_enabled); 1397 1398 if (otg_enabled == 0) 1399 return false; 1400 1401 REG_GET_2(OTG_V_BLANK_START_END, 1402 OTG_V_BLANK_START, &v_blank_start, 1403 OTG_V_BLANK_END, &v_blank_end); 1404 1405 REG_GET_2(OTG_H_BLANK_START_END, 1406 OTG_H_BLANK_START, &h_blank_start, 1407 OTG_H_BLANK_END, &h_blank_end); 1408 1409 *otg_active_width = v_blank_start - v_blank_end; 1410 *otg_active_height = h_blank_start - h_blank_end; 1411 return true; 1412 } 1413 1414 void optc1_clear_optc_underflow(struct timing_generator *optc) 1415 { 1416 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1417 1418 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1419 } 1420 1421 void optc1_tg_init(struct timing_generator *optc) 1422 { 1423 optc1_set_blank_data_double_buffer(optc, true); 1424 optc1_set_timing_double_buffer(optc, true); 1425 optc1_clear_optc_underflow(optc); 1426 } 1427 1428 bool optc1_is_tg_enabled(struct timing_generator *optc) 1429 { 1430 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1431 uint32_t otg_enabled = 0; 1432 1433 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1434 1435 return (otg_enabled != 0); 1436 1437 } 1438 1439 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1440 { 1441 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1442 uint32_t underflow_occurred = 0; 1443 1444 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1445 OPTC_UNDERFLOW_OCCURRED_STATUS, 1446 &underflow_occurred); 1447 1448 return (underflow_occurred == 1); 1449 } 1450 1451 bool optc1_configure_crc(struct timing_generator *optc, 1452 const struct crc_params *params) 1453 { 1454 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1455 1456 /* Cannot configure crc on a CRTC that is disabled */ 1457 if (!optc1_is_tg_enabled(optc)) 1458 return false; 1459 1460 REG_WRITE(OTG_CRC_CNTL, 0); 1461 1462 if (!params->enable) 1463 return true; 1464 1465 /* Program frame boundaries */ 1466 /* Window A x axis start and end. */ 1467 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1468 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1469 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1470 1471 /* Window A y axis start and end. */ 1472 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1473 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1474 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1475 1476 /* Window B x axis start and end. */ 1477 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1478 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1479 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1480 1481 /* Window B y axis start and end. */ 1482 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1483 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1484 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1485 1486 /* Set crc mode and selection, and enable. Only using CRC0*/ 1487 REG_UPDATE_3(OTG_CRC_CNTL, 1488 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1489 OTG_CRC0_SELECT, params->selection, 1490 OTG_CRC_EN, 1); 1491 1492 return true; 1493 } 1494 1495 bool optc1_get_crc(struct timing_generator *optc, 1496 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1497 { 1498 uint32_t field = 0; 1499 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1500 1501 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1502 1503 /* Early return if CRC is not enabled for this CRTC */ 1504 if (!field) 1505 return false; 1506 1507 REG_GET_2(OTG_CRC0_DATA_RG, 1508 CRC0_R_CR, r_cr, 1509 CRC0_G_Y, g_y); 1510 1511 REG_GET(OTG_CRC0_DATA_B, 1512 CRC0_B_CB, b_cb); 1513 1514 return true; 1515 } 1516 1517 static const struct timing_generator_funcs dcn10_tg_funcs = { 1518 .validate_timing = optc1_validate_timing, 1519 .program_timing = optc1_program_timing, 1520 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1521 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1522 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1523 .program_global_sync = optc1_program_global_sync, 1524 .enable_crtc = optc1_enable_crtc, 1525 .disable_crtc = optc1_disable_crtc, 1526 /* used by enable_timing_synchronization. Not need for FPGA */ 1527 .is_counter_moving = optc1_is_counter_moving, 1528 .get_position = optc1_get_position, 1529 .get_frame_count = optc1_get_vblank_counter, 1530 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1531 .get_otg_active_size = optc1_get_otg_active_size, 1532 .set_early_control = optc1_set_early_control, 1533 /* used by enable_timing_synchronization. Not need for FPGA */ 1534 .wait_for_state = optc1_wait_for_state, 1535 .set_blank = optc1_set_blank, 1536 .is_blanked = optc1_is_blanked, 1537 .set_blank_color = optc1_program_blank_color, 1538 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1539 .enable_reset_trigger = optc1_enable_reset_trigger, 1540 .enable_crtc_reset = optc1_enable_crtc_reset, 1541 .disable_reset_trigger = optc1_disable_reset_trigger, 1542 .lock = optc1_lock, 1543 .is_locked = optc1_is_locked, 1544 .unlock = optc1_unlock, 1545 .enable_optc_clock = optc1_enable_optc_clock, 1546 .set_drr = optc1_set_drr, 1547 .get_last_used_drr_vtotal = NULL, 1548 .set_static_screen_control = optc1_set_static_screen_control, 1549 .set_test_pattern = optc1_set_test_pattern, 1550 .program_stereo = optc1_program_stereo, 1551 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1552 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1553 .tg_init = optc1_tg_init, 1554 .is_tg_enabled = optc1_is_tg_enabled, 1555 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1556 .clear_optc_underflow = optc1_clear_optc_underflow, 1557 .get_crc = optc1_get_crc, 1558 .configure_crc = optc1_configure_crc, 1559 .set_vtg_params = optc1_set_vtg_params, 1560 .program_manual_trigger = optc1_program_manual_trigger, 1561 .setup_manual_trigger = optc1_setup_manual_trigger, 1562 .get_hw_timing = optc1_get_hw_timing, 1563 }; 1564 1565 void dcn10_timing_generator_init(struct optc *optc1) 1566 { 1567 optc1->base.funcs = &dcn10_tg_funcs; 1568 1569 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1570 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1571 1572 optc1->min_h_blank = 32; 1573 optc1->min_v_blank = 3; 1574 optc1->min_v_blank_interlace = 5; 1575 optc1->min_h_sync_width = 4; 1576 optc1->min_v_sync_width = 1; 1577 } 1578 1579 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1580 * 1581 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1582 * containter rate. 1583 * 1584 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1585 * halved to maintain the correct pixel rate. 1586 * 1587 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1588 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1589 * 1590 */ 1591 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1592 { 1593 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1594 1595 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1596 && !timing->dsc_cfg.ycbcr422_simple); 1597 return two_pix; 1598 } 1599 1600