1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 optc1->orginal_patched_timing = patched_crtc_timing; 169 170 /* Load horizontal timing */ 171 172 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 173 REG_SET(OTG_H_TOTAL, 0, 174 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 175 176 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 177 REG_UPDATE_2(OTG_H_SYNC_A, 178 OTG_H_SYNC_A_START, 0, 179 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 180 181 /* blank_start = line end - front porch */ 182 asic_blank_start = patched_crtc_timing.h_total - 183 patched_crtc_timing.h_front_porch; 184 185 /* blank_end = blank_start - active */ 186 asic_blank_end = asic_blank_start - 187 patched_crtc_timing.h_border_right - 188 patched_crtc_timing.h_addressable - 189 patched_crtc_timing.h_border_left; 190 191 REG_UPDATE_2(OTG_H_BLANK_START_END, 192 OTG_H_BLANK_START, asic_blank_start, 193 OTG_H_BLANK_END, asic_blank_end); 194 195 /* h_sync polarity */ 196 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 197 0 : 1; 198 199 REG_UPDATE(OTG_H_SYNC_A_CNTL, 200 OTG_H_SYNC_A_POL, h_sync_polarity); 201 202 v_total = patched_crtc_timing.v_total - 1; 203 204 REG_SET(OTG_V_TOTAL, 0, 205 OTG_V_TOTAL, v_total); 206 207 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 208 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 209 */ 210 REG_SET(OTG_V_TOTAL_MAX, 0, 211 OTG_V_TOTAL_MAX, v_total); 212 REG_SET(OTG_V_TOTAL_MIN, 0, 213 OTG_V_TOTAL_MIN, v_total); 214 215 /* v_sync_start = 0, v_sync_end = v_sync_width */ 216 v_sync_end = patched_crtc_timing.v_sync_width; 217 218 REG_UPDATE_2(OTG_V_SYNC_A, 219 OTG_V_SYNC_A_START, 0, 220 OTG_V_SYNC_A_END, v_sync_end); 221 222 /* blank_start = frame end - front porch */ 223 asic_blank_start = patched_crtc_timing.v_total - 224 patched_crtc_timing.v_front_porch; 225 226 /* blank_end = blank_start - active */ 227 asic_blank_end = asic_blank_start - 228 patched_crtc_timing.v_border_bottom - 229 patched_crtc_timing.v_addressable - 230 patched_crtc_timing.v_border_top; 231 232 REG_UPDATE_2(OTG_V_BLANK_START_END, 233 OTG_V_BLANK_START, asic_blank_start, 234 OTG_V_BLANK_END, asic_blank_end); 235 236 /* v_sync polarity */ 237 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 238 0 : 1; 239 240 REG_UPDATE(OTG_V_SYNC_A_CNTL, 241 OTG_V_SYNC_A_POL, v_sync_polarity); 242 243 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 244 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 245 optc1->signal == SIGNAL_TYPE_EDP) { 246 start_point = 1; 247 if (patched_crtc_timing.flags.INTERLACE == 1) 248 field_num = 1; 249 } 250 251 /* Interlace */ 252 if (REG(OTG_INTERLACE_CONTROL)) { 253 if (patched_crtc_timing.flags.INTERLACE == 1) 254 REG_UPDATE(OTG_INTERLACE_CONTROL, 255 OTG_INTERLACE_ENABLE, 1); 256 else 257 REG_UPDATE(OTG_INTERLACE_CONTROL, 258 OTG_INTERLACE_ENABLE, 0); 259 } 260 261 /* VTG enable set to 0 first VInit */ 262 REG_UPDATE(CONTROL, 263 VTG0_ENABLE, 0); 264 265 /* original code is using VTG offset to address OTG reg, seems wrong */ 266 REG_UPDATE_2(OTG_CONTROL, 267 OTG_START_POINT_CNTL, start_point, 268 OTG_FIELD_NUMBER_CNTL, field_num); 269 270 optc->funcs->program_global_sync(optc, 271 vready_offset, 272 vstartup_start, 273 vupdate_offset, 274 vupdate_width); 275 276 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true); 277 278 /* TODO 279 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 280 * program_horz_count_by_2 281 * for DVI 30bpp mode, 0 otherwise 282 * program_horz_count_by_2(optc, &patched_crtc_timing); 283 */ 284 285 /* Enable stereo - only when we need to pack 3D frame. Other types 286 * of stereo handled in explicit call 287 */ 288 289 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 290 h_div = H_TIMING_DIV_BY2; 291 292 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { 293 uint32_t data_fmt = 0; 294 295 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 296 data_fmt = 1; 297 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 298 data_fmt = 2; 299 300 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 301 } 302 303 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 304 if (optc1->opp_count == 4) 305 h_div = H_TIMING_DIV_BY4; 306 307 REG_UPDATE(OTG_H_TIMING_CNTL, 308 OTG_H_TIMING_DIV_MODE, h_div); 309 } else { 310 REG_UPDATE(OTG_H_TIMING_CNTL, 311 OTG_H_TIMING_DIV_BY2, h_div); 312 } 313 } 314 315 void optc1_set_vtg_params(struct timing_generator *optc, 316 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2) 317 { 318 struct dc_crtc_timing patched_crtc_timing; 319 uint32_t asic_blank_end; 320 uint32_t v_init; 321 uint32_t v_fp2 = 0; 322 int32_t vertical_line_start; 323 324 struct optc *optc1 = DCN10TG_FROM_TG(optc); 325 326 patched_crtc_timing = *dc_crtc_timing; 327 apply_front_porch_workaround(&patched_crtc_timing); 328 329 /* VCOUNT_INIT is the start of blank */ 330 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 331 332 /* end of blank = v_init - active */ 333 asic_blank_end = v_init - 334 patched_crtc_timing.v_border_bottom - 335 patched_crtc_timing.v_addressable - 336 patched_crtc_timing.v_border_top; 337 338 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 339 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 340 if (vertical_line_start < 0) 341 v_fp2 = -vertical_line_start; 342 343 /* Interlace */ 344 if (REG(OTG_INTERLACE_CONTROL)) { 345 if (patched_crtc_timing.flags.INTERLACE == 1) { 346 v_init = v_init / 2; 347 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 348 v_fp2 = v_fp2 / 2; 349 } 350 } 351 352 if (program_fp2) 353 REG_UPDATE_2(CONTROL, 354 VTG0_FP2, v_fp2, 355 VTG0_VCOUNT_INIT, v_init); 356 else 357 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); 358 } 359 360 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 361 { 362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 363 364 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 365 366 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 367 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 368 } 369 370 /** 371 * optc1_set_timing_double_buffer() - DRR double buffering control 372 * 373 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 374 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 375 * 376 * Options: any time, start of frame, dp start of frame (range timing) 377 */ 378 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 379 { 380 struct optc *optc1 = DCN10TG_FROM_TG(optc); 381 uint32_t mode = enable ? 2 : 0; 382 383 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 384 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 385 } 386 387 /** 388 * unblank_crtc 389 * Call ASIC Control Object to UnBlank CRTC. 390 */ 391 static void optc1_unblank_crtc(struct timing_generator *optc) 392 { 393 struct optc *optc1 = DCN10TG_FROM_TG(optc); 394 395 REG_UPDATE_2(OTG_BLANK_CONTROL, 396 OTG_BLANK_DATA_EN, 0, 397 OTG_BLANK_DE_MODE, 0); 398 399 /* W/A for automated testing 400 * Automated testing will fail underflow test as there 401 * sporadic underflows which occur during the optc blank 402 * sequence. As a w/a, clear underflow on unblank. 403 * This prevents the failure, but will not mask actual 404 * underflow that affect real use cases. 405 */ 406 optc1_clear_optc_underflow(optc); 407 } 408 409 /** 410 * blank_crtc 411 * Call ASIC Control Object to Blank CRTC. 412 */ 413 414 static void optc1_blank_crtc(struct timing_generator *optc) 415 { 416 struct optc *optc1 = DCN10TG_FROM_TG(optc); 417 418 REG_UPDATE_2(OTG_BLANK_CONTROL, 419 OTG_BLANK_DATA_EN, 1, 420 OTG_BLANK_DE_MODE, 0); 421 422 optc1_set_blank_data_double_buffer(optc, false); 423 } 424 425 void optc1_set_blank(struct timing_generator *optc, 426 bool enable_blanking) 427 { 428 if (enable_blanking) 429 optc1_blank_crtc(optc); 430 else 431 optc1_unblank_crtc(optc); 432 } 433 434 bool optc1_is_blanked(struct timing_generator *optc) 435 { 436 struct optc *optc1 = DCN10TG_FROM_TG(optc); 437 uint32_t blank_en; 438 uint32_t blank_state; 439 440 REG_GET_2(OTG_BLANK_CONTROL, 441 OTG_BLANK_DATA_EN, &blank_en, 442 OTG_CURRENT_BLANK_STATE, &blank_state); 443 444 return blank_en && blank_state; 445 } 446 447 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 448 { 449 struct optc *optc1 = DCN10TG_FROM_TG(optc); 450 451 if (enable) { 452 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 453 OPTC_INPUT_CLK_EN, 1, 454 OPTC_INPUT_CLK_GATE_DIS, 1); 455 456 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 457 OPTC_INPUT_CLK_ON, 1, 458 1, 1000); 459 460 /* Enable clock */ 461 REG_UPDATE_2(OTG_CLOCK_CONTROL, 462 OTG_CLOCK_EN, 1, 463 OTG_CLOCK_GATE_DIS, 1); 464 REG_WAIT(OTG_CLOCK_CONTROL, 465 OTG_CLOCK_ON, 1, 466 1, 1000); 467 } else { 468 469 //last chance to clear underflow, otherwise, it will always there due to clock is off. 470 if (optc->funcs->is_optc_underflow_occurred(optc) == true) 471 optc->funcs->clear_optc_underflow(optc); 472 473 REG_UPDATE_2(OTG_CLOCK_CONTROL, 474 OTG_CLOCK_GATE_DIS, 0, 475 OTG_CLOCK_EN, 0); 476 477 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 478 OPTC_INPUT_CLK_GATE_DIS, 0, 479 OPTC_INPUT_CLK_EN, 0); 480 } 481 } 482 483 /** 484 * Enable CRTC 485 * Enable CRTC - call ASIC Control Object to enable Timing generator. 486 */ 487 static bool optc1_enable_crtc(struct timing_generator *optc) 488 { 489 /* TODO FPGA wait for answer 490 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 491 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 492 */ 493 struct optc *optc1 = DCN10TG_FROM_TG(optc); 494 495 /* opp instance for OTG. For DCN1.0, ODM is remoed. 496 * OPP and OPTC should 1:1 mapping 497 */ 498 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 499 OPTC_SRC_SEL, optc->inst); 500 501 /* VTG enable first is for HW workaround */ 502 REG_UPDATE(CONTROL, 503 VTG0_ENABLE, 1); 504 505 REG_SEQ_START(); 506 507 /* Enable CRTC */ 508 REG_UPDATE_2(OTG_CONTROL, 509 OTG_DISABLE_POINT_CNTL, 3, 510 OTG_MASTER_EN, 1); 511 512 REG_SEQ_SUBMIT(); 513 REG_SEQ_WAIT_DONE(); 514 515 return true; 516 } 517 518 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 519 bool optc1_disable_crtc(struct timing_generator *optc) 520 { 521 struct optc *optc1 = DCN10TG_FROM_TG(optc); 522 523 /* disable otg request until end of the first line 524 * in the vertical blank region 525 */ 526 REG_UPDATE_2(OTG_CONTROL, 527 OTG_DISABLE_POINT_CNTL, 3, 528 OTG_MASTER_EN, 0); 529 530 REG_UPDATE(CONTROL, 531 VTG0_ENABLE, 0); 532 533 /* CRTC disabled, so disable clock. */ 534 REG_WAIT(OTG_CLOCK_CONTROL, 535 OTG_BUSY, 0, 536 1, 100000); 537 538 return true; 539 } 540 541 542 void optc1_program_blank_color( 543 struct timing_generator *optc, 544 const struct tg_color *black_color) 545 { 546 struct optc *optc1 = DCN10TG_FROM_TG(optc); 547 548 REG_SET_3(OTG_BLACK_COLOR, 0, 549 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 550 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 551 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 552 } 553 554 bool optc1_validate_timing( 555 struct timing_generator *optc, 556 const struct dc_crtc_timing *timing) 557 { 558 uint32_t v_blank; 559 uint32_t h_blank; 560 uint32_t min_v_blank; 561 struct optc *optc1 = DCN10TG_FROM_TG(optc); 562 563 ASSERT(timing != NULL); 564 565 v_blank = (timing->v_total - timing->v_addressable - 566 timing->v_border_top - timing->v_border_bottom); 567 568 h_blank = (timing->h_total - timing->h_addressable - 569 timing->h_border_right - 570 timing->h_border_left); 571 572 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 573 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 574 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 575 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 576 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 577 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 578 return false; 579 580 /* Temporarily blocking interlacing mode until it's supported */ 581 if (timing->flags.INTERLACE == 1) 582 return false; 583 584 /* Check maximum number of pixels supported by Timing Generator 585 * (Currently will never fail, in order to fail needs display which 586 * needs more than 8192 horizontal and 587 * more than 8192 vertical total pixels) 588 */ 589 if (timing->h_total > optc1->max_h_total || 590 timing->v_total > optc1->max_v_total) 591 return false; 592 593 594 if (h_blank < optc1->min_h_blank) 595 return false; 596 597 if (timing->h_sync_width < optc1->min_h_sync_width || 598 timing->v_sync_width < optc1->min_v_sync_width) 599 return false; 600 601 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 602 603 if (v_blank < min_v_blank) 604 return false; 605 606 return true; 607 608 } 609 610 /* 611 * get_vblank_counter 612 * 613 * @brief 614 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 615 * holds the counter of frames. 616 * 617 * @param 618 * struct timing_generator *optc - [in] timing generator which controls the 619 * desired CRTC 620 * 621 * @return 622 * Counter of frames, which should equal to number of vblanks. 623 */ 624 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 625 { 626 struct optc *optc1 = DCN10TG_FROM_TG(optc); 627 uint32_t frame_count; 628 629 REG_GET(OTG_STATUS_FRAME_COUNT, 630 OTG_FRAME_COUNT, &frame_count); 631 632 return frame_count; 633 } 634 635 void optc1_lock(struct timing_generator *optc) 636 { 637 struct optc *optc1 = DCN10TG_FROM_TG(optc); 638 uint32_t regval = 0; 639 640 regval = REG_READ(OTG_CONTROL); 641 642 /* otg is not running, do not need to be locked */ 643 if ((regval & 0x1) == 0x0) 644 return; 645 646 REG_SET(OTG_GLOBAL_CONTROL0, 0, 647 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 648 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 649 OTG_MASTER_UPDATE_LOCK, 1); 650 651 /* Should be fast, status does not update on maximus */ 652 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 653 654 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 655 UPDATE_LOCK_STATUS, 1, 656 1, 10); 657 } 658 } 659 660 void optc1_unlock(struct timing_generator *optc) 661 { 662 struct optc *optc1 = DCN10TG_FROM_TG(optc); 663 664 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 665 OTG_MASTER_UPDATE_LOCK, 0); 666 } 667 668 bool optc1_is_locked(struct timing_generator *optc) 669 { 670 struct optc *optc1 = DCN10TG_FROM_TG(optc); 671 uint32_t locked; 672 673 REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked); 674 675 return (locked == 1); 676 } 677 678 void optc1_get_position(struct timing_generator *optc, 679 struct crtc_position *position) 680 { 681 struct optc *optc1 = DCN10TG_FROM_TG(optc); 682 683 REG_GET_2(OTG_STATUS_POSITION, 684 OTG_HORZ_COUNT, &position->horizontal_count, 685 OTG_VERT_COUNT, &position->vertical_count); 686 687 REG_GET(OTG_NOM_VERT_POSITION, 688 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 689 } 690 691 bool optc1_is_counter_moving(struct timing_generator *optc) 692 { 693 struct crtc_position position1, position2; 694 695 optc->funcs->get_position(optc, &position1); 696 optc->funcs->get_position(optc, &position2); 697 698 if (position1.horizontal_count == position2.horizontal_count && 699 position1.vertical_count == position2.vertical_count) 700 return false; 701 else 702 return true; 703 } 704 705 bool optc1_did_triggered_reset_occur( 706 struct timing_generator *optc) 707 { 708 struct optc *optc1 = DCN10TG_FROM_TG(optc); 709 uint32_t occurred_force, occurred_vsync; 710 711 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 712 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 713 714 REG_GET(OTG_VERT_SYNC_CONTROL, 715 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 716 717 return occurred_vsync != 0 || occurred_force != 0; 718 } 719 720 void optc1_disable_reset_trigger(struct timing_generator *optc) 721 { 722 struct optc *optc1 = DCN10TG_FROM_TG(optc); 723 724 REG_WRITE(OTG_TRIGA_CNTL, 0); 725 726 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 727 OTG_FORCE_COUNT_NOW_CLEAR, 1); 728 729 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 730 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 731 } 732 733 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 734 { 735 struct optc *optc1 = DCN10TG_FROM_TG(optc); 736 uint32_t falling_edge; 737 738 REG_GET(OTG_V_SYNC_A_CNTL, 739 OTG_V_SYNC_A_POL, &falling_edge); 740 741 if (falling_edge) 742 REG_SET_3(OTG_TRIGA_CNTL, 0, 743 /* vsync signal from selected OTG pipe based 744 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 745 */ 746 OTG_TRIGA_SOURCE_SELECT, 20, 747 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 748 /* always detect falling edge */ 749 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 750 else 751 REG_SET_3(OTG_TRIGA_CNTL, 0, 752 /* vsync signal from selected OTG pipe based 753 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 754 */ 755 OTG_TRIGA_SOURCE_SELECT, 20, 756 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 757 /* always detect rising edge */ 758 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 759 760 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 761 /* force H count to H_TOTAL and V count to V_TOTAL in 762 * progressive mode and V_TOTAL-1 in interlaced mode 763 */ 764 OTG_FORCE_COUNT_NOW_MODE, 2); 765 } 766 767 void optc1_enable_crtc_reset( 768 struct timing_generator *optc, 769 int source_tg_inst, 770 struct crtc_trigger_info *crtc_tp) 771 { 772 struct optc *optc1 = DCN10TG_FROM_TG(optc); 773 uint32_t falling_edge = 0; 774 uint32_t rising_edge = 0; 775 776 switch (crtc_tp->event) { 777 778 case CRTC_EVENT_VSYNC_RISING: 779 rising_edge = 1; 780 break; 781 782 case CRTC_EVENT_VSYNC_FALLING: 783 falling_edge = 1; 784 break; 785 } 786 787 REG_SET_4(OTG_TRIGA_CNTL, 0, 788 /* vsync signal from selected OTG pipe based 789 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 790 */ 791 OTG_TRIGA_SOURCE_SELECT, 20, 792 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 793 /* always detect falling edge */ 794 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 795 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 796 797 switch (crtc_tp->delay) { 798 case TRIGGER_DELAY_NEXT_LINE: 799 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 800 OTG_AUTO_FORCE_VSYNC_MODE, 1); 801 break; 802 case TRIGGER_DELAY_NEXT_PIXEL: 803 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 804 /* force H count to H_TOTAL and V count to V_TOTAL in 805 * progressive mode and V_TOTAL-1 in interlaced mode 806 */ 807 OTG_FORCE_COUNT_NOW_MODE, 2); 808 break; 809 } 810 } 811 812 void optc1_wait_for_state(struct timing_generator *optc, 813 enum crtc_state state) 814 { 815 struct optc *optc1 = DCN10TG_FROM_TG(optc); 816 817 switch (state) { 818 case CRTC_STATE_VBLANK: 819 REG_WAIT(OTG_STATUS, 820 OTG_V_BLANK, 1, 821 1, 100000); /* 1 vupdate at 10hz */ 822 break; 823 824 case CRTC_STATE_VACTIVE: 825 REG_WAIT(OTG_STATUS, 826 OTG_V_ACTIVE_DISP, 1, 827 1, 100000); /* 1 vupdate at 10hz */ 828 break; 829 830 default: 831 break; 832 } 833 } 834 835 void optc1_set_early_control( 836 struct timing_generator *optc, 837 uint32_t early_cntl) 838 { 839 /* asic design change, do not need this control 840 * empty for share caller logic 841 */ 842 } 843 844 845 void optc1_set_static_screen_control( 846 struct timing_generator *optc, 847 uint32_t event_triggers, 848 uint32_t num_frames) 849 { 850 struct optc *optc1 = DCN10TG_FROM_TG(optc); 851 852 // By register spec, it only takes 8 bit value 853 if (num_frames > 0xFF) 854 num_frames = 0xFF; 855 856 /* Bit 8 is no longer applicable in RV for PSR case, 857 * set bit 8 to 0 if given 858 */ 859 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 860 != 0) 861 event_triggers = event_triggers & 862 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 863 864 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 865 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 866 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 867 } 868 869 static void optc1_setup_manual_trigger(struct timing_generator *optc) 870 { 871 struct optc *optc1 = DCN10TG_FROM_TG(optc); 872 873 REG_SET(OTG_GLOBAL_CONTROL2, 0, 874 MANUAL_FLOW_CONTROL_SEL, optc->inst); 875 876 REG_SET_8(OTG_TRIGA_CNTL, 0, 877 OTG_TRIGA_SOURCE_SELECT, 22, 878 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 879 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 880 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 881 OTG_TRIGA_POLARITY_SELECT, 0, 882 OTG_TRIGA_FREQUENCY_SELECT, 0, 883 OTG_TRIGA_DELAY, 0, 884 OTG_TRIGA_CLEAR, 1); 885 } 886 887 static void optc1_program_manual_trigger(struct timing_generator *optc) 888 { 889 struct optc *optc1 = DCN10TG_FROM_TG(optc); 890 891 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 892 MANUAL_FLOW_CONTROL, 1); 893 894 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 895 MANUAL_FLOW_CONTROL, 0); 896 } 897 898 899 /** 900 ***************************************************************************** 901 * Function: set_drr 902 * 903 * @brief 904 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 905 * 906 ***************************************************************************** 907 */ 908 void optc1_set_drr( 909 struct timing_generator *optc, 910 const struct drr_params *params) 911 { 912 struct optc *optc1 = DCN10TG_FROM_TG(optc); 913 914 if (params != NULL && 915 params->vertical_total_max > 0 && 916 params->vertical_total_min > 0) { 917 918 if (params->vertical_total_mid != 0) { 919 920 REG_SET(OTG_V_TOTAL_MID, 0, 921 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 922 923 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 924 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 925 OTG_VTOTAL_MID_FRAME_NUM, 926 (uint8_t)params->vertical_total_mid_frame_num); 927 928 } 929 930 REG_SET(OTG_V_TOTAL_MAX, 0, 931 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 932 933 REG_SET(OTG_V_TOTAL_MIN, 0, 934 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 935 936 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 937 OTG_V_TOTAL_MIN_SEL, 1, 938 OTG_V_TOTAL_MAX_SEL, 1, 939 OTG_FORCE_LOCK_ON_EVENT, 0, 940 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 941 OTG_SET_V_TOTAL_MIN_MASK, 0); 942 943 // Setup manual flow control for EOF via TRIG_A 944 optc->funcs->setup_manual_trigger(optc); 945 946 } else { 947 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 948 OTG_SET_V_TOTAL_MIN_MASK, 0, 949 OTG_V_TOTAL_MIN_SEL, 0, 950 OTG_V_TOTAL_MAX_SEL, 0, 951 OTG_FORCE_LOCK_ON_EVENT, 0); 952 953 REG_SET(OTG_V_TOTAL_MIN, 0, 954 OTG_V_TOTAL_MIN, 0); 955 956 REG_SET(OTG_V_TOTAL_MAX, 0, 957 OTG_V_TOTAL_MAX, 0); 958 } 959 } 960 961 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) 962 { 963 struct optc *optc1 = DCN10TG_FROM_TG(optc); 964 965 REG_SET(OTG_V_TOTAL_MAX, 0, 966 OTG_V_TOTAL_MAX, vtotal_max); 967 968 REG_SET(OTG_V_TOTAL_MIN, 0, 969 OTG_V_TOTAL_MIN, vtotal_min); 970 } 971 972 static void optc1_set_test_pattern( 973 struct timing_generator *optc, 974 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 975 * because this is not DP-specific (which is probably somewhere in DP 976 * encoder) */ 977 enum controller_dp_test_pattern test_pattern, 978 enum dc_color_depth color_depth) 979 { 980 struct optc *optc1 = DCN10TG_FROM_TG(optc); 981 enum test_pattern_color_format bit_depth; 982 enum test_pattern_dyn_range dyn_range; 983 enum test_pattern_mode mode; 984 uint32_t pattern_mask; 985 uint32_t pattern_data; 986 /* color ramp generator mixes 16-bits color */ 987 uint32_t src_bpc = 16; 988 /* requested bpc */ 989 uint32_t dst_bpc; 990 uint32_t index; 991 /* RGB values of the color bars. 992 * Produce two RGB colors: RGB0 - white (all Fs) 993 * and RGB1 - black (all 0s) 994 * (three RGB components for two colors) 995 */ 996 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 997 0x0000, 0x0000}; 998 /* dest color (converted to the specified color format) */ 999 uint16_t dst_color[6]; 1000 uint32_t inc_base; 1001 1002 /* translate to bit depth */ 1003 switch (color_depth) { 1004 case COLOR_DEPTH_666: 1005 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 1006 break; 1007 case COLOR_DEPTH_888: 1008 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1009 break; 1010 case COLOR_DEPTH_101010: 1011 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 1012 break; 1013 case COLOR_DEPTH_121212: 1014 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 1015 break; 1016 default: 1017 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1018 break; 1019 } 1020 1021 switch (test_pattern) { 1022 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 1023 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 1024 { 1025 dyn_range = (test_pattern == 1026 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 1027 TEST_PATTERN_DYN_RANGE_CEA : 1028 TEST_PATTERN_DYN_RANGE_VESA); 1029 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1030 1031 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1032 OTG_TEST_PATTERN_VRES, 6, 1033 OTG_TEST_PATTERN_HRES, 6); 1034 1035 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1036 OTG_TEST_PATTERN_EN, 1, 1037 OTG_TEST_PATTERN_MODE, mode, 1038 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1039 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1040 } 1041 break; 1042 1043 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1044 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1045 { 1046 mode = (test_pattern == 1047 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1048 TEST_PATTERN_MODE_VERTICALBARS : 1049 TEST_PATTERN_MODE_HORIZONTALBARS); 1050 1051 switch (bit_depth) { 1052 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1053 dst_bpc = 6; 1054 break; 1055 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1056 dst_bpc = 8; 1057 break; 1058 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1059 dst_bpc = 10; 1060 break; 1061 default: 1062 dst_bpc = 8; 1063 break; 1064 } 1065 1066 /* adjust color to the required colorFormat */ 1067 for (index = 0; index < 6; index++) { 1068 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1069 * (srcBpc - dstBpc); 1070 */ 1071 dst_color[index] = 1072 src_color[index] >> (src_bpc - dst_bpc); 1073 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1074 * lowest 6 are hardwired to ZERO 1075 * color bits should be left aligned aligned to MSB 1076 * XXXXXXXXXX000000 for 10 bit, 1077 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1078 */ 1079 dst_color[index] <<= (16 - dst_bpc); 1080 } 1081 1082 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1083 1084 /* We have to write the mask before data, similar to pipeline. 1085 * For example, for 8 bpc, if we want RGB0 to be magenta, 1086 * and RGB1 to be cyan, 1087 * we need to make 7 writes: 1088 * MASK DATA 1089 * 000001 00000000 00000000 set mask to R0 1090 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1091 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1092 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1093 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1094 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1095 * 100000 11111111 00000000 B1 255, 0xFF00 1096 * 1097 * we will make a loop of 6 in which we prepare the mask, 1098 * then write, then prepare the color for next write. 1099 * first iteration will write mask only, 1100 * but each next iteration color prepared in 1101 * previous iteration will be written within new mask, 1102 * the last component will written separately, 1103 * mask is not changing between 6th and 7th write 1104 * and color will be prepared by last iteration 1105 */ 1106 1107 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1108 * is B1, G1, R1, B0, G0, R0 1109 */ 1110 pattern_data = 0; 1111 for (index = 0; index < 6; index++) { 1112 /* prepare color mask, first write PATTERN_DATA 1113 * will have all zeros 1114 */ 1115 pattern_mask = (1 << index); 1116 1117 /* write color component */ 1118 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1119 OTG_TEST_PATTERN_MASK, pattern_mask, 1120 OTG_TEST_PATTERN_DATA, pattern_data); 1121 1122 /* prepare next color component, 1123 * will be written in the next iteration 1124 */ 1125 pattern_data = dst_color[index]; 1126 } 1127 /* write last color component, 1128 * it's been already prepared in the loop 1129 */ 1130 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1131 OTG_TEST_PATTERN_MASK, pattern_mask, 1132 OTG_TEST_PATTERN_DATA, pattern_data); 1133 1134 /* enable test pattern */ 1135 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1136 OTG_TEST_PATTERN_EN, 1, 1137 OTG_TEST_PATTERN_MODE, mode, 1138 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1139 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1140 } 1141 break; 1142 1143 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1144 { 1145 mode = (bit_depth == 1146 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1147 TEST_PATTERN_MODE_DUALRAMP_RGB : 1148 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1149 1150 switch (bit_depth) { 1151 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1152 dst_bpc = 6; 1153 break; 1154 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1155 dst_bpc = 8; 1156 break; 1157 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1158 dst_bpc = 10; 1159 break; 1160 default: 1161 dst_bpc = 8; 1162 break; 1163 } 1164 1165 /* increment for the first ramp for one color gradation 1166 * 1 gradation for 6-bit color is 2^10 1167 * gradations in 16-bit color 1168 */ 1169 inc_base = (src_bpc - dst_bpc); 1170 1171 switch (bit_depth) { 1172 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1173 { 1174 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1175 OTG_TEST_PATTERN_INC0, inc_base, 1176 OTG_TEST_PATTERN_INC1, 0, 1177 OTG_TEST_PATTERN_HRES, 6, 1178 OTG_TEST_PATTERN_VRES, 6, 1179 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1180 } 1181 break; 1182 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1183 { 1184 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1185 OTG_TEST_PATTERN_INC0, inc_base, 1186 OTG_TEST_PATTERN_INC1, 0, 1187 OTG_TEST_PATTERN_HRES, 8, 1188 OTG_TEST_PATTERN_VRES, 6, 1189 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1190 } 1191 break; 1192 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1193 { 1194 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1195 OTG_TEST_PATTERN_INC0, inc_base, 1196 OTG_TEST_PATTERN_INC1, inc_base + 2, 1197 OTG_TEST_PATTERN_HRES, 8, 1198 OTG_TEST_PATTERN_VRES, 5, 1199 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1200 } 1201 break; 1202 default: 1203 break; 1204 } 1205 1206 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1207 1208 /* enable test pattern */ 1209 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1210 1211 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1212 OTG_TEST_PATTERN_EN, 1, 1213 OTG_TEST_PATTERN_MODE, mode, 1214 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1215 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1216 } 1217 break; 1218 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1219 { 1220 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1221 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1222 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1223 } 1224 break; 1225 default: 1226 break; 1227 1228 } 1229 } 1230 1231 void optc1_get_crtc_scanoutpos( 1232 struct timing_generator *optc, 1233 uint32_t *v_blank_start, 1234 uint32_t *v_blank_end, 1235 uint32_t *h_position, 1236 uint32_t *v_position) 1237 { 1238 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1239 struct crtc_position position; 1240 1241 REG_GET_2(OTG_V_BLANK_START_END, 1242 OTG_V_BLANK_START, v_blank_start, 1243 OTG_V_BLANK_END, v_blank_end); 1244 1245 optc1_get_position(optc, &position); 1246 1247 *h_position = position.horizontal_count; 1248 *v_position = position.vertical_count; 1249 } 1250 1251 static void optc1_enable_stereo(struct timing_generator *optc, 1252 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1253 { 1254 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1255 1256 if (flags) { 1257 uint32_t stereo_en; 1258 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1259 1260 if (flags->PROGRAM_STEREO) 1261 REG_UPDATE_3(OTG_STEREO_CONTROL, 1262 OTG_STEREO_EN, stereo_en, 1263 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1264 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1265 1266 if (flags->PROGRAM_POLARITY) 1267 REG_UPDATE(OTG_STEREO_CONTROL, 1268 OTG_STEREO_EYE_FLAG_POLARITY, 1269 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1270 1271 if (flags->DISABLE_STEREO_DP_SYNC) 1272 REG_UPDATE(OTG_STEREO_CONTROL, 1273 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1274 1275 if (flags->PROGRAM_STEREO) 1276 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1277 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1278 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1279 1280 } 1281 } 1282 1283 void optc1_program_stereo(struct timing_generator *optc, 1284 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1285 { 1286 if (flags->PROGRAM_STEREO) 1287 optc1_enable_stereo(optc, timing, flags); 1288 else 1289 optc1_disable_stereo(optc); 1290 } 1291 1292 1293 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1294 { 1295 bool ret = false; 1296 uint32_t left_eye = 0; 1297 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1298 1299 REG_GET(OTG_STEREO_STATUS, 1300 OTG_STEREO_CURRENT_EYE, &left_eye); 1301 if (left_eye == 1) 1302 ret = true; 1303 else 1304 ret = false; 1305 1306 return ret; 1307 } 1308 1309 bool optc1_get_hw_timing(struct timing_generator *tg, 1310 struct dc_crtc_timing *hw_crtc_timing) 1311 { 1312 struct dcn_otg_state s = {0}; 1313 1314 if (tg == NULL || hw_crtc_timing == NULL) 1315 return false; 1316 1317 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1318 1319 hw_crtc_timing->h_total = s.h_total + 1; 1320 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1321 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1322 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1323 1324 hw_crtc_timing->v_total = s.v_total + 1; 1325 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1326 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1327 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1328 1329 return true; 1330 } 1331 1332 1333 void optc1_read_otg_state(struct optc *optc1, 1334 struct dcn_otg_state *s) 1335 { 1336 REG_GET(OTG_CONTROL, 1337 OTG_MASTER_EN, &s->otg_enabled); 1338 1339 REG_GET_2(OTG_V_BLANK_START_END, 1340 OTG_V_BLANK_START, &s->v_blank_start, 1341 OTG_V_BLANK_END, &s->v_blank_end); 1342 1343 REG_GET(OTG_V_SYNC_A_CNTL, 1344 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1345 1346 REG_GET(OTG_V_TOTAL, 1347 OTG_V_TOTAL, &s->v_total); 1348 1349 REG_GET(OTG_V_TOTAL_MAX, 1350 OTG_V_TOTAL_MAX, &s->v_total_max); 1351 1352 REG_GET(OTG_V_TOTAL_MIN, 1353 OTG_V_TOTAL_MIN, &s->v_total_min); 1354 1355 REG_GET(OTG_V_TOTAL_CONTROL, 1356 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1357 1358 REG_GET(OTG_V_TOTAL_CONTROL, 1359 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1360 1361 REG_GET_2(OTG_V_SYNC_A, 1362 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1363 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1364 1365 REG_GET_2(OTG_H_BLANK_START_END, 1366 OTG_H_BLANK_START, &s->h_blank_start, 1367 OTG_H_BLANK_END, &s->h_blank_end); 1368 1369 REG_GET_2(OTG_H_SYNC_A, 1370 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1371 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1372 1373 REG_GET(OTG_H_SYNC_A_CNTL, 1374 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1375 1376 REG_GET(OTG_H_TOTAL, 1377 OTG_H_TOTAL, &s->h_total); 1378 1379 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1380 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1381 1382 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1383 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1384 1385 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1386 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1387 } 1388 1389 bool optc1_get_otg_active_size(struct timing_generator *optc, 1390 uint32_t *otg_active_width, 1391 uint32_t *otg_active_height) 1392 { 1393 uint32_t otg_enabled; 1394 uint32_t v_blank_start; 1395 uint32_t v_blank_end; 1396 uint32_t h_blank_start; 1397 uint32_t h_blank_end; 1398 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1399 1400 1401 REG_GET(OTG_CONTROL, 1402 OTG_MASTER_EN, &otg_enabled); 1403 1404 if (otg_enabled == 0) 1405 return false; 1406 1407 REG_GET_2(OTG_V_BLANK_START_END, 1408 OTG_V_BLANK_START, &v_blank_start, 1409 OTG_V_BLANK_END, &v_blank_end); 1410 1411 REG_GET_2(OTG_H_BLANK_START_END, 1412 OTG_H_BLANK_START, &h_blank_start, 1413 OTG_H_BLANK_END, &h_blank_end); 1414 1415 *otg_active_width = v_blank_start - v_blank_end; 1416 *otg_active_height = h_blank_start - h_blank_end; 1417 return true; 1418 } 1419 1420 void optc1_clear_optc_underflow(struct timing_generator *optc) 1421 { 1422 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1423 1424 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1425 } 1426 1427 void optc1_tg_init(struct timing_generator *optc) 1428 { 1429 optc1_set_blank_data_double_buffer(optc, true); 1430 optc1_set_timing_double_buffer(optc, true); 1431 optc1_clear_optc_underflow(optc); 1432 } 1433 1434 bool optc1_is_tg_enabled(struct timing_generator *optc) 1435 { 1436 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1437 uint32_t otg_enabled = 0; 1438 1439 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1440 1441 return (otg_enabled != 0); 1442 1443 } 1444 1445 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1446 { 1447 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1448 uint32_t underflow_occurred = 0; 1449 1450 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1451 OPTC_UNDERFLOW_OCCURRED_STATUS, 1452 &underflow_occurred); 1453 1454 return (underflow_occurred == 1); 1455 } 1456 1457 bool optc1_configure_crc(struct timing_generator *optc, 1458 const struct crc_params *params) 1459 { 1460 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1461 1462 /* Cannot configure crc on a CRTC that is disabled */ 1463 if (!optc1_is_tg_enabled(optc)) 1464 return false; 1465 1466 REG_WRITE(OTG_CRC_CNTL, 0); 1467 1468 if (!params->enable) 1469 return true; 1470 1471 /* Program frame boundaries */ 1472 /* Window A x axis start and end. */ 1473 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1474 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1475 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1476 1477 /* Window A y axis start and end. */ 1478 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1479 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1480 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1481 1482 /* Window B x axis start and end. */ 1483 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1484 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1485 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1486 1487 /* Window B y axis start and end. */ 1488 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1489 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1490 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1491 1492 /* Set crc mode and selection, and enable. Only using CRC0*/ 1493 REG_UPDATE_3(OTG_CRC_CNTL, 1494 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1495 OTG_CRC0_SELECT, params->selection, 1496 OTG_CRC_EN, 1); 1497 1498 return true; 1499 } 1500 1501 bool optc1_get_crc(struct timing_generator *optc, 1502 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1503 { 1504 uint32_t field = 0; 1505 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1506 1507 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1508 1509 /* Early return if CRC is not enabled for this CRTC */ 1510 if (!field) 1511 return false; 1512 1513 REG_GET_2(OTG_CRC0_DATA_RG, 1514 CRC0_R_CR, r_cr, 1515 CRC0_G_Y, g_y); 1516 1517 REG_GET(OTG_CRC0_DATA_B, 1518 CRC0_B_CB, b_cb); 1519 1520 return true; 1521 } 1522 1523 static const struct timing_generator_funcs dcn10_tg_funcs = { 1524 .validate_timing = optc1_validate_timing, 1525 .program_timing = optc1_program_timing, 1526 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1527 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1528 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1529 .program_global_sync = optc1_program_global_sync, 1530 .enable_crtc = optc1_enable_crtc, 1531 .disable_crtc = optc1_disable_crtc, 1532 /* used by enable_timing_synchronization. Not need for FPGA */ 1533 .is_counter_moving = optc1_is_counter_moving, 1534 .get_position = optc1_get_position, 1535 .get_frame_count = optc1_get_vblank_counter, 1536 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1537 .get_otg_active_size = optc1_get_otg_active_size, 1538 .set_early_control = optc1_set_early_control, 1539 /* used by enable_timing_synchronization. Not need for FPGA */ 1540 .wait_for_state = optc1_wait_for_state, 1541 .set_blank = optc1_set_blank, 1542 .is_blanked = optc1_is_blanked, 1543 .set_blank_color = optc1_program_blank_color, 1544 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1545 .enable_reset_trigger = optc1_enable_reset_trigger, 1546 .enable_crtc_reset = optc1_enable_crtc_reset, 1547 .disable_reset_trigger = optc1_disable_reset_trigger, 1548 .lock = optc1_lock, 1549 .is_locked = optc1_is_locked, 1550 .unlock = optc1_unlock, 1551 .enable_optc_clock = optc1_enable_optc_clock, 1552 .set_drr = optc1_set_drr, 1553 .get_last_used_drr_vtotal = NULL, 1554 .set_static_screen_control = optc1_set_static_screen_control, 1555 .set_test_pattern = optc1_set_test_pattern, 1556 .program_stereo = optc1_program_stereo, 1557 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1558 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1559 .tg_init = optc1_tg_init, 1560 .is_tg_enabled = optc1_is_tg_enabled, 1561 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1562 .clear_optc_underflow = optc1_clear_optc_underflow, 1563 .get_crc = optc1_get_crc, 1564 .configure_crc = optc1_configure_crc, 1565 .set_vtg_params = optc1_set_vtg_params, 1566 .program_manual_trigger = optc1_program_manual_trigger, 1567 .setup_manual_trigger = optc1_setup_manual_trigger, 1568 .get_hw_timing = optc1_get_hw_timing, 1569 }; 1570 1571 void dcn10_timing_generator_init(struct optc *optc1) 1572 { 1573 optc1->base.funcs = &dcn10_tg_funcs; 1574 1575 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1576 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1577 1578 optc1->min_h_blank = 32; 1579 optc1->min_v_blank = 3; 1580 optc1->min_v_blank_interlace = 5; 1581 optc1->min_h_sync_width = 4; 1582 optc1->min_v_sync_width = 1; 1583 } 1584 1585 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1586 * 1587 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1588 * containter rate. 1589 * 1590 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1591 * halved to maintain the correct pixel rate. 1592 * 1593 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1594 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1595 * 1596 */ 1597 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1598 { 1599 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1600 1601 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1602 && !timing->dsc_cfg.ycbcr422_simple); 1603 return two_pix; 1604 } 1605 1606