1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 289 h_div = H_TIMING_DIV_BY2; 290 291 REG_UPDATE(OTG_H_TIMING_CNTL, 292 OTG_H_TIMING_DIV_BY2, h_div); 293 } 294 295 void optc1_set_vtg_params(struct timing_generator *optc, 296 const struct dc_crtc_timing *dc_crtc_timing) 297 { 298 struct dc_crtc_timing patched_crtc_timing; 299 uint32_t asic_blank_end; 300 uint32_t v_init; 301 uint32_t v_fp2 = 0; 302 int32_t vertical_line_start; 303 304 struct optc *optc1 = DCN10TG_FROM_TG(optc); 305 306 patched_crtc_timing = *dc_crtc_timing; 307 apply_front_porch_workaround(&patched_crtc_timing); 308 309 /* VCOUNT_INIT is the start of blank */ 310 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 311 312 /* end of blank = v_init - active */ 313 asic_blank_end = v_init - 314 patched_crtc_timing.v_border_bottom - 315 patched_crtc_timing.v_addressable - 316 patched_crtc_timing.v_border_top; 317 318 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 319 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 320 if (vertical_line_start < 0) 321 v_fp2 = -vertical_line_start; 322 323 /* Interlace */ 324 if (REG(OTG_INTERLACE_CONTROL)) { 325 if (patched_crtc_timing.flags.INTERLACE == 1) { 326 v_init = v_init / 2; 327 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 328 v_fp2 = v_fp2 / 2; 329 } 330 } 331 332 REG_UPDATE_2(CONTROL, 333 VTG0_FP2, v_fp2, 334 VTG0_VCOUNT_INIT, v_init); 335 } 336 337 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 338 { 339 struct optc *optc1 = DCN10TG_FROM_TG(optc); 340 341 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 342 343 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 344 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 345 } 346 347 /** 348 * optc1_set_timing_double_buffer() - DRR double buffering control 349 * 350 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 351 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 352 * 353 * Options: any time, start of frame, dp start of frame (range timing) 354 */ 355 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 356 { 357 struct optc *optc1 = DCN10TG_FROM_TG(optc); 358 uint32_t mode = enable ? 2 : 0; 359 360 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 361 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 362 } 363 364 /** 365 * unblank_crtc 366 * Call ASIC Control Object to UnBlank CRTC. 367 */ 368 static void optc1_unblank_crtc(struct timing_generator *optc) 369 { 370 struct optc *optc1 = DCN10TG_FROM_TG(optc); 371 372 REG_UPDATE_2(OTG_BLANK_CONTROL, 373 OTG_BLANK_DATA_EN, 0, 374 OTG_BLANK_DE_MODE, 0); 375 376 /* W/A for automated testing 377 * Automated testing will fail underflow test as there 378 * sporadic underflows which occur during the optc blank 379 * sequence. As a w/a, clear underflow on unblank. 380 * This prevents the failure, but will not mask actual 381 * underflow that affect real use cases. 382 */ 383 optc1_clear_optc_underflow(optc); 384 } 385 386 /** 387 * blank_crtc 388 * Call ASIC Control Object to Blank CRTC. 389 */ 390 391 static void optc1_blank_crtc(struct timing_generator *optc) 392 { 393 struct optc *optc1 = DCN10TG_FROM_TG(optc); 394 395 REG_UPDATE_2(OTG_BLANK_CONTROL, 396 OTG_BLANK_DATA_EN, 1, 397 OTG_BLANK_DE_MODE, 0); 398 399 optc1_set_blank_data_double_buffer(optc, false); 400 } 401 402 void optc1_set_blank(struct timing_generator *optc, 403 bool enable_blanking) 404 { 405 if (enable_blanking) 406 optc1_blank_crtc(optc); 407 else 408 optc1_unblank_crtc(optc); 409 } 410 411 bool optc1_is_blanked(struct timing_generator *optc) 412 { 413 struct optc *optc1 = DCN10TG_FROM_TG(optc); 414 uint32_t blank_en; 415 uint32_t blank_state; 416 417 REG_GET_2(OTG_BLANK_CONTROL, 418 OTG_BLANK_DATA_EN, &blank_en, 419 OTG_CURRENT_BLANK_STATE, &blank_state); 420 421 return blank_en && blank_state; 422 } 423 424 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 425 { 426 struct optc *optc1 = DCN10TG_FROM_TG(optc); 427 428 if (enable) { 429 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 430 OPTC_INPUT_CLK_EN, 1, 431 OPTC_INPUT_CLK_GATE_DIS, 1); 432 433 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 434 OPTC_INPUT_CLK_ON, 1, 435 1, 1000); 436 437 /* Enable clock */ 438 REG_UPDATE_2(OTG_CLOCK_CONTROL, 439 OTG_CLOCK_EN, 1, 440 OTG_CLOCK_GATE_DIS, 1); 441 REG_WAIT(OTG_CLOCK_CONTROL, 442 OTG_CLOCK_ON, 1, 443 1, 1000); 444 } else { 445 REG_UPDATE_2(OTG_CLOCK_CONTROL, 446 OTG_CLOCK_GATE_DIS, 0, 447 OTG_CLOCK_EN, 0); 448 449 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 450 OPTC_INPUT_CLK_GATE_DIS, 0, 451 OPTC_INPUT_CLK_EN, 0); 452 } 453 } 454 455 /** 456 * Enable CRTC 457 * Enable CRTC - call ASIC Control Object to enable Timing generator. 458 */ 459 static bool optc1_enable_crtc(struct timing_generator *optc) 460 { 461 /* TODO FPGA wait for answer 462 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 463 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 464 */ 465 struct optc *optc1 = DCN10TG_FROM_TG(optc); 466 467 /* opp instance for OTG. For DCN1.0, ODM is remoed. 468 * OPP and OPTC should 1:1 mapping 469 */ 470 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 471 OPTC_SRC_SEL, optc->inst); 472 473 /* VTG enable first is for HW workaround */ 474 REG_UPDATE(CONTROL, 475 VTG0_ENABLE, 1); 476 477 REG_SEQ_START(); 478 479 /* Enable CRTC */ 480 REG_UPDATE_2(OTG_CONTROL, 481 OTG_DISABLE_POINT_CNTL, 3, 482 OTG_MASTER_EN, 1); 483 484 REG_SEQ_SUBMIT(); 485 REG_SEQ_WAIT_DONE(); 486 487 return true; 488 } 489 490 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 491 bool optc1_disable_crtc(struct timing_generator *optc) 492 { 493 struct optc *optc1 = DCN10TG_FROM_TG(optc); 494 495 /* disable otg request until end of the first line 496 * in the vertical blank region 497 */ 498 REG_UPDATE_2(OTG_CONTROL, 499 OTG_DISABLE_POINT_CNTL, 3, 500 OTG_MASTER_EN, 0); 501 502 REG_UPDATE(CONTROL, 503 VTG0_ENABLE, 0); 504 505 /* CRTC disabled, so disable clock. */ 506 REG_WAIT(OTG_CLOCK_CONTROL, 507 OTG_BUSY, 0, 508 1, 100000); 509 510 return true; 511 } 512 513 514 void optc1_program_blank_color( 515 struct timing_generator *optc, 516 const struct tg_color *black_color) 517 { 518 struct optc *optc1 = DCN10TG_FROM_TG(optc); 519 520 REG_SET_3(OTG_BLACK_COLOR, 0, 521 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 522 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 523 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 524 } 525 526 bool optc1_validate_timing( 527 struct timing_generator *optc, 528 const struct dc_crtc_timing *timing) 529 { 530 uint32_t v_blank; 531 uint32_t h_blank; 532 uint32_t min_v_blank; 533 struct optc *optc1 = DCN10TG_FROM_TG(optc); 534 535 ASSERT(timing != NULL); 536 537 v_blank = (timing->v_total - timing->v_addressable - 538 timing->v_border_top - timing->v_border_bottom); 539 540 h_blank = (timing->h_total - timing->h_addressable - 541 timing->h_border_right - 542 timing->h_border_left); 543 544 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 545 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 546 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 547 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 548 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 549 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 550 return false; 551 552 /* Temporarily blocking interlacing mode until it's supported */ 553 if (timing->flags.INTERLACE == 1) 554 return false; 555 556 /* Check maximum number of pixels supported by Timing Generator 557 * (Currently will never fail, in order to fail needs display which 558 * needs more than 8192 horizontal and 559 * more than 8192 vertical total pixels) 560 */ 561 if (timing->h_total > optc1->max_h_total || 562 timing->v_total > optc1->max_v_total) 563 return false; 564 565 566 if (h_blank < optc1->min_h_blank) 567 return false; 568 569 if (timing->h_sync_width < optc1->min_h_sync_width || 570 timing->v_sync_width < optc1->min_v_sync_width) 571 return false; 572 573 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 574 575 if (v_blank < min_v_blank) 576 return false; 577 578 return true; 579 580 } 581 582 /* 583 * get_vblank_counter 584 * 585 * @brief 586 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 587 * holds the counter of frames. 588 * 589 * @param 590 * struct timing_generator *optc - [in] timing generator which controls the 591 * desired CRTC 592 * 593 * @return 594 * Counter of frames, which should equal to number of vblanks. 595 */ 596 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 597 { 598 struct optc *optc1 = DCN10TG_FROM_TG(optc); 599 uint32_t frame_count; 600 601 REG_GET(OTG_STATUS_FRAME_COUNT, 602 OTG_FRAME_COUNT, &frame_count); 603 604 return frame_count; 605 } 606 607 void optc1_lock(struct timing_generator *optc) 608 { 609 struct optc *optc1 = DCN10TG_FROM_TG(optc); 610 uint32_t regval = 0; 611 612 regval = REG_READ(OTG_CONTROL); 613 614 /* otg is not running, do not need to be locked */ 615 if ((regval & 0x1) == 0x0) 616 return; 617 618 REG_SET(OTG_GLOBAL_CONTROL0, 0, 619 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 620 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 621 OTG_MASTER_UPDATE_LOCK, 1); 622 623 /* Should be fast, status does not update on maximus */ 624 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 625 626 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 627 UPDATE_LOCK_STATUS, 1, 628 1, 10); 629 } 630 } 631 632 void optc1_unlock(struct timing_generator *optc) 633 { 634 struct optc *optc1 = DCN10TG_FROM_TG(optc); 635 636 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 637 OTG_MASTER_UPDATE_LOCK, 0); 638 } 639 640 void optc1_get_position(struct timing_generator *optc, 641 struct crtc_position *position) 642 { 643 struct optc *optc1 = DCN10TG_FROM_TG(optc); 644 645 REG_GET_2(OTG_STATUS_POSITION, 646 OTG_HORZ_COUNT, &position->horizontal_count, 647 OTG_VERT_COUNT, &position->vertical_count); 648 649 REG_GET(OTG_NOM_VERT_POSITION, 650 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 651 } 652 653 bool optc1_is_counter_moving(struct timing_generator *optc) 654 { 655 struct crtc_position position1, position2; 656 657 optc->funcs->get_position(optc, &position1); 658 optc->funcs->get_position(optc, &position2); 659 660 if (position1.horizontal_count == position2.horizontal_count && 661 position1.vertical_count == position2.vertical_count) 662 return false; 663 else 664 return true; 665 } 666 667 bool optc1_did_triggered_reset_occur( 668 struct timing_generator *optc) 669 { 670 struct optc *optc1 = DCN10TG_FROM_TG(optc); 671 uint32_t occurred_force, occurred_vsync; 672 673 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 674 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 675 676 REG_GET(OTG_VERT_SYNC_CONTROL, 677 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 678 679 return occurred_vsync != 0 || occurred_force != 0; 680 } 681 682 void optc1_disable_reset_trigger(struct timing_generator *optc) 683 { 684 struct optc *optc1 = DCN10TG_FROM_TG(optc); 685 686 REG_WRITE(OTG_TRIGA_CNTL, 0); 687 688 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 689 OTG_FORCE_COUNT_NOW_CLEAR, 1); 690 691 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 692 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 693 } 694 695 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 696 { 697 struct optc *optc1 = DCN10TG_FROM_TG(optc); 698 uint32_t falling_edge; 699 700 REG_GET(OTG_V_SYNC_A_CNTL, 701 OTG_V_SYNC_A_POL, &falling_edge); 702 703 if (falling_edge) 704 REG_SET_3(OTG_TRIGA_CNTL, 0, 705 /* vsync signal from selected OTG pipe based 706 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 707 */ 708 OTG_TRIGA_SOURCE_SELECT, 20, 709 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 710 /* always detect falling edge */ 711 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 712 else 713 REG_SET_3(OTG_TRIGA_CNTL, 0, 714 /* vsync signal from selected OTG pipe based 715 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 716 */ 717 OTG_TRIGA_SOURCE_SELECT, 20, 718 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 719 /* always detect rising edge */ 720 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 721 722 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 723 /* force H count to H_TOTAL and V count to V_TOTAL in 724 * progressive mode and V_TOTAL-1 in interlaced mode 725 */ 726 OTG_FORCE_COUNT_NOW_MODE, 2); 727 } 728 729 void optc1_enable_crtc_reset( 730 struct timing_generator *optc, 731 int source_tg_inst, 732 struct crtc_trigger_info *crtc_tp) 733 { 734 struct optc *optc1 = DCN10TG_FROM_TG(optc); 735 uint32_t falling_edge = 0; 736 uint32_t rising_edge = 0; 737 738 switch (crtc_tp->event) { 739 740 case CRTC_EVENT_VSYNC_RISING: 741 rising_edge = 1; 742 break; 743 744 case CRTC_EVENT_VSYNC_FALLING: 745 falling_edge = 1; 746 break; 747 } 748 749 REG_SET_4(OTG_TRIGA_CNTL, 0, 750 /* vsync signal from selected OTG pipe based 751 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 752 */ 753 OTG_TRIGA_SOURCE_SELECT, 20, 754 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 755 /* always detect falling edge */ 756 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 757 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 758 759 switch (crtc_tp->delay) { 760 case TRIGGER_DELAY_NEXT_LINE: 761 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 762 OTG_AUTO_FORCE_VSYNC_MODE, 1); 763 break; 764 case TRIGGER_DELAY_NEXT_PIXEL: 765 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 766 /* force H count to H_TOTAL and V count to V_TOTAL in 767 * progressive mode and V_TOTAL-1 in interlaced mode 768 */ 769 OTG_FORCE_COUNT_NOW_MODE, 2); 770 break; 771 } 772 } 773 774 void optc1_wait_for_state(struct timing_generator *optc, 775 enum crtc_state state) 776 { 777 struct optc *optc1 = DCN10TG_FROM_TG(optc); 778 779 switch (state) { 780 case CRTC_STATE_VBLANK: 781 REG_WAIT(OTG_STATUS, 782 OTG_V_BLANK, 1, 783 1, 100000); /* 1 vupdate at 10hz */ 784 break; 785 786 case CRTC_STATE_VACTIVE: 787 REG_WAIT(OTG_STATUS, 788 OTG_V_ACTIVE_DISP, 1, 789 1, 100000); /* 1 vupdate at 10hz */ 790 break; 791 792 default: 793 break; 794 } 795 } 796 797 void optc1_set_early_control( 798 struct timing_generator *optc, 799 uint32_t early_cntl) 800 { 801 /* asic design change, do not need this control 802 * empty for share caller logic 803 */ 804 } 805 806 807 void optc1_set_static_screen_control( 808 struct timing_generator *optc, 809 uint32_t event_triggers, 810 uint32_t num_frames) 811 { 812 struct optc *optc1 = DCN10TG_FROM_TG(optc); 813 814 // By register spec, it only takes 8 bit value 815 if (num_frames > 0xFF) 816 num_frames = 0xFF; 817 818 /* Bit 8 is no longer applicable in RV for PSR case, 819 * set bit 8 to 0 if given 820 */ 821 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 822 != 0) 823 event_triggers = event_triggers & 824 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 825 826 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 827 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 828 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 829 } 830 831 void optc1_setup_manual_trigger(struct timing_generator *optc) 832 { 833 struct optc *optc1 = DCN10TG_FROM_TG(optc); 834 835 REG_SET(OTG_GLOBAL_CONTROL2, 0, 836 MANUAL_FLOW_CONTROL_SEL, optc->inst); 837 838 REG_SET_8(OTG_TRIGA_CNTL, 0, 839 OTG_TRIGA_SOURCE_SELECT, 22, 840 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 841 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 842 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 843 OTG_TRIGA_POLARITY_SELECT, 0, 844 OTG_TRIGA_FREQUENCY_SELECT, 0, 845 OTG_TRIGA_DELAY, 0, 846 OTG_TRIGA_CLEAR, 1); 847 } 848 849 void optc1_program_manual_trigger(struct timing_generator *optc) 850 { 851 struct optc *optc1 = DCN10TG_FROM_TG(optc); 852 853 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 854 MANUAL_FLOW_CONTROL, 1); 855 856 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 857 MANUAL_FLOW_CONTROL, 0); 858 } 859 860 861 /** 862 ***************************************************************************** 863 * Function: set_drr 864 * 865 * @brief 866 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 867 * 868 ***************************************************************************** 869 */ 870 void optc1_set_drr( 871 struct timing_generator *optc, 872 const struct drr_params *params) 873 { 874 struct optc *optc1 = DCN10TG_FROM_TG(optc); 875 876 if (params != NULL && 877 params->vertical_total_max > 0 && 878 params->vertical_total_min > 0) { 879 880 if (params->vertical_total_mid != 0) { 881 882 REG_SET(OTG_V_TOTAL_MID, 0, 883 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 884 885 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 886 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 887 OTG_VTOTAL_MID_FRAME_NUM, 888 (uint8_t)params->vertical_total_mid_frame_num); 889 890 } 891 892 REG_SET(OTG_V_TOTAL_MAX, 0, 893 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 894 895 REG_SET(OTG_V_TOTAL_MIN, 0, 896 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 897 898 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 899 OTG_V_TOTAL_MIN_SEL, 1, 900 OTG_V_TOTAL_MAX_SEL, 1, 901 OTG_FORCE_LOCK_ON_EVENT, 0, 902 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 903 OTG_SET_V_TOTAL_MIN_MASK, 0); 904 905 // Setup manual flow control for EOF via TRIG_A 906 optc->funcs->setup_manual_trigger(optc); 907 908 } else { 909 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 910 OTG_SET_V_TOTAL_MIN_MASK, 0, 911 OTG_V_TOTAL_MIN_SEL, 0, 912 OTG_V_TOTAL_MAX_SEL, 0, 913 OTG_FORCE_LOCK_ON_EVENT, 0); 914 915 REG_SET(OTG_V_TOTAL_MIN, 0, 916 OTG_V_TOTAL_MIN, 0); 917 918 REG_SET(OTG_V_TOTAL_MAX, 0, 919 OTG_V_TOTAL_MAX, 0); 920 } 921 } 922 923 static void optc1_set_test_pattern( 924 struct timing_generator *optc, 925 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 926 * because this is not DP-specific (which is probably somewhere in DP 927 * encoder) */ 928 enum controller_dp_test_pattern test_pattern, 929 enum dc_color_depth color_depth) 930 { 931 struct optc *optc1 = DCN10TG_FROM_TG(optc); 932 enum test_pattern_color_format bit_depth; 933 enum test_pattern_dyn_range dyn_range; 934 enum test_pattern_mode mode; 935 uint32_t pattern_mask; 936 uint32_t pattern_data; 937 /* color ramp generator mixes 16-bits color */ 938 uint32_t src_bpc = 16; 939 /* requested bpc */ 940 uint32_t dst_bpc; 941 uint32_t index; 942 /* RGB values of the color bars. 943 * Produce two RGB colors: RGB0 - white (all Fs) 944 * and RGB1 - black (all 0s) 945 * (three RGB components for two colors) 946 */ 947 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 948 0x0000, 0x0000}; 949 /* dest color (converted to the specified color format) */ 950 uint16_t dst_color[6]; 951 uint32_t inc_base; 952 953 /* translate to bit depth */ 954 switch (color_depth) { 955 case COLOR_DEPTH_666: 956 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 957 break; 958 case COLOR_DEPTH_888: 959 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 960 break; 961 case COLOR_DEPTH_101010: 962 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 963 break; 964 case COLOR_DEPTH_121212: 965 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 966 break; 967 default: 968 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 969 break; 970 } 971 972 switch (test_pattern) { 973 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 974 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 975 { 976 dyn_range = (test_pattern == 977 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 978 TEST_PATTERN_DYN_RANGE_CEA : 979 TEST_PATTERN_DYN_RANGE_VESA); 980 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 981 982 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 983 OTG_TEST_PATTERN_VRES, 6, 984 OTG_TEST_PATTERN_HRES, 6); 985 986 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 987 OTG_TEST_PATTERN_EN, 1, 988 OTG_TEST_PATTERN_MODE, mode, 989 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 990 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 991 } 992 break; 993 994 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 995 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 996 { 997 mode = (test_pattern == 998 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 999 TEST_PATTERN_MODE_VERTICALBARS : 1000 TEST_PATTERN_MODE_HORIZONTALBARS); 1001 1002 switch (bit_depth) { 1003 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1004 dst_bpc = 6; 1005 break; 1006 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1007 dst_bpc = 8; 1008 break; 1009 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1010 dst_bpc = 10; 1011 break; 1012 default: 1013 dst_bpc = 8; 1014 break; 1015 } 1016 1017 /* adjust color to the required colorFormat */ 1018 for (index = 0; index < 6; index++) { 1019 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1020 * (srcBpc - dstBpc); 1021 */ 1022 dst_color[index] = 1023 src_color[index] >> (src_bpc - dst_bpc); 1024 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1025 * lowest 6 are hardwired to ZERO 1026 * color bits should be left aligned aligned to MSB 1027 * XXXXXXXXXX000000 for 10 bit, 1028 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1029 */ 1030 dst_color[index] <<= (16 - dst_bpc); 1031 } 1032 1033 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1034 1035 /* We have to write the mask before data, similar to pipeline. 1036 * For example, for 8 bpc, if we want RGB0 to be magenta, 1037 * and RGB1 to be cyan, 1038 * we need to make 7 writes: 1039 * MASK DATA 1040 * 000001 00000000 00000000 set mask to R0 1041 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1042 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1043 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1044 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1045 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1046 * 100000 11111111 00000000 B1 255, 0xFF00 1047 * 1048 * we will make a loop of 6 in which we prepare the mask, 1049 * then write, then prepare the color for next write. 1050 * first iteration will write mask only, 1051 * but each next iteration color prepared in 1052 * previous iteration will be written within new mask, 1053 * the last component will written separately, 1054 * mask is not changing between 6th and 7th write 1055 * and color will be prepared by last iteration 1056 */ 1057 1058 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1059 * is B1, G1, R1, B0, G0, R0 1060 */ 1061 pattern_data = 0; 1062 for (index = 0; index < 6; index++) { 1063 /* prepare color mask, first write PATTERN_DATA 1064 * will have all zeros 1065 */ 1066 pattern_mask = (1 << index); 1067 1068 /* write color component */ 1069 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1070 OTG_TEST_PATTERN_MASK, pattern_mask, 1071 OTG_TEST_PATTERN_DATA, pattern_data); 1072 1073 /* prepare next color component, 1074 * will be written in the next iteration 1075 */ 1076 pattern_data = dst_color[index]; 1077 } 1078 /* write last color component, 1079 * it's been already prepared in the loop 1080 */ 1081 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1082 OTG_TEST_PATTERN_MASK, pattern_mask, 1083 OTG_TEST_PATTERN_DATA, pattern_data); 1084 1085 /* enable test pattern */ 1086 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1087 OTG_TEST_PATTERN_EN, 1, 1088 OTG_TEST_PATTERN_MODE, mode, 1089 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1090 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1091 } 1092 break; 1093 1094 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1095 { 1096 mode = (bit_depth == 1097 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1098 TEST_PATTERN_MODE_DUALRAMP_RGB : 1099 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1100 1101 switch (bit_depth) { 1102 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1103 dst_bpc = 6; 1104 break; 1105 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1106 dst_bpc = 8; 1107 break; 1108 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1109 dst_bpc = 10; 1110 break; 1111 default: 1112 dst_bpc = 8; 1113 break; 1114 } 1115 1116 /* increment for the first ramp for one color gradation 1117 * 1 gradation for 6-bit color is 2^10 1118 * gradations in 16-bit color 1119 */ 1120 inc_base = (src_bpc - dst_bpc); 1121 1122 switch (bit_depth) { 1123 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1124 { 1125 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1126 OTG_TEST_PATTERN_INC0, inc_base, 1127 OTG_TEST_PATTERN_INC1, 0, 1128 OTG_TEST_PATTERN_HRES, 6, 1129 OTG_TEST_PATTERN_VRES, 6, 1130 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1131 } 1132 break; 1133 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1134 { 1135 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1136 OTG_TEST_PATTERN_INC0, inc_base, 1137 OTG_TEST_PATTERN_INC1, 0, 1138 OTG_TEST_PATTERN_HRES, 8, 1139 OTG_TEST_PATTERN_VRES, 6, 1140 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1141 } 1142 break; 1143 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1144 { 1145 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1146 OTG_TEST_PATTERN_INC0, inc_base, 1147 OTG_TEST_PATTERN_INC1, inc_base + 2, 1148 OTG_TEST_PATTERN_HRES, 8, 1149 OTG_TEST_PATTERN_VRES, 5, 1150 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1151 } 1152 break; 1153 default: 1154 break; 1155 } 1156 1157 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1158 1159 /* enable test pattern */ 1160 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1161 1162 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1163 OTG_TEST_PATTERN_EN, 1, 1164 OTG_TEST_PATTERN_MODE, mode, 1165 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1166 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1167 } 1168 break; 1169 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1170 { 1171 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1172 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1173 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1174 } 1175 break; 1176 default: 1177 break; 1178 1179 } 1180 } 1181 1182 void optc1_get_crtc_scanoutpos( 1183 struct timing_generator *optc, 1184 uint32_t *v_blank_start, 1185 uint32_t *v_blank_end, 1186 uint32_t *h_position, 1187 uint32_t *v_position) 1188 { 1189 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1190 struct crtc_position position; 1191 1192 REG_GET_2(OTG_V_BLANK_START_END, 1193 OTG_V_BLANK_START, v_blank_start, 1194 OTG_V_BLANK_END, v_blank_end); 1195 1196 optc1_get_position(optc, &position); 1197 1198 *h_position = position.horizontal_count; 1199 *v_position = position.vertical_count; 1200 } 1201 1202 static void optc1_enable_stereo(struct timing_generator *optc, 1203 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1204 { 1205 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1206 1207 if (flags) { 1208 uint32_t stereo_en; 1209 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1210 1211 if (flags->PROGRAM_STEREO) 1212 REG_UPDATE_3(OTG_STEREO_CONTROL, 1213 OTG_STEREO_EN, stereo_en, 1214 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1215 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1216 1217 if (flags->PROGRAM_POLARITY) 1218 REG_UPDATE(OTG_STEREO_CONTROL, 1219 OTG_STEREO_EYE_FLAG_POLARITY, 1220 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1221 1222 if (flags->DISABLE_STEREO_DP_SYNC) 1223 REG_UPDATE(OTG_STEREO_CONTROL, 1224 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1225 1226 if (flags->PROGRAM_STEREO) 1227 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1228 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1229 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1230 1231 } 1232 } 1233 1234 void optc1_program_stereo(struct timing_generator *optc, 1235 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1236 { 1237 if (flags->PROGRAM_STEREO) 1238 optc1_enable_stereo(optc, timing, flags); 1239 else 1240 optc1_disable_stereo(optc); 1241 } 1242 1243 1244 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1245 { 1246 bool ret = false; 1247 uint32_t left_eye = 0; 1248 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1249 1250 REG_GET(OTG_STEREO_STATUS, 1251 OTG_STEREO_CURRENT_EYE, &left_eye); 1252 if (left_eye == 1) 1253 ret = true; 1254 else 1255 ret = false; 1256 1257 return ret; 1258 } 1259 1260 bool optc1_get_hw_timing(struct timing_generator *tg, 1261 struct dc_crtc_timing *hw_crtc_timing) 1262 { 1263 struct dcn_otg_state s = {0}; 1264 1265 if (tg == NULL || hw_crtc_timing == NULL) 1266 return false; 1267 1268 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1269 1270 hw_crtc_timing->h_total = s.h_total + 1; 1271 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1272 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1273 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1274 1275 hw_crtc_timing->v_total = s.v_total + 1; 1276 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1277 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1278 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1279 1280 return true; 1281 } 1282 1283 1284 void optc1_read_otg_state(struct optc *optc1, 1285 struct dcn_otg_state *s) 1286 { 1287 REG_GET(OTG_CONTROL, 1288 OTG_MASTER_EN, &s->otg_enabled); 1289 1290 REG_GET_2(OTG_V_BLANK_START_END, 1291 OTG_V_BLANK_START, &s->v_blank_start, 1292 OTG_V_BLANK_END, &s->v_blank_end); 1293 1294 REG_GET(OTG_V_SYNC_A_CNTL, 1295 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1296 1297 REG_GET(OTG_V_TOTAL, 1298 OTG_V_TOTAL, &s->v_total); 1299 1300 REG_GET(OTG_V_TOTAL_MAX, 1301 OTG_V_TOTAL_MAX, &s->v_total_max); 1302 1303 REG_GET(OTG_V_TOTAL_MIN, 1304 OTG_V_TOTAL_MIN, &s->v_total_min); 1305 1306 REG_GET(OTG_V_TOTAL_CONTROL, 1307 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1308 1309 REG_GET(OTG_V_TOTAL_CONTROL, 1310 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1311 1312 REG_GET_2(OTG_V_SYNC_A, 1313 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1314 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1315 1316 REG_GET_2(OTG_H_BLANK_START_END, 1317 OTG_H_BLANK_START, &s->h_blank_start, 1318 OTG_H_BLANK_END, &s->h_blank_end); 1319 1320 REG_GET_2(OTG_H_SYNC_A, 1321 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1322 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1323 1324 REG_GET(OTG_H_SYNC_A_CNTL, 1325 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1326 1327 REG_GET(OTG_H_TOTAL, 1328 OTG_H_TOTAL, &s->h_total); 1329 1330 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1331 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1332 } 1333 1334 bool optc1_get_otg_active_size(struct timing_generator *optc, 1335 uint32_t *otg_active_width, 1336 uint32_t *otg_active_height) 1337 { 1338 uint32_t otg_enabled; 1339 uint32_t v_blank_start; 1340 uint32_t v_blank_end; 1341 uint32_t h_blank_start; 1342 uint32_t h_blank_end; 1343 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1344 1345 1346 REG_GET(OTG_CONTROL, 1347 OTG_MASTER_EN, &otg_enabled); 1348 1349 if (otg_enabled == 0) 1350 return false; 1351 1352 REG_GET_2(OTG_V_BLANK_START_END, 1353 OTG_V_BLANK_START, &v_blank_start, 1354 OTG_V_BLANK_END, &v_blank_end); 1355 1356 REG_GET_2(OTG_H_BLANK_START_END, 1357 OTG_H_BLANK_START, &h_blank_start, 1358 OTG_H_BLANK_END, &h_blank_end); 1359 1360 *otg_active_width = v_blank_start - v_blank_end; 1361 *otg_active_height = h_blank_start - h_blank_end; 1362 return true; 1363 } 1364 1365 void optc1_clear_optc_underflow(struct timing_generator *optc) 1366 { 1367 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1368 1369 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1370 } 1371 1372 void optc1_tg_init(struct timing_generator *optc) 1373 { 1374 optc1_set_blank_data_double_buffer(optc, true); 1375 optc1_set_timing_double_buffer(optc, true); 1376 optc1_clear_optc_underflow(optc); 1377 } 1378 1379 bool optc1_is_tg_enabled(struct timing_generator *optc) 1380 { 1381 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1382 uint32_t otg_enabled = 0; 1383 1384 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1385 1386 return (otg_enabled != 0); 1387 1388 } 1389 1390 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1391 { 1392 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1393 uint32_t underflow_occurred = 0; 1394 1395 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1396 OPTC_UNDERFLOW_OCCURRED_STATUS, 1397 &underflow_occurred); 1398 1399 return (underflow_occurred == 1); 1400 } 1401 1402 bool optc1_configure_crc(struct timing_generator *optc, 1403 const struct crc_params *params) 1404 { 1405 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1406 1407 /* Cannot configure crc on a CRTC that is disabled */ 1408 if (!optc1_is_tg_enabled(optc)) 1409 return false; 1410 1411 REG_WRITE(OTG_CRC_CNTL, 0); 1412 1413 if (!params->enable) 1414 return true; 1415 1416 /* Program frame boundaries */ 1417 /* Window A x axis start and end. */ 1418 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1419 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1420 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1421 1422 /* Window A y axis start and end. */ 1423 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1424 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1425 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1426 1427 /* Window B x axis start and end. */ 1428 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1429 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1430 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1431 1432 /* Window B y axis start and end. */ 1433 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1434 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1435 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1436 1437 /* Set crc mode and selection, and enable. Only using CRC0*/ 1438 REG_UPDATE_3(OTG_CRC_CNTL, 1439 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1440 OTG_CRC0_SELECT, params->selection, 1441 OTG_CRC_EN, 1); 1442 1443 return true; 1444 } 1445 1446 bool optc1_get_crc(struct timing_generator *optc, 1447 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1448 { 1449 uint32_t field = 0; 1450 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1451 1452 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1453 1454 /* Early return if CRC is not enabled for this CRTC */ 1455 if (!field) 1456 return false; 1457 1458 REG_GET_2(OTG_CRC0_DATA_RG, 1459 CRC0_R_CR, r_cr, 1460 CRC0_G_Y, g_y); 1461 1462 REG_GET(OTG_CRC0_DATA_B, 1463 CRC0_B_CB, b_cb); 1464 1465 return true; 1466 } 1467 1468 static const struct timing_generator_funcs dcn10_tg_funcs = { 1469 .validate_timing = optc1_validate_timing, 1470 .program_timing = optc1_program_timing, 1471 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1472 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1473 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1474 .program_global_sync = optc1_program_global_sync, 1475 .enable_crtc = optc1_enable_crtc, 1476 .disable_crtc = optc1_disable_crtc, 1477 /* used by enable_timing_synchronization. Not need for FPGA */ 1478 .is_counter_moving = optc1_is_counter_moving, 1479 .get_position = optc1_get_position, 1480 .get_frame_count = optc1_get_vblank_counter, 1481 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1482 .get_otg_active_size = optc1_get_otg_active_size, 1483 .set_early_control = optc1_set_early_control, 1484 /* used by enable_timing_synchronization. Not need for FPGA */ 1485 .wait_for_state = optc1_wait_for_state, 1486 .set_blank = optc1_set_blank, 1487 .is_blanked = optc1_is_blanked, 1488 .set_blank_color = optc1_program_blank_color, 1489 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1490 .enable_reset_trigger = optc1_enable_reset_trigger, 1491 .enable_crtc_reset = optc1_enable_crtc_reset, 1492 .disable_reset_trigger = optc1_disable_reset_trigger, 1493 .lock = optc1_lock, 1494 .unlock = optc1_unlock, 1495 .enable_optc_clock = optc1_enable_optc_clock, 1496 .set_drr = optc1_set_drr, 1497 .set_static_screen_control = optc1_set_static_screen_control, 1498 .set_test_pattern = optc1_set_test_pattern, 1499 .program_stereo = optc1_program_stereo, 1500 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1501 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1502 .tg_init = optc1_tg_init, 1503 .is_tg_enabled = optc1_is_tg_enabled, 1504 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1505 .clear_optc_underflow = optc1_clear_optc_underflow, 1506 .get_crc = optc1_get_crc, 1507 .configure_crc = optc1_configure_crc, 1508 .set_vtg_params = optc1_set_vtg_params, 1509 .program_manual_trigger = optc1_program_manual_trigger, 1510 .setup_manual_trigger = optc1_setup_manual_trigger, 1511 .get_hw_timing = optc1_get_hw_timing, 1512 }; 1513 1514 void dcn10_timing_generator_init(struct optc *optc1) 1515 { 1516 optc1->base.funcs = &dcn10_tg_funcs; 1517 1518 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1519 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1520 1521 optc1->min_h_blank = 32; 1522 optc1->min_v_blank = 3; 1523 optc1->min_v_blank_interlace = 5; 1524 optc1->min_h_sync_width = 8; 1525 optc1->min_v_sync_width = 1; 1526 } 1527 1528 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1529 * 1530 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1531 * containter rate. 1532 * 1533 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1534 * halved to maintain the correct pixel rate. 1535 * 1536 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1537 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1538 * 1539 */ 1540 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1541 { 1542 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1543 1544 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1545 && !timing->dsc_cfg.ycbcr422_simple); 1546 return two_pix; 1547 } 1548 1549