1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 289 h_div = H_TIMING_DIV_BY2; 290 291 REG_UPDATE(OTG_H_TIMING_CNTL, 292 OTG_H_TIMING_DIV_BY2, h_div); 293 } 294 295 void optc1_set_vtg_params(struct timing_generator *optc, 296 const struct dc_crtc_timing *dc_crtc_timing) 297 { 298 struct dc_crtc_timing patched_crtc_timing; 299 uint32_t asic_blank_end; 300 uint32_t v_init; 301 uint32_t v_fp2 = 0; 302 303 struct optc *optc1 = DCN10TG_FROM_TG(optc); 304 305 patched_crtc_timing = *dc_crtc_timing; 306 apply_front_porch_workaround(&patched_crtc_timing); 307 308 /* VCOUNT_INIT is the start of blank */ 309 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 310 311 /* end of blank = v_init - active */ 312 asic_blank_end = v_init - 313 patched_crtc_timing.v_border_bottom - 314 patched_crtc_timing.v_addressable - 315 patched_crtc_timing.v_border_top; 316 317 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 318 if (optc1->vstartup_start > asic_blank_end) 319 v_fp2 = optc1->vstartup_start - asic_blank_end; 320 321 /* Interlace */ 322 if (REG(OTG_INTERLACE_CONTROL)) { 323 if (patched_crtc_timing.flags.INTERLACE == 1) { 324 v_init = v_init / 2; 325 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 326 v_fp2 = v_fp2 / 2; 327 } 328 } 329 330 REG_UPDATE_2(CONTROL, 331 VTG0_FP2, v_fp2, 332 VTG0_VCOUNT_INIT, v_init); 333 } 334 335 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 336 { 337 struct optc *optc1 = DCN10TG_FROM_TG(optc); 338 339 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 340 341 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 342 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 343 } 344 345 /** 346 * unblank_crtc 347 * Call ASIC Control Object to UnBlank CRTC. 348 */ 349 static void optc1_unblank_crtc(struct timing_generator *optc) 350 { 351 struct optc *optc1 = DCN10TG_FROM_TG(optc); 352 353 REG_UPDATE_2(OTG_BLANK_CONTROL, 354 OTG_BLANK_DATA_EN, 0, 355 OTG_BLANK_DE_MODE, 0); 356 357 /* W/A for automated testing 358 * Automated testing will fail underflow test as there 359 * sporadic underflows which occur during the optc blank 360 * sequence. As a w/a, clear underflow on unblank. 361 * This prevents the failure, but will not mask actual 362 * underflow that affect real use cases. 363 */ 364 optc1_clear_optc_underflow(optc); 365 } 366 367 /** 368 * blank_crtc 369 * Call ASIC Control Object to Blank CRTC. 370 */ 371 372 static void optc1_blank_crtc(struct timing_generator *optc) 373 { 374 struct optc *optc1 = DCN10TG_FROM_TG(optc); 375 376 REG_UPDATE_2(OTG_BLANK_CONTROL, 377 OTG_BLANK_DATA_EN, 1, 378 OTG_BLANK_DE_MODE, 0); 379 380 optc1_set_blank_data_double_buffer(optc, false); 381 } 382 383 void optc1_set_blank(struct timing_generator *optc, 384 bool enable_blanking) 385 { 386 if (enable_blanking) 387 optc1_blank_crtc(optc); 388 else 389 optc1_unblank_crtc(optc); 390 } 391 392 bool optc1_is_blanked(struct timing_generator *optc) 393 { 394 struct optc *optc1 = DCN10TG_FROM_TG(optc); 395 uint32_t blank_en; 396 uint32_t blank_state; 397 398 REG_GET_2(OTG_BLANK_CONTROL, 399 OTG_BLANK_DATA_EN, &blank_en, 400 OTG_CURRENT_BLANK_STATE, &blank_state); 401 402 return blank_en && blank_state; 403 } 404 405 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 406 { 407 struct optc *optc1 = DCN10TG_FROM_TG(optc); 408 409 if (enable) { 410 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 411 OPTC_INPUT_CLK_EN, 1, 412 OPTC_INPUT_CLK_GATE_DIS, 1); 413 414 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 415 OPTC_INPUT_CLK_ON, 1, 416 1, 1000); 417 418 /* Enable clock */ 419 REG_UPDATE_2(OTG_CLOCK_CONTROL, 420 OTG_CLOCK_EN, 1, 421 OTG_CLOCK_GATE_DIS, 1); 422 REG_WAIT(OTG_CLOCK_CONTROL, 423 OTG_CLOCK_ON, 1, 424 1, 1000); 425 } else { 426 REG_UPDATE_2(OTG_CLOCK_CONTROL, 427 OTG_CLOCK_GATE_DIS, 0, 428 OTG_CLOCK_EN, 0); 429 430 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 431 OPTC_INPUT_CLK_GATE_DIS, 0, 432 OPTC_INPUT_CLK_EN, 0); 433 } 434 } 435 436 /** 437 * Enable CRTC 438 * Enable CRTC - call ASIC Control Object to enable Timing generator. 439 */ 440 static bool optc1_enable_crtc(struct timing_generator *optc) 441 { 442 /* TODO FPGA wait for answer 443 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 444 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 445 */ 446 struct optc *optc1 = DCN10TG_FROM_TG(optc); 447 448 /* opp instance for OTG. For DCN1.0, ODM is remoed. 449 * OPP and OPTC should 1:1 mapping 450 */ 451 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 452 OPTC_SRC_SEL, optc->inst); 453 454 /* VTG enable first is for HW workaround */ 455 REG_UPDATE(CONTROL, 456 VTG0_ENABLE, 1); 457 458 REG_SEQ_START(); 459 460 /* Enable CRTC */ 461 REG_UPDATE_2(OTG_CONTROL, 462 OTG_DISABLE_POINT_CNTL, 3, 463 OTG_MASTER_EN, 1); 464 465 REG_SEQ_SUBMIT(); 466 REG_SEQ_WAIT_DONE(); 467 468 return true; 469 } 470 471 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 472 bool optc1_disable_crtc(struct timing_generator *optc) 473 { 474 struct optc *optc1 = DCN10TG_FROM_TG(optc); 475 476 /* disable otg request until end of the first line 477 * in the vertical blank region 478 */ 479 REG_UPDATE_2(OTG_CONTROL, 480 OTG_DISABLE_POINT_CNTL, 3, 481 OTG_MASTER_EN, 0); 482 483 REG_UPDATE(CONTROL, 484 VTG0_ENABLE, 0); 485 486 /* CRTC disabled, so disable clock. */ 487 REG_WAIT(OTG_CLOCK_CONTROL, 488 OTG_BUSY, 0, 489 1, 100000); 490 491 return true; 492 } 493 494 495 void optc1_program_blank_color( 496 struct timing_generator *optc, 497 const struct tg_color *black_color) 498 { 499 struct optc *optc1 = DCN10TG_FROM_TG(optc); 500 501 REG_SET_3(OTG_BLACK_COLOR, 0, 502 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 503 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 504 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 505 } 506 507 bool optc1_validate_timing( 508 struct timing_generator *optc, 509 const struct dc_crtc_timing *timing) 510 { 511 uint32_t v_blank; 512 uint32_t h_blank; 513 uint32_t min_v_blank; 514 struct optc *optc1 = DCN10TG_FROM_TG(optc); 515 516 ASSERT(timing != NULL); 517 518 v_blank = (timing->v_total - timing->v_addressable - 519 timing->v_border_top - timing->v_border_bottom); 520 521 h_blank = (timing->h_total - timing->h_addressable - 522 timing->h_border_right - 523 timing->h_border_left); 524 525 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 526 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 527 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 528 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 529 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 530 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 531 return false; 532 533 /* Temporarily blocking interlacing mode until it's supported */ 534 if (timing->flags.INTERLACE == 1) 535 return false; 536 537 /* Check maximum number of pixels supported by Timing Generator 538 * (Currently will never fail, in order to fail needs display which 539 * needs more than 8192 horizontal and 540 * more than 8192 vertical total pixels) 541 */ 542 if (timing->h_total > optc1->max_h_total || 543 timing->v_total > optc1->max_v_total) 544 return false; 545 546 547 if (h_blank < optc1->min_h_blank) 548 return false; 549 550 if (timing->h_sync_width < optc1->min_h_sync_width || 551 timing->v_sync_width < optc1->min_v_sync_width) 552 return false; 553 554 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 555 556 if (v_blank < min_v_blank) 557 return false; 558 559 return true; 560 561 } 562 563 /* 564 * get_vblank_counter 565 * 566 * @brief 567 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 568 * holds the counter of frames. 569 * 570 * @param 571 * struct timing_generator *optc - [in] timing generator which controls the 572 * desired CRTC 573 * 574 * @return 575 * Counter of frames, which should equal to number of vblanks. 576 */ 577 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 578 { 579 struct optc *optc1 = DCN10TG_FROM_TG(optc); 580 uint32_t frame_count; 581 582 REG_GET(OTG_STATUS_FRAME_COUNT, 583 OTG_FRAME_COUNT, &frame_count); 584 585 return frame_count; 586 } 587 588 void optc1_lock(struct timing_generator *optc) 589 { 590 struct optc *optc1 = DCN10TG_FROM_TG(optc); 591 uint32_t regval = 0; 592 593 regval = REG_READ(OTG_CONTROL); 594 595 /* otg is not running, do not need to be locked */ 596 if ((regval & 0x1) == 0x0) 597 return; 598 599 REG_SET(OTG_GLOBAL_CONTROL0, 0, 600 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 601 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 602 OTG_MASTER_UPDATE_LOCK, 1); 603 604 /* Should be fast, status does not update on maximus */ 605 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 606 607 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 608 UPDATE_LOCK_STATUS, 1, 609 1, 10); 610 } 611 } 612 613 void optc1_unlock(struct timing_generator *optc) 614 { 615 struct optc *optc1 = DCN10TG_FROM_TG(optc); 616 617 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 618 OTG_MASTER_UPDATE_LOCK, 0); 619 } 620 621 void optc1_get_position(struct timing_generator *optc, 622 struct crtc_position *position) 623 { 624 struct optc *optc1 = DCN10TG_FROM_TG(optc); 625 626 REG_GET_2(OTG_STATUS_POSITION, 627 OTG_HORZ_COUNT, &position->horizontal_count, 628 OTG_VERT_COUNT, &position->vertical_count); 629 630 REG_GET(OTG_NOM_VERT_POSITION, 631 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 632 } 633 634 bool optc1_is_counter_moving(struct timing_generator *optc) 635 { 636 struct crtc_position position1, position2; 637 638 optc->funcs->get_position(optc, &position1); 639 optc->funcs->get_position(optc, &position2); 640 641 if (position1.horizontal_count == position2.horizontal_count && 642 position1.vertical_count == position2.vertical_count) 643 return false; 644 else 645 return true; 646 } 647 648 bool optc1_did_triggered_reset_occur( 649 struct timing_generator *optc) 650 { 651 struct optc *optc1 = DCN10TG_FROM_TG(optc); 652 uint32_t occurred_force, occurred_vsync; 653 654 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 655 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 656 657 REG_GET(OTG_VERT_SYNC_CONTROL, 658 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 659 660 return occurred_vsync != 0 || occurred_force != 0; 661 } 662 663 void optc1_disable_reset_trigger(struct timing_generator *optc) 664 { 665 struct optc *optc1 = DCN10TG_FROM_TG(optc); 666 667 REG_WRITE(OTG_TRIGA_CNTL, 0); 668 669 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 670 OTG_FORCE_COUNT_NOW_CLEAR, 1); 671 672 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 673 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 674 } 675 676 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 677 { 678 struct optc *optc1 = DCN10TG_FROM_TG(optc); 679 uint32_t falling_edge; 680 681 REG_GET(OTG_V_SYNC_A_CNTL, 682 OTG_V_SYNC_A_POL, &falling_edge); 683 684 if (falling_edge) 685 REG_SET_3(OTG_TRIGA_CNTL, 0, 686 /* vsync signal from selected OTG pipe based 687 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 688 */ 689 OTG_TRIGA_SOURCE_SELECT, 20, 690 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 691 /* always detect falling edge */ 692 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 693 else 694 REG_SET_3(OTG_TRIGA_CNTL, 0, 695 /* vsync signal from selected OTG pipe based 696 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 697 */ 698 OTG_TRIGA_SOURCE_SELECT, 20, 699 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 700 /* always detect rising edge */ 701 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 702 703 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 704 /* force H count to H_TOTAL and V count to V_TOTAL in 705 * progressive mode and V_TOTAL-1 in interlaced mode 706 */ 707 OTG_FORCE_COUNT_NOW_MODE, 2); 708 } 709 710 void optc1_enable_crtc_reset( 711 struct timing_generator *optc, 712 int source_tg_inst, 713 struct crtc_trigger_info *crtc_tp) 714 { 715 struct optc *optc1 = DCN10TG_FROM_TG(optc); 716 uint32_t falling_edge = 0; 717 uint32_t rising_edge = 0; 718 719 switch (crtc_tp->event) { 720 721 case CRTC_EVENT_VSYNC_RISING: 722 rising_edge = 1; 723 break; 724 725 case CRTC_EVENT_VSYNC_FALLING: 726 falling_edge = 1; 727 break; 728 } 729 730 REG_SET_4(OTG_TRIGA_CNTL, 0, 731 /* vsync signal from selected OTG pipe based 732 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 733 */ 734 OTG_TRIGA_SOURCE_SELECT, 20, 735 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 736 /* always detect falling edge */ 737 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 738 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 739 740 switch (crtc_tp->delay) { 741 case TRIGGER_DELAY_NEXT_LINE: 742 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 743 OTG_AUTO_FORCE_VSYNC_MODE, 1); 744 break; 745 case TRIGGER_DELAY_NEXT_PIXEL: 746 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 747 /* force H count to H_TOTAL and V count to V_TOTAL in 748 * progressive mode and V_TOTAL-1 in interlaced mode 749 */ 750 OTG_FORCE_COUNT_NOW_MODE, 2); 751 break; 752 } 753 } 754 755 void optc1_wait_for_state(struct timing_generator *optc, 756 enum crtc_state state) 757 { 758 struct optc *optc1 = DCN10TG_FROM_TG(optc); 759 760 switch (state) { 761 case CRTC_STATE_VBLANK: 762 REG_WAIT(OTG_STATUS, 763 OTG_V_BLANK, 1, 764 1, 100000); /* 1 vupdate at 10hz */ 765 break; 766 767 case CRTC_STATE_VACTIVE: 768 REG_WAIT(OTG_STATUS, 769 OTG_V_ACTIVE_DISP, 1, 770 1, 100000); /* 1 vupdate at 10hz */ 771 break; 772 773 default: 774 break; 775 } 776 } 777 778 void optc1_set_early_control( 779 struct timing_generator *optc, 780 uint32_t early_cntl) 781 { 782 /* asic design change, do not need this control 783 * empty for share caller logic 784 */ 785 } 786 787 788 void optc1_set_static_screen_control( 789 struct timing_generator *optc, 790 uint32_t event_triggers, 791 uint32_t num_frames) 792 { 793 struct optc *optc1 = DCN10TG_FROM_TG(optc); 794 795 // By register spec, it only takes 8 bit value 796 if (num_frames > 0xFF) 797 num_frames = 0xFF; 798 799 /* Bit 8 is no longer applicable in RV for PSR case, 800 * set bit 8 to 0 if given 801 */ 802 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 803 != 0) 804 event_triggers = event_triggers & 805 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 806 807 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 808 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 809 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 810 } 811 812 void optc1_setup_manual_trigger(struct timing_generator *optc) 813 { 814 struct optc *optc1 = DCN10TG_FROM_TG(optc); 815 816 REG_SET(OTG_GLOBAL_CONTROL2, 0, 817 MANUAL_FLOW_CONTROL_SEL, optc->inst); 818 819 REG_SET_8(OTG_TRIGA_CNTL, 0, 820 OTG_TRIGA_SOURCE_SELECT, 22, 821 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 822 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 823 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 824 OTG_TRIGA_POLARITY_SELECT, 0, 825 OTG_TRIGA_FREQUENCY_SELECT, 0, 826 OTG_TRIGA_DELAY, 0, 827 OTG_TRIGA_CLEAR, 1); 828 } 829 830 void optc1_program_manual_trigger(struct timing_generator *optc) 831 { 832 struct optc *optc1 = DCN10TG_FROM_TG(optc); 833 834 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 835 MANUAL_FLOW_CONTROL, 1); 836 837 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 838 MANUAL_FLOW_CONTROL, 0); 839 } 840 841 842 /** 843 ***************************************************************************** 844 * Function: set_drr 845 * 846 * @brief 847 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 848 * 849 ***************************************************************************** 850 */ 851 void optc1_set_drr( 852 struct timing_generator *optc, 853 const struct drr_params *params) 854 { 855 struct optc *optc1 = DCN10TG_FROM_TG(optc); 856 857 if (params != NULL && 858 params->vertical_total_max > 0 && 859 params->vertical_total_min > 0) { 860 861 if (params->vertical_total_mid != 0) { 862 863 REG_SET(OTG_V_TOTAL_MID, 0, 864 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 865 866 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 867 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 868 OTG_VTOTAL_MID_FRAME_NUM, 869 (uint8_t)params->vertical_total_mid_frame_num); 870 871 } 872 873 REG_SET(OTG_V_TOTAL_MAX, 0, 874 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 875 876 REG_SET(OTG_V_TOTAL_MIN, 0, 877 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 878 879 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 880 OTG_V_TOTAL_MIN_SEL, 1, 881 OTG_V_TOTAL_MAX_SEL, 1, 882 OTG_FORCE_LOCK_ON_EVENT, 0, 883 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 884 OTG_SET_V_TOTAL_MIN_MASK, 0); 885 886 // Setup manual flow control for EOF via TRIG_A 887 optc->funcs->setup_manual_trigger(optc); 888 889 } else { 890 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 891 OTG_SET_V_TOTAL_MIN_MASK, 0, 892 OTG_V_TOTAL_MIN_SEL, 0, 893 OTG_V_TOTAL_MAX_SEL, 0, 894 OTG_FORCE_LOCK_ON_EVENT, 0); 895 896 REG_SET(OTG_V_TOTAL_MIN, 0, 897 OTG_V_TOTAL_MIN, 0); 898 899 REG_SET(OTG_V_TOTAL_MAX, 0, 900 OTG_V_TOTAL_MAX, 0); 901 } 902 } 903 904 static void optc1_set_test_pattern( 905 struct timing_generator *optc, 906 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 907 * because this is not DP-specific (which is probably somewhere in DP 908 * encoder) */ 909 enum controller_dp_test_pattern test_pattern, 910 enum dc_color_depth color_depth) 911 { 912 struct optc *optc1 = DCN10TG_FROM_TG(optc); 913 enum test_pattern_color_format bit_depth; 914 enum test_pattern_dyn_range dyn_range; 915 enum test_pattern_mode mode; 916 uint32_t pattern_mask; 917 uint32_t pattern_data; 918 /* color ramp generator mixes 16-bits color */ 919 uint32_t src_bpc = 16; 920 /* requested bpc */ 921 uint32_t dst_bpc; 922 uint32_t index; 923 /* RGB values of the color bars. 924 * Produce two RGB colors: RGB0 - white (all Fs) 925 * and RGB1 - black (all 0s) 926 * (three RGB components for two colors) 927 */ 928 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 929 0x0000, 0x0000}; 930 /* dest color (converted to the specified color format) */ 931 uint16_t dst_color[6]; 932 uint32_t inc_base; 933 934 /* translate to bit depth */ 935 switch (color_depth) { 936 case COLOR_DEPTH_666: 937 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 938 break; 939 case COLOR_DEPTH_888: 940 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 941 break; 942 case COLOR_DEPTH_101010: 943 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 944 break; 945 case COLOR_DEPTH_121212: 946 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 947 break; 948 default: 949 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 950 break; 951 } 952 953 switch (test_pattern) { 954 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 955 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 956 { 957 dyn_range = (test_pattern == 958 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 959 TEST_PATTERN_DYN_RANGE_CEA : 960 TEST_PATTERN_DYN_RANGE_VESA); 961 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 962 963 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 964 OTG_TEST_PATTERN_VRES, 6, 965 OTG_TEST_PATTERN_HRES, 6); 966 967 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 968 OTG_TEST_PATTERN_EN, 1, 969 OTG_TEST_PATTERN_MODE, mode, 970 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 971 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 972 } 973 break; 974 975 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 976 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 977 { 978 mode = (test_pattern == 979 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 980 TEST_PATTERN_MODE_VERTICALBARS : 981 TEST_PATTERN_MODE_HORIZONTALBARS); 982 983 switch (bit_depth) { 984 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 985 dst_bpc = 6; 986 break; 987 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 988 dst_bpc = 8; 989 break; 990 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 991 dst_bpc = 10; 992 break; 993 default: 994 dst_bpc = 8; 995 break; 996 } 997 998 /* adjust color to the required colorFormat */ 999 for (index = 0; index < 6; index++) { 1000 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1001 * (srcBpc - dstBpc); 1002 */ 1003 dst_color[index] = 1004 src_color[index] >> (src_bpc - dst_bpc); 1005 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1006 * lowest 6 are hardwired to ZERO 1007 * color bits should be left aligned aligned to MSB 1008 * XXXXXXXXXX000000 for 10 bit, 1009 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1010 */ 1011 dst_color[index] <<= (16 - dst_bpc); 1012 } 1013 1014 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1015 1016 /* We have to write the mask before data, similar to pipeline. 1017 * For example, for 8 bpc, if we want RGB0 to be magenta, 1018 * and RGB1 to be cyan, 1019 * we need to make 7 writes: 1020 * MASK DATA 1021 * 000001 00000000 00000000 set mask to R0 1022 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1023 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1024 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1025 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1026 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1027 * 100000 11111111 00000000 B1 255, 0xFF00 1028 * 1029 * we will make a loop of 6 in which we prepare the mask, 1030 * then write, then prepare the color for next write. 1031 * first iteration will write mask only, 1032 * but each next iteration color prepared in 1033 * previous iteration will be written within new mask, 1034 * the last component will written separately, 1035 * mask is not changing between 6th and 7th write 1036 * and color will be prepared by last iteration 1037 */ 1038 1039 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1040 * is B1, G1, R1, B0, G0, R0 1041 */ 1042 pattern_data = 0; 1043 for (index = 0; index < 6; index++) { 1044 /* prepare color mask, first write PATTERN_DATA 1045 * will have all zeros 1046 */ 1047 pattern_mask = (1 << index); 1048 1049 /* write color component */ 1050 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1051 OTG_TEST_PATTERN_MASK, pattern_mask, 1052 OTG_TEST_PATTERN_DATA, pattern_data); 1053 1054 /* prepare next color component, 1055 * will be written in the next iteration 1056 */ 1057 pattern_data = dst_color[index]; 1058 } 1059 /* write last color component, 1060 * it's been already prepared in the loop 1061 */ 1062 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1063 OTG_TEST_PATTERN_MASK, pattern_mask, 1064 OTG_TEST_PATTERN_DATA, pattern_data); 1065 1066 /* enable test pattern */ 1067 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1068 OTG_TEST_PATTERN_EN, 1, 1069 OTG_TEST_PATTERN_MODE, mode, 1070 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1071 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1072 } 1073 break; 1074 1075 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1076 { 1077 mode = (bit_depth == 1078 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1079 TEST_PATTERN_MODE_DUALRAMP_RGB : 1080 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1081 1082 switch (bit_depth) { 1083 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1084 dst_bpc = 6; 1085 break; 1086 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1087 dst_bpc = 8; 1088 break; 1089 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1090 dst_bpc = 10; 1091 break; 1092 default: 1093 dst_bpc = 8; 1094 break; 1095 } 1096 1097 /* increment for the first ramp for one color gradation 1098 * 1 gradation for 6-bit color is 2^10 1099 * gradations in 16-bit color 1100 */ 1101 inc_base = (src_bpc - dst_bpc); 1102 1103 switch (bit_depth) { 1104 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1105 { 1106 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1107 OTG_TEST_PATTERN_INC0, inc_base, 1108 OTG_TEST_PATTERN_INC1, 0, 1109 OTG_TEST_PATTERN_HRES, 6, 1110 OTG_TEST_PATTERN_VRES, 6, 1111 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1112 } 1113 break; 1114 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1115 { 1116 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1117 OTG_TEST_PATTERN_INC0, inc_base, 1118 OTG_TEST_PATTERN_INC1, 0, 1119 OTG_TEST_PATTERN_HRES, 8, 1120 OTG_TEST_PATTERN_VRES, 6, 1121 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1122 } 1123 break; 1124 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1125 { 1126 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1127 OTG_TEST_PATTERN_INC0, inc_base, 1128 OTG_TEST_PATTERN_INC1, inc_base + 2, 1129 OTG_TEST_PATTERN_HRES, 8, 1130 OTG_TEST_PATTERN_VRES, 5, 1131 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1132 } 1133 break; 1134 default: 1135 break; 1136 } 1137 1138 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1139 1140 /* enable test pattern */ 1141 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1142 1143 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1144 OTG_TEST_PATTERN_EN, 1, 1145 OTG_TEST_PATTERN_MODE, mode, 1146 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1147 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1148 } 1149 break; 1150 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1151 { 1152 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1153 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1154 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1155 } 1156 break; 1157 default: 1158 break; 1159 1160 } 1161 } 1162 1163 void optc1_get_crtc_scanoutpos( 1164 struct timing_generator *optc, 1165 uint32_t *v_blank_start, 1166 uint32_t *v_blank_end, 1167 uint32_t *h_position, 1168 uint32_t *v_position) 1169 { 1170 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1171 struct crtc_position position; 1172 1173 REG_GET_2(OTG_V_BLANK_START_END, 1174 OTG_V_BLANK_START, v_blank_start, 1175 OTG_V_BLANK_END, v_blank_end); 1176 1177 optc1_get_position(optc, &position); 1178 1179 *h_position = position.horizontal_count; 1180 *v_position = position.vertical_count; 1181 } 1182 1183 static void optc1_enable_stereo(struct timing_generator *optc, 1184 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1185 { 1186 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1187 1188 if (flags) { 1189 uint32_t stereo_en; 1190 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1191 1192 if (flags->PROGRAM_STEREO) 1193 REG_UPDATE_3(OTG_STEREO_CONTROL, 1194 OTG_STEREO_EN, stereo_en, 1195 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1196 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1197 1198 if (flags->PROGRAM_POLARITY) 1199 REG_UPDATE(OTG_STEREO_CONTROL, 1200 OTG_STEREO_EYE_FLAG_POLARITY, 1201 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1202 1203 if (flags->DISABLE_STEREO_DP_SYNC) 1204 REG_UPDATE(OTG_STEREO_CONTROL, 1205 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1206 1207 if (flags->PROGRAM_STEREO) 1208 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1209 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1210 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1211 1212 } 1213 } 1214 1215 void optc1_program_stereo(struct timing_generator *optc, 1216 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1217 { 1218 if (flags->PROGRAM_STEREO) 1219 optc1_enable_stereo(optc, timing, flags); 1220 else 1221 optc1_disable_stereo(optc); 1222 } 1223 1224 1225 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1226 { 1227 bool ret = false; 1228 uint32_t left_eye = 0; 1229 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1230 1231 REG_GET(OTG_STEREO_STATUS, 1232 OTG_STEREO_CURRENT_EYE, &left_eye); 1233 if (left_eye == 1) 1234 ret = true; 1235 else 1236 ret = false; 1237 1238 return ret; 1239 } 1240 1241 bool optc1_get_hw_timing(struct timing_generator *tg, 1242 struct dc_crtc_timing *hw_crtc_timing) 1243 { 1244 struct dcn_otg_state s = {0}; 1245 1246 if (tg == NULL || hw_crtc_timing == NULL) 1247 return false; 1248 1249 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1250 1251 hw_crtc_timing->h_total = s.h_total + 1; 1252 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1253 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1254 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1255 1256 hw_crtc_timing->v_total = s.v_total + 1; 1257 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1258 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1259 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1260 1261 return true; 1262 } 1263 1264 1265 void optc1_read_otg_state(struct optc *optc1, 1266 struct dcn_otg_state *s) 1267 { 1268 REG_GET(OTG_CONTROL, 1269 OTG_MASTER_EN, &s->otg_enabled); 1270 1271 REG_GET_2(OTG_V_BLANK_START_END, 1272 OTG_V_BLANK_START, &s->v_blank_start, 1273 OTG_V_BLANK_END, &s->v_blank_end); 1274 1275 REG_GET(OTG_V_SYNC_A_CNTL, 1276 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1277 1278 REG_GET(OTG_V_TOTAL, 1279 OTG_V_TOTAL, &s->v_total); 1280 1281 REG_GET(OTG_V_TOTAL_MAX, 1282 OTG_V_TOTAL_MAX, &s->v_total_max); 1283 1284 REG_GET(OTG_V_TOTAL_MIN, 1285 OTG_V_TOTAL_MIN, &s->v_total_min); 1286 1287 REG_GET(OTG_V_TOTAL_CONTROL, 1288 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1289 1290 REG_GET(OTG_V_TOTAL_CONTROL, 1291 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1292 1293 REG_GET_2(OTG_V_SYNC_A, 1294 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1295 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1296 1297 REG_GET_2(OTG_H_BLANK_START_END, 1298 OTG_H_BLANK_START, &s->h_blank_start, 1299 OTG_H_BLANK_END, &s->h_blank_end); 1300 1301 REG_GET_2(OTG_H_SYNC_A, 1302 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1303 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1304 1305 REG_GET(OTG_H_SYNC_A_CNTL, 1306 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1307 1308 REG_GET(OTG_H_TOTAL, 1309 OTG_H_TOTAL, &s->h_total); 1310 1311 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1312 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1313 } 1314 1315 bool optc1_get_otg_active_size(struct timing_generator *optc, 1316 uint32_t *otg_active_width, 1317 uint32_t *otg_active_height) 1318 { 1319 uint32_t otg_enabled; 1320 uint32_t v_blank_start; 1321 uint32_t v_blank_end; 1322 uint32_t h_blank_start; 1323 uint32_t h_blank_end; 1324 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1325 1326 1327 REG_GET(OTG_CONTROL, 1328 OTG_MASTER_EN, &otg_enabled); 1329 1330 if (otg_enabled == 0) 1331 return false; 1332 1333 REG_GET_2(OTG_V_BLANK_START_END, 1334 OTG_V_BLANK_START, &v_blank_start, 1335 OTG_V_BLANK_END, &v_blank_end); 1336 1337 REG_GET_2(OTG_H_BLANK_START_END, 1338 OTG_H_BLANK_START, &h_blank_start, 1339 OTG_H_BLANK_END, &h_blank_end); 1340 1341 *otg_active_width = v_blank_start - v_blank_end; 1342 *otg_active_height = h_blank_start - h_blank_end; 1343 return true; 1344 } 1345 1346 void optc1_clear_optc_underflow(struct timing_generator *optc) 1347 { 1348 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1349 1350 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1351 } 1352 1353 void optc1_tg_init(struct timing_generator *optc) 1354 { 1355 optc1_set_blank_data_double_buffer(optc, true); 1356 optc1_clear_optc_underflow(optc); 1357 } 1358 1359 bool optc1_is_tg_enabled(struct timing_generator *optc) 1360 { 1361 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1362 uint32_t otg_enabled = 0; 1363 1364 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1365 1366 return (otg_enabled != 0); 1367 1368 } 1369 1370 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1371 { 1372 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1373 uint32_t underflow_occurred = 0; 1374 1375 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1376 OPTC_UNDERFLOW_OCCURRED_STATUS, 1377 &underflow_occurred); 1378 1379 return (underflow_occurred == 1); 1380 } 1381 1382 bool optc1_configure_crc(struct timing_generator *optc, 1383 const struct crc_params *params) 1384 { 1385 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1386 1387 /* Cannot configure crc on a CRTC that is disabled */ 1388 if (!optc1_is_tg_enabled(optc)) 1389 return false; 1390 1391 REG_WRITE(OTG_CRC_CNTL, 0); 1392 1393 if (!params->enable) 1394 return true; 1395 1396 /* Program frame boundaries */ 1397 /* Window A x axis start and end. */ 1398 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1399 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1400 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1401 1402 /* Window A y axis start and end. */ 1403 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1404 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1405 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1406 1407 /* Window B x axis start and end. */ 1408 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1409 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1410 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1411 1412 /* Window B y axis start and end. */ 1413 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1414 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1415 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1416 1417 /* Set crc mode and selection, and enable. Only using CRC0*/ 1418 REG_UPDATE_3(OTG_CRC_CNTL, 1419 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1420 OTG_CRC0_SELECT, params->selection, 1421 OTG_CRC_EN, 1); 1422 1423 return true; 1424 } 1425 1426 bool optc1_get_crc(struct timing_generator *optc, 1427 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1428 { 1429 uint32_t field = 0; 1430 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1431 1432 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1433 1434 /* Early return if CRC is not enabled for this CRTC */ 1435 if (!field) 1436 return false; 1437 1438 REG_GET_2(OTG_CRC0_DATA_RG, 1439 CRC0_R_CR, r_cr, 1440 CRC0_G_Y, g_y); 1441 1442 REG_GET(OTG_CRC0_DATA_B, 1443 CRC0_B_CB, b_cb); 1444 1445 return true; 1446 } 1447 1448 static const struct timing_generator_funcs dcn10_tg_funcs = { 1449 .validate_timing = optc1_validate_timing, 1450 .program_timing = optc1_program_timing, 1451 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1452 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1453 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1454 .program_global_sync = optc1_program_global_sync, 1455 .enable_crtc = optc1_enable_crtc, 1456 .disable_crtc = optc1_disable_crtc, 1457 /* used by enable_timing_synchronization. Not need for FPGA */ 1458 .is_counter_moving = optc1_is_counter_moving, 1459 .get_position = optc1_get_position, 1460 .get_frame_count = optc1_get_vblank_counter, 1461 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1462 .get_otg_active_size = optc1_get_otg_active_size, 1463 .set_early_control = optc1_set_early_control, 1464 /* used by enable_timing_synchronization. Not need for FPGA */ 1465 .wait_for_state = optc1_wait_for_state, 1466 .set_blank = optc1_set_blank, 1467 .is_blanked = optc1_is_blanked, 1468 .set_blank_color = optc1_program_blank_color, 1469 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1470 .enable_reset_trigger = optc1_enable_reset_trigger, 1471 .enable_crtc_reset = optc1_enable_crtc_reset, 1472 .disable_reset_trigger = optc1_disable_reset_trigger, 1473 .lock = optc1_lock, 1474 .unlock = optc1_unlock, 1475 .enable_optc_clock = optc1_enable_optc_clock, 1476 .set_drr = optc1_set_drr, 1477 .set_static_screen_control = optc1_set_static_screen_control, 1478 .set_test_pattern = optc1_set_test_pattern, 1479 .program_stereo = optc1_program_stereo, 1480 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1481 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1482 .tg_init = optc1_tg_init, 1483 .is_tg_enabled = optc1_is_tg_enabled, 1484 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1485 .clear_optc_underflow = optc1_clear_optc_underflow, 1486 .get_crc = optc1_get_crc, 1487 .configure_crc = optc1_configure_crc, 1488 .set_vtg_params = optc1_set_vtg_params, 1489 .program_manual_trigger = optc1_program_manual_trigger, 1490 .setup_manual_trigger = optc1_setup_manual_trigger, 1491 .get_hw_timing = optc1_get_hw_timing, 1492 }; 1493 1494 void dcn10_timing_generator_init(struct optc *optc1) 1495 { 1496 optc1->base.funcs = &dcn10_tg_funcs; 1497 1498 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1499 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1500 1501 optc1->min_h_blank = 32; 1502 optc1->min_v_blank = 3; 1503 optc1->min_v_blank_interlace = 5; 1504 optc1->min_h_sync_width = 8; 1505 optc1->min_v_sync_width = 1; 1506 } 1507 1508 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1509 * 1510 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1511 * containter rate. 1512 * 1513 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1514 * halved to maintain the correct pixel rate. 1515 * 1516 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1517 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1518 * 1519 */ 1520 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1521 { 1522 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1523 1524 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1525 && !timing->dsc_cfg.ycbcr422_simple); 1526 return two_pix; 1527 } 1528 1529