1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_OPP_DCN10_H__ 26 #define __DC_OPP_DCN10_H__ 27 28 #include "opp.h" 29 30 #define TO_DCN10_OPP(opp)\ 31 container_of(opp, struct dcn10_opp, base) 32 33 #define OPP_SF(reg_name, field_name, post_fix)\ 34 .field_name = reg_name ## __ ## field_name ## post_fix 35 36 #define OPP_REG_LIST_DCN(id) \ 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 38 SRI(FMT_CONTROL, FMT, id), \ 39 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 40 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 41 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 42 SRI(FMT_CLAMP_CNTL, FMT, id), \ 43 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 44 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id) 45 46 #define OPP_REG_LIST_DCN10(id) \ 47 OPP_REG_LIST_DCN(id) 48 49 #define OPP_COMMON_REG_VARIABLE_LIST \ 50 uint32_t FMT_BIT_DEPTH_CONTROL; \ 51 uint32_t FMT_CONTROL; \ 52 uint32_t FMT_DITHER_RAND_R_SEED; \ 53 uint32_t FMT_DITHER_RAND_G_SEED; \ 54 uint32_t FMT_DITHER_RAND_B_SEED; \ 55 uint32_t FMT_CLAMP_CNTL; \ 56 uint32_t FMT_DYNAMIC_EXP_CNTL; \ 57 uint32_t FMT_MAP420_MEMORY_CONTROL; 58 59 #define OPP_MASK_SH_LIST_DCN(mask_sh) \ 60 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ 61 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ 62 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ 63 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ 64 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ 65 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ 66 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ 67 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 68 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ 69 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ 70 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ 71 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ 72 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ 73 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ 74 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ 75 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ 76 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ 77 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ 78 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ 79 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ 80 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ 81 OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh) 82 83 #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ 84 OPP_MASK_SH_LIST_DCN(mask_sh) 85 86 #define OPP_DCN10_REG_FIELD_LIST(type) \ 87 type FMT_TRUNCATE_EN; \ 88 type FMT_TRUNCATE_DEPTH; \ 89 type FMT_TRUNCATE_MODE; \ 90 type FMT_SPATIAL_DITHER_EN; \ 91 type FMT_SPATIAL_DITHER_MODE; \ 92 type FMT_SPATIAL_DITHER_DEPTH; \ 93 type FMT_TEMPORAL_DITHER_EN; \ 94 type FMT_HIGHPASS_RANDOM_ENABLE; \ 95 type FMT_FRAME_RANDOM_ENABLE; \ 96 type FMT_RGB_RANDOM_ENABLE; \ 97 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 98 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 99 type FMT_RAND_R_SEED; \ 100 type FMT_RAND_G_SEED; \ 101 type FMT_RAND_B_SEED; \ 102 type FMT_PIXEL_ENCODING; \ 103 type FMT_CLAMP_DATA_EN; \ 104 type FMT_CLAMP_COLOR_FORMAT; \ 105 type FMT_DYNAMIC_EXP_EN; \ 106 type FMT_DYNAMIC_EXP_MODE; \ 107 type FMT_MAP420MEM_PWR_FORCE; \ 108 type FMT_STEREOSYNC_OVERRIDE; 109 110 struct dcn10_opp_registers { 111 OPP_COMMON_REG_VARIABLE_LIST 112 }; 113 114 struct dcn10_opp_shift { 115 OPP_DCN10_REG_FIELD_LIST(uint8_t) 116 }; 117 118 struct dcn10_opp_mask { 119 OPP_DCN10_REG_FIELD_LIST(uint32_t) 120 }; 121 122 struct dcn10_opp { 123 struct output_pixel_processor base; 124 125 const struct dcn10_opp_registers *regs; 126 const struct dcn10_opp_shift *opp_shift; 127 const struct dcn10_opp_mask *opp_mask; 128 129 bool is_write_to_ram_a_safe; 130 }; 131 132 void dcn10_opp_construct(struct dcn10_opp *oppn10, 133 struct dc_context *ctx, 134 uint32_t inst, 135 const struct dcn10_opp_registers *regs, 136 const struct dcn10_opp_shift *opp_shift, 137 const struct dcn10_opp_mask *opp_mask); 138 139 void opp1_set_dyn_expansion( 140 struct output_pixel_processor *opp, 141 enum dc_color_space color_sp, 142 enum dc_color_depth color_dpth, 143 enum signal_type signal); 144 145 void opp1_program_fmt( 146 struct output_pixel_processor *opp, 147 struct bit_depth_reduction_params *fmt_bit_depth, 148 struct clamping_and_pixel_encoding_params *clamping); 149 150 void opp1_program_bit_depth_reduction( 151 struct output_pixel_processor *opp, 152 const struct bit_depth_reduction_params *params); 153 154 void opp1_set_stereo_polarity( 155 struct output_pixel_processor *opp, 156 bool enable, bool rightEyePolarity); 157 158 void opp1_destroy(struct output_pixel_processor **opp); 159 160 #endif 161