1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_OPP_DCN10_H__ 26 #define __DC_OPP_DCN10_H__ 27 28 #include "opp.h" 29 30 #define TO_DCN10_OPP(opp)\ 31 container_of(opp, struct dcn10_opp, base) 32 33 #define OPP_SF(reg_name, field_name, post_fix)\ 34 .field_name = reg_name ## __ ## field_name ## post_fix 35 36 #define OPP_REG_LIST_DCN(id) \ 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 38 SRI(FMT_CONTROL, FMT, id), \ 39 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 40 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 41 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 42 SRI(FMT_CLAMP_CNTL, FMT, id), \ 43 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 44 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id) 45 46 #define OPP_REG_LIST_DCN10(id) \ 47 OPP_REG_LIST_DCN(id) 48 49 #define OPP_MASK_SH_LIST_DCN(mask_sh) \ 50 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ 51 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ 52 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ 53 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ 54 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ 55 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ 56 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ 57 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 58 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ 59 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ 60 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ 61 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ 62 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ 63 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ 64 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ 65 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ 66 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ 67 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ 68 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ 69 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ 70 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ 71 OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh) 72 73 #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ 74 OPP_MASK_SH_LIST_DCN(mask_sh) 75 76 #define OPP_DCN10_REG_FIELD_LIST(type) \ 77 type DPG_EN; \ 78 type DPG_MODE; \ 79 type DPG_VRES; \ 80 type DPG_HRES; \ 81 type DPG_COLOUR0_R_CR; \ 82 type DPG_COLOUR1_R_CR; \ 83 type DPG_COLOUR0_B_CB; \ 84 type DPG_COLOUR1_B_CB; \ 85 type DPG_COLOUR0_G_Y; \ 86 type DPG_COLOUR1_G_Y; \ 87 type CM_OCSC_C11; \ 88 type CM_OCSC_C12; \ 89 type CM_OCSC_C13; \ 90 type CM_OCSC_C14; \ 91 type CM_OCSC_C21; \ 92 type CM_OCSC_C22; \ 93 type CM_OCSC_C23; \ 94 type CM_OCSC_C24; \ 95 type CM_OCSC_C31; \ 96 type CM_OCSC_C32; \ 97 type CM_OCSC_C33; \ 98 type CM_OCSC_C34; \ 99 type CM_COMB_C11; \ 100 type CM_COMB_C12; \ 101 type CM_COMB_C13; \ 102 type CM_COMB_C14; \ 103 type CM_COMB_C21; \ 104 type CM_COMB_C22; \ 105 type CM_COMB_C23; \ 106 type CM_COMB_C24; \ 107 type CM_COMB_C31; \ 108 type CM_COMB_C32; \ 109 type CM_COMB_C33; \ 110 type CM_COMB_C34; \ 111 type FMT_TRUNCATE_EN; \ 112 type FMT_TRUNCATE_DEPTH; \ 113 type FMT_TRUNCATE_MODE; \ 114 type FMT_SPATIAL_DITHER_EN; \ 115 type FMT_SPATIAL_DITHER_MODE; \ 116 type FMT_SPATIAL_DITHER_DEPTH; \ 117 type FMT_TEMPORAL_DITHER_EN; \ 118 type FMT_HIGHPASS_RANDOM_ENABLE; \ 119 type FMT_FRAME_RANDOM_ENABLE; \ 120 type FMT_RGB_RANDOM_ENABLE; \ 121 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 122 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 123 type FMT_RAND_R_SEED; \ 124 type FMT_RAND_G_SEED; \ 125 type FMT_RAND_B_SEED; \ 126 type FMT_PIXEL_ENCODING; \ 127 type FMT_CLAMP_DATA_EN; \ 128 type FMT_CLAMP_COLOR_FORMAT; \ 129 type FMT_DYNAMIC_EXP_EN; \ 130 type FMT_DYNAMIC_EXP_MODE; \ 131 type FMT_MAP420MEM_PWR_FORCE; \ 132 type FMT_STEREOSYNC_OVERRIDE 133 134 struct dcn10_opp_shift { 135 OPP_DCN10_REG_FIELD_LIST(uint8_t); 136 }; 137 138 struct dcn10_opp_mask { 139 OPP_DCN10_REG_FIELD_LIST(uint32_t); 140 }; 141 142 struct dcn10_opp_registers { 143 uint32_t DPG_CONTROL; 144 uint32_t DPG_COLOUR_B_CB; 145 uint32_t DPG_COLOUR_G_Y; 146 uint32_t DPG_COLOUR_R_CR; 147 uint32_t CM_OCSC_C11_C12; 148 uint32_t CM_OCSC_C13_C14; 149 uint32_t CM_OCSC_C21_C22; 150 uint32_t CM_OCSC_C23_C24; 151 uint32_t CM_OCSC_C31_C32; 152 uint32_t CM_OCSC_C33_C34; 153 uint32_t CM_COMB_C11_C12; 154 uint32_t CM_COMB_C13_C14; 155 uint32_t CM_COMB_C21_C22; 156 uint32_t CM_COMB_C23_C24; 157 uint32_t CM_COMB_C31_C32; 158 uint32_t CM_COMB_C33_C34; 159 uint32_t FMT_BIT_DEPTH_CONTROL; 160 uint32_t FMT_CONTROL; 161 uint32_t FMT_DITHER_RAND_R_SEED; 162 uint32_t FMT_DITHER_RAND_G_SEED; 163 uint32_t FMT_DITHER_RAND_B_SEED; 164 uint32_t FMT_CLAMP_CNTL; 165 uint32_t FMT_DYNAMIC_EXP_CNTL; 166 uint32_t FMT_MAP420_MEMORY_CONTROL; 167 }; 168 169 struct dcn10_opp { 170 struct output_pixel_processor base; 171 172 const struct dcn10_opp_registers *regs; 173 const struct dcn10_opp_shift *opp_shift; 174 const struct dcn10_opp_mask *opp_mask; 175 176 bool is_write_to_ram_a_safe; 177 }; 178 179 void dcn10_opp_construct(struct dcn10_opp *oppn10, 180 struct dc_context *ctx, 181 uint32_t inst, 182 const struct dcn10_opp_registers *regs, 183 const struct dcn10_opp_shift *opp_shift, 184 const struct dcn10_opp_mask *opp_mask); 185 186 #endif 187