1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dcn10_opp.h" 28 #include "reg_helper.h" 29 30 #define REG(reg) \ 31 (oppn10->regs->reg) 32 33 #undef FN 34 #define FN(reg_name, field_name) \ 35 oppn10->opp_shift->field_name, oppn10->opp_mask->field_name 36 37 #define CTX \ 38 oppn10->base.ctx 39 40 static void opp_set_regamma_mode( 41 struct output_pixel_processor *opp, 42 enum opp_regamma mode) 43 { 44 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 45 uint32_t re_mode = 0; 46 uint32_t obuf_bypass = 0; /* need for pipe split */ 47 uint32_t obuf_hupscale = 0; 48 49 switch (mode) { 50 case OPP_REGAMMA_BYPASS: 51 re_mode = 0; 52 break; 53 case OPP_REGAMMA_SRGB: 54 re_mode = 1; 55 break; 56 case OPP_REGAMMA_3_6: 57 re_mode = 2; 58 break; 59 case OPP_REGAMMA_USER: 60 re_mode = oppn10->is_write_to_ram_a_safe ? 3 : 4; 61 oppn10->is_write_to_ram_a_safe = !oppn10->is_write_to_ram_a_safe; 62 break; 63 default: 64 break; 65 } 66 67 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); 68 REG_UPDATE_2(OBUF_CONTROL, 69 OBUF_BYPASS, obuf_bypass, 70 OBUF_H_2X_UPSCALE_EN, obuf_hupscale); 71 } 72 73 /************* FORMATTER ************/ 74 75 /** 76 * set_truncation 77 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp 78 * 2) enable truncation 79 * 3) HW remove 12bit FMT support for DCE11 power saving reason. 80 */ 81 static void set_truncation( 82 struct dcn10_opp *oppn10, 83 const struct bit_depth_reduction_params *params) 84 { 85 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, 86 FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED, 87 FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, 88 FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); 89 } 90 91 static void set_spatial_dither( 92 struct dcn10_opp *oppn10, 93 const struct bit_depth_reduction_params *params) 94 { 95 /*Disable spatial (random) dithering*/ 96 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, 97 FMT_SPATIAL_DITHER_EN, 0, 98 FMT_SPATIAL_DITHER_MODE, 0, 99 FMT_SPATIAL_DITHER_DEPTH, 0, 100 FMT_TEMPORAL_DITHER_EN, 0, 101 FMT_HIGHPASS_RANDOM_ENABLE, 0, 102 FMT_FRAME_RANDOM_ENABLE, 0, 103 FMT_RGB_RANDOM_ENABLE, 0); 104 105 106 /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ 107 if (params->flags.FRAME_RANDOM == 1) { 108 if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { 109 REG_UPDATE_2(FMT_CONTROL, 110 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, 111 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); 112 } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { 113 REG_UPDATE_2(FMT_CONTROL, 114 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, 115 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); 116 } else { 117 return; 118 } 119 } else { 120 REG_UPDATE_2(FMT_CONTROL, 121 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, 122 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); 123 } 124 125 /*Set seed for random values for 126 * spatial dithering for R,G,B channels*/ 127 128 REG_SET(FMT_DITHER_RAND_R_SEED, 0, 129 FMT_RAND_R_SEED, params->r_seed_value); 130 131 REG_SET(FMT_DITHER_RAND_G_SEED, 0, 132 FMT_RAND_G_SEED, params->g_seed_value); 133 134 REG_SET(FMT_DITHER_RAND_B_SEED, 0, 135 FMT_RAND_B_SEED, params->b_seed_value); 136 137 /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero 138 * offset for the R/Cr channel, lower 4LSB 139 * is forced to zeros. Typically set to 0 140 * RGB and 0x80000 YCbCr. 141 */ 142 /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero 143 * offset for the G/Y channel, lower 4LSB is 144 * forced to zeros. Typically set to 0 RGB 145 * and 0x80000 YCbCr. 146 */ 147 /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero 148 * offset for the B/Cb channel, lower 4LSB is 149 * forced to zeros. Typically set to 0 RGB and 150 * 0x80000 YCbCr. 151 */ 152 153 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, 154 /*Enable spatial dithering*/ 155 FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, 156 /* Set spatial dithering mode 157 * (default is Seed patterrn AAAA...) 158 */ 159 FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, 160 /*Set spatial dithering bit depth*/ 161 FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, 162 /*Disable High pass filter*/ 163 FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, 164 /*Reset only at startup*/ 165 FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, 166 /*Set RGB data dithered with x^28+x^3+1*/ 167 FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); 168 } 169 170 static void opp_program_bit_depth_reduction( 171 struct output_pixel_processor *opp, 172 const struct bit_depth_reduction_params *params) 173 { 174 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 175 176 set_truncation(oppn10, params); 177 set_spatial_dither(oppn10, params); 178 /* TODO 179 * set_temporal_dither(oppn10, params); 180 */ 181 } 182 183 /** 184 * set_pixel_encoding 185 * 186 * Set Pixel Encoding 187 * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly 188 * 1: YCbCr 4:2:2 189 */ 190 static void set_pixel_encoding( 191 struct dcn10_opp *oppn10, 192 const struct clamping_and_pixel_encoding_params *params) 193 { 194 switch (params->pixel_encoding) { 195 196 case PIXEL_ENCODING_RGB: 197 case PIXEL_ENCODING_YCBCR444: 198 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); 199 break; 200 case PIXEL_ENCODING_YCBCR422: 201 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1); 202 break; 203 case PIXEL_ENCODING_YCBCR420: 204 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); 205 break; 206 default: 207 break; 208 } 209 } 210 211 /** 212 * Set Clamping 213 * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) 214 * 1 for 8 bpc 215 * 2 for 10 bpc 216 * 3 for 12 bpc 217 * 7 for programable 218 * 2) Enable clamp if Limited range requested 219 */ 220 static void opp_set_clamping( 221 struct dcn10_opp *oppn10, 222 const struct clamping_and_pixel_encoding_params *params) 223 { 224 REG_UPDATE_2(FMT_CLAMP_CNTL, 225 FMT_CLAMP_DATA_EN, 0, 226 FMT_CLAMP_COLOR_FORMAT, 0); 227 228 switch (params->clamping_level) { 229 case CLAMPING_FULL_RANGE: 230 REG_UPDATE_2(FMT_CLAMP_CNTL, 231 FMT_CLAMP_DATA_EN, 1, 232 FMT_CLAMP_COLOR_FORMAT, 0); 233 break; 234 case CLAMPING_LIMITED_RANGE_8BPC: 235 REG_UPDATE_2(FMT_CLAMP_CNTL, 236 FMT_CLAMP_DATA_EN, 1, 237 FMT_CLAMP_COLOR_FORMAT, 1); 238 break; 239 case CLAMPING_LIMITED_RANGE_10BPC: 240 REG_UPDATE_2(FMT_CLAMP_CNTL, 241 FMT_CLAMP_DATA_EN, 1, 242 FMT_CLAMP_COLOR_FORMAT, 2); 243 244 break; 245 case CLAMPING_LIMITED_RANGE_12BPC: 246 REG_UPDATE_2(FMT_CLAMP_CNTL, 247 FMT_CLAMP_DATA_EN, 1, 248 FMT_CLAMP_COLOR_FORMAT, 3); 249 break; 250 case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: 251 /* TODO */ 252 default: 253 break; 254 } 255 256 } 257 258 static void opp_set_dyn_expansion( 259 struct output_pixel_processor *opp, 260 enum dc_color_space color_sp, 261 enum dc_color_depth color_dpth, 262 enum signal_type signal) 263 { 264 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 265 266 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 267 FMT_DYNAMIC_EXP_EN, 0, 268 FMT_DYNAMIC_EXP_MODE, 0); 269 270 /*00 - 10-bit -> 12-bit dynamic expansion*/ 271 /*01 - 8-bit -> 12-bit dynamic expansion*/ 272 if (signal == SIGNAL_TYPE_HDMI_TYPE_A || 273 signal == SIGNAL_TYPE_DISPLAY_PORT || 274 signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 275 switch (color_dpth) { 276 case COLOR_DEPTH_888: 277 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 278 FMT_DYNAMIC_EXP_EN, 1, 279 FMT_DYNAMIC_EXP_MODE, 1); 280 break; 281 case COLOR_DEPTH_101010: 282 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 283 FMT_DYNAMIC_EXP_EN, 1, 284 FMT_DYNAMIC_EXP_MODE, 0); 285 break; 286 case COLOR_DEPTH_121212: 287 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 288 FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/ 289 FMT_DYNAMIC_EXP_MODE, 0); 290 break; 291 default: 292 break; 293 } 294 } 295 } 296 297 static void opp_program_clamping_and_pixel_encoding( 298 struct output_pixel_processor *opp, 299 const struct clamping_and_pixel_encoding_params *params) 300 { 301 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 302 303 opp_set_clamping(oppn10, params); 304 set_pixel_encoding(oppn10, params); 305 } 306 307 static void opp_program_fmt( 308 struct output_pixel_processor *opp, 309 struct bit_depth_reduction_params *fmt_bit_depth, 310 struct clamping_and_pixel_encoding_params *clamping) 311 { 312 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 313 314 if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) 315 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); 316 317 /* dithering is affected by <CrtcSourceSelect>, hence should be 318 * programmed afterwards */ 319 opp_program_bit_depth_reduction( 320 opp, 321 fmt_bit_depth); 322 323 opp_program_clamping_and_pixel_encoding( 324 opp, 325 clamping); 326 327 return; 328 } 329 330 static void opp_set_output_csc_default( 331 struct output_pixel_processor *opp, 332 const struct default_adjustment *default_adjust) 333 { 334 335 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 336 uint32_t ocsc_mode = 0; 337 338 if (default_adjust != NULL) { 339 switch (default_adjust->out_color_space) { 340 case COLOR_SPACE_SRGB: 341 ocsc_mode = 0; 342 break; 343 case COLOR_SPACE_SRGB_LIMITED: 344 ocsc_mode = 1; 345 break; 346 case COLOR_SPACE_YCBCR601: 347 case COLOR_SPACE_YCBCR601_LIMITED: 348 ocsc_mode = 2; 349 break; 350 case COLOR_SPACE_YCBCR709: 351 case COLOR_SPACE_YCBCR709_LIMITED: 352 ocsc_mode = 3; 353 break; 354 case COLOR_SPACE_UNKNOWN: 355 default: 356 break; 357 } 358 } 359 360 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); 361 362 } 363 /*program re gamma RAM B*/ 364 static void opp_program_regamma_lutb_settings( 365 struct output_pixel_processor *opp, 366 const struct pwl_params *params) 367 { 368 const struct gamma_curve *curve; 369 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 370 371 REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0, 372 CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x, 373 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0); 374 REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0, 375 CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x, 376 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0); 377 REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0, 378 CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x, 379 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0); 380 381 REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0, 382 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); 383 REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0, 384 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); 385 REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0, 386 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); 387 388 REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0, 389 CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x); 390 REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0, 391 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, 392 CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); 393 394 REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0, 395 CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x); 396 REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0, 397 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, 398 CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); 399 400 REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0, 401 CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x); 402 REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0, 403 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, 404 CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); 405 406 curve = params->arr_curve_points; 407 REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0, 408 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 409 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 410 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 411 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 412 413 curve += 2; 414 REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0, 415 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, 416 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 417 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, 418 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 419 420 curve += 2; 421 REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0, 422 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, 423 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 424 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, 425 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 426 427 curve += 2; 428 REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0, 429 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, 430 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 431 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, 432 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 433 434 curve += 2; 435 REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0, 436 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, 437 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 438 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, 439 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 440 441 curve += 2; 442 REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0, 443 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, 444 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 445 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, 446 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 447 448 curve += 2; 449 REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0, 450 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, 451 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 452 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, 453 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 454 455 curve += 2; 456 REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0, 457 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, 458 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 459 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, 460 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 461 462 curve += 2; 463 REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0, 464 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, 465 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 466 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, 467 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 468 469 curve += 2; 470 REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0, 471 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, 472 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 473 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, 474 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 475 476 curve += 2; 477 REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0, 478 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, 479 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 480 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, 481 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 482 483 curve += 2; 484 REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0, 485 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, 486 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 487 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, 488 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 489 490 curve += 2; 491 REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0, 492 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, 493 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 494 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, 495 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 496 497 curve += 2; 498 REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0, 499 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, 500 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 501 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, 502 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 503 504 curve += 2; 505 REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0, 506 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, 507 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 508 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, 509 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 510 511 curve += 2; 512 REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0, 513 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, 514 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 515 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, 516 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 517 518 curve += 2; 519 REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0, 520 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, 521 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 522 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, 523 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 524 525 } 526 527 /*program re gamma RAM A*/ 528 static void opp_program_regamma_luta_settings( 529 struct output_pixel_processor *opp, 530 const struct pwl_params *params) 531 { 532 const struct gamma_curve *curve; 533 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 534 535 REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0, 536 CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x, 537 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0); 538 REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0, 539 CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x, 540 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0); 541 REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0, 542 CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x, 543 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0); 544 545 REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0, 546 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope); 547 REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0, 548 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope); 549 REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0, 550 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope); 551 552 REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0, 553 CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x); 554 REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0, 555 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope, 556 CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y); 557 558 REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0, 559 CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x); 560 REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0, 561 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope, 562 CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y); 563 564 REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0, 565 CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x); 566 REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0, 567 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope, 568 CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y); 569 570 curve = params->arr_curve_points; 571 REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0, 572 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 573 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 574 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 575 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 576 577 curve += 2; 578 REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0, 579 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, 580 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, 581 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, 582 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); 583 584 curve += 2; 585 REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0, 586 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, 587 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, 588 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, 589 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); 590 591 curve += 2; 592 REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0, 593 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, 594 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, 595 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, 596 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); 597 598 curve += 2; 599 REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0, 600 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, 601 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, 602 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, 603 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); 604 605 curve += 2; 606 REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0, 607 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, 608 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, 609 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, 610 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); 611 612 curve += 2; 613 REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0, 614 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, 615 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, 616 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, 617 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); 618 619 curve += 2; 620 REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0, 621 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, 622 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, 623 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, 624 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); 625 626 curve += 2; 627 REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0, 628 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, 629 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, 630 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, 631 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); 632 633 curve += 2; 634 REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0, 635 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, 636 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, 637 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, 638 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); 639 640 curve += 2; 641 REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0, 642 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, 643 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, 644 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, 645 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); 646 647 curve += 2; 648 REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0, 649 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, 650 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, 651 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, 652 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); 653 654 curve += 2; 655 REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0, 656 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, 657 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, 658 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, 659 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); 660 661 curve += 2; 662 REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0, 663 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, 664 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, 665 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, 666 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); 667 668 curve += 2; 669 REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0, 670 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, 671 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, 672 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, 673 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); 674 675 curve += 2; 676 REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0, 677 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, 678 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, 679 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, 680 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); 681 682 curve += 2; 683 REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0, 684 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, 685 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, 686 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, 687 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); 688 } 689 690 static void opp_configure_regamma_lut( 691 struct output_pixel_processor *opp, 692 bool is_ram_a) 693 { 694 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 695 696 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, 697 CM_RGAM_LUT_WRITE_EN_MASK, 7); 698 REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK, 699 CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 700 REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0); 701 } 702 703 static void opp_power_on_regamma_lut( 704 struct output_pixel_processor *opp, 705 bool power_on) 706 { 707 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 708 REG_SET(CM_MEM_PWR_CTRL, 0, 709 RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); 710 711 } 712 713 static void opp_program_regamma_lut( 714 struct output_pixel_processor *opp, 715 const struct pwl_result_data *rgb, 716 uint32_t num) 717 { 718 uint32_t i; 719 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 720 for (i = 0 ; i < num; i++) { 721 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); 722 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); 723 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); 724 725 REG_SET(CM_RGAM_LUT_DATA, 0, 726 CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); 727 REG_SET(CM_RGAM_LUT_DATA, 0, 728 CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); 729 REG_SET(CM_RGAM_LUT_DATA, 0, 730 CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); 731 732 } 733 734 } 735 736 static bool opp_set_regamma_pwl( 737 struct output_pixel_processor *opp, const struct pwl_params *params) 738 { 739 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 740 741 opp_power_on_regamma_lut(opp, true); 742 opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe); 743 744 if (oppn10->is_write_to_ram_a_safe) 745 opp_program_regamma_luta_settings(opp, params); 746 else 747 opp_program_regamma_lutb_settings(opp, params); 748 749 opp_program_regamma_lut( 750 opp, params->rgb_resulted, params->hw_points_num); 751 752 return true; 753 } 754 755 static void opp_set_stereo_polarity( 756 struct output_pixel_processor *opp, 757 bool enable, bool rightEyePolarity) 758 { 759 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 760 761 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable); 762 } 763 764 /*****************************************/ 765 /* Constructor, Destructor */ 766 /*****************************************/ 767 768 static void dcn10_opp_destroy(struct output_pixel_processor **opp) 769 { 770 dm_free(TO_DCN10_OPP(*opp)); 771 *opp = NULL; 772 } 773 774 static struct opp_funcs dcn10_opp_funcs = { 775 .opp_power_on_regamma_lut = opp_power_on_regamma_lut, 776 .opp_set_csc_adjustment = NULL, 777 .opp_set_csc_default = opp_set_output_csc_default, 778 .opp_set_dyn_expansion = opp_set_dyn_expansion, 779 .opp_program_regamma_pwl = opp_set_regamma_pwl, 780 .opp_set_regamma_mode = opp_set_regamma_mode, 781 .opp_program_fmt = opp_program_fmt, 782 .opp_program_bit_depth_reduction = opp_program_bit_depth_reduction, 783 .opp_set_stereo_polarity = opp_set_stereo_polarity, 784 .opp_destroy = dcn10_opp_destroy 785 }; 786 787 void dcn10_opp_construct(struct dcn10_opp *oppn10, 788 struct dc_context *ctx, 789 uint32_t inst, 790 const struct dcn10_opp_registers *regs, 791 const struct dcn10_opp_shift *opp_shift, 792 const struct dcn10_opp_mask *opp_mask) 793 { 794 oppn10->base.ctx = ctx; 795 oppn10->base.inst = inst; 796 oppn10->base.funcs = &dcn10_opp_funcs; 797 798 oppn10->regs = regs; 799 oppn10->opp_shift = opp_shift; 800 oppn10->opp_mask = opp_mask; 801 } 802