1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dcn10_opp.h" 28 #include "reg_helper.h" 29 30 #define REG(reg) \ 31 (oppn10->regs->reg) 32 33 #undef FN 34 #define FN(reg_name, field_name) \ 35 oppn10->opp_shift->field_name, oppn10->opp_mask->field_name 36 37 #define CTX \ 38 oppn10->base.ctx 39 40 41 42 /************* FORMATTER ************/ 43 44 /** 45 * set_truncation 46 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp 47 * 2) enable truncation 48 * 3) HW remove 12bit FMT support for DCE11 power saving reason. 49 */ 50 static void set_truncation( 51 struct dcn10_opp *oppn10, 52 const struct bit_depth_reduction_params *params) 53 { 54 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, 55 FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED, 56 FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, 57 FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); 58 } 59 60 static void set_spatial_dither( 61 struct dcn10_opp *oppn10, 62 const struct bit_depth_reduction_params *params) 63 { 64 /*Disable spatial (random) dithering*/ 65 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, 66 FMT_SPATIAL_DITHER_EN, 0, 67 FMT_SPATIAL_DITHER_MODE, 0, 68 FMT_SPATIAL_DITHER_DEPTH, 0, 69 FMT_TEMPORAL_DITHER_EN, 0, 70 FMT_HIGHPASS_RANDOM_ENABLE, 0, 71 FMT_FRAME_RANDOM_ENABLE, 0, 72 FMT_RGB_RANDOM_ENABLE, 0); 73 74 75 /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ 76 if (params->flags.FRAME_RANDOM == 1) { 77 if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { 78 REG_UPDATE_2(FMT_CONTROL, 79 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, 80 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); 81 } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { 82 REG_UPDATE_2(FMT_CONTROL, 83 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, 84 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); 85 } else { 86 return; 87 } 88 } else { 89 REG_UPDATE_2(FMT_CONTROL, 90 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, 91 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); 92 } 93 94 /*Set seed for random values for 95 * spatial dithering for R,G,B channels*/ 96 97 REG_SET(FMT_DITHER_RAND_R_SEED, 0, 98 FMT_RAND_R_SEED, params->r_seed_value); 99 100 REG_SET(FMT_DITHER_RAND_G_SEED, 0, 101 FMT_RAND_G_SEED, params->g_seed_value); 102 103 REG_SET(FMT_DITHER_RAND_B_SEED, 0, 104 FMT_RAND_B_SEED, params->b_seed_value); 105 106 /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero 107 * offset for the R/Cr channel, lower 4LSB 108 * is forced to zeros. Typically set to 0 109 * RGB and 0x80000 YCbCr. 110 */ 111 /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero 112 * offset for the G/Y channel, lower 4LSB is 113 * forced to zeros. Typically set to 0 RGB 114 * and 0x80000 YCbCr. 115 */ 116 /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero 117 * offset for the B/Cb channel, lower 4LSB is 118 * forced to zeros. Typically set to 0 RGB and 119 * 0x80000 YCbCr. 120 */ 121 122 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, 123 /*Enable spatial dithering*/ 124 FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, 125 /* Set spatial dithering mode 126 * (default is Seed patterrn AAAA...) 127 */ 128 FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, 129 /*Set spatial dithering bit depth*/ 130 FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, 131 /*Disable High pass filter*/ 132 FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, 133 /*Reset only at startup*/ 134 FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, 135 /*Set RGB data dithered with x^28+x^3+1*/ 136 FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); 137 } 138 139 static void oppn10_program_bit_depth_reduction( 140 struct output_pixel_processor *opp, 141 const struct bit_depth_reduction_params *params) 142 { 143 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 144 145 set_truncation(oppn10, params); 146 set_spatial_dither(oppn10, params); 147 /* TODO 148 * set_temporal_dither(oppn10, params); 149 */ 150 } 151 152 /** 153 * set_pixel_encoding 154 * 155 * Set Pixel Encoding 156 * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly 157 * 1: YCbCr 4:2:2 158 */ 159 static void set_pixel_encoding( 160 struct dcn10_opp *oppn10, 161 const struct clamping_and_pixel_encoding_params *params) 162 { 163 switch (params->pixel_encoding) { 164 165 case PIXEL_ENCODING_RGB: 166 case PIXEL_ENCODING_YCBCR444: 167 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); 168 break; 169 case PIXEL_ENCODING_YCBCR422: 170 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1); 171 break; 172 case PIXEL_ENCODING_YCBCR420: 173 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); 174 break; 175 default: 176 break; 177 } 178 } 179 180 /** 181 * Set Clamping 182 * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping) 183 * 1 for 8 bpc 184 * 2 for 10 bpc 185 * 3 for 12 bpc 186 * 7 for programable 187 * 2) Enable clamp if Limited range requested 188 */ 189 static void opp_set_clamping( 190 struct dcn10_opp *oppn10, 191 const struct clamping_and_pixel_encoding_params *params) 192 { 193 REG_UPDATE_2(FMT_CLAMP_CNTL, 194 FMT_CLAMP_DATA_EN, 0, 195 FMT_CLAMP_COLOR_FORMAT, 0); 196 197 switch (params->clamping_level) { 198 case CLAMPING_FULL_RANGE: 199 REG_UPDATE_2(FMT_CLAMP_CNTL, 200 FMT_CLAMP_DATA_EN, 1, 201 FMT_CLAMP_COLOR_FORMAT, 0); 202 break; 203 case CLAMPING_LIMITED_RANGE_8BPC: 204 REG_UPDATE_2(FMT_CLAMP_CNTL, 205 FMT_CLAMP_DATA_EN, 1, 206 FMT_CLAMP_COLOR_FORMAT, 1); 207 break; 208 case CLAMPING_LIMITED_RANGE_10BPC: 209 REG_UPDATE_2(FMT_CLAMP_CNTL, 210 FMT_CLAMP_DATA_EN, 1, 211 FMT_CLAMP_COLOR_FORMAT, 2); 212 213 break; 214 case CLAMPING_LIMITED_RANGE_12BPC: 215 REG_UPDATE_2(FMT_CLAMP_CNTL, 216 FMT_CLAMP_DATA_EN, 1, 217 FMT_CLAMP_COLOR_FORMAT, 3); 218 break; 219 case CLAMPING_LIMITED_RANGE_PROGRAMMABLE: 220 /* TODO */ 221 default: 222 break; 223 } 224 225 } 226 227 static void oppn10_set_dyn_expansion( 228 struct output_pixel_processor *opp, 229 enum dc_color_space color_sp, 230 enum dc_color_depth color_dpth, 231 enum signal_type signal) 232 { 233 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 234 235 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 236 FMT_DYNAMIC_EXP_EN, 0, 237 FMT_DYNAMIC_EXP_MODE, 0); 238 239 /*00 - 10-bit -> 12-bit dynamic expansion*/ 240 /*01 - 8-bit -> 12-bit dynamic expansion*/ 241 if (signal == SIGNAL_TYPE_HDMI_TYPE_A || 242 signal == SIGNAL_TYPE_DISPLAY_PORT || 243 signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 signal == SIGNAL_TYPE_VIRTUAL) { 245 switch (color_dpth) { 246 case COLOR_DEPTH_888: 247 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 248 FMT_DYNAMIC_EXP_EN, 1, 249 FMT_DYNAMIC_EXP_MODE, 1); 250 break; 251 case COLOR_DEPTH_101010: 252 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 253 FMT_DYNAMIC_EXP_EN, 1, 254 FMT_DYNAMIC_EXP_MODE, 0); 255 break; 256 case COLOR_DEPTH_121212: 257 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, 258 FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/ 259 FMT_DYNAMIC_EXP_MODE, 0); 260 break; 261 default: 262 break; 263 } 264 } 265 } 266 267 static void opp_program_clamping_and_pixel_encoding( 268 struct output_pixel_processor *opp, 269 const struct clamping_and_pixel_encoding_params *params) 270 { 271 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 272 273 opp_set_clamping(oppn10, params); 274 set_pixel_encoding(oppn10, params); 275 } 276 277 static void oppn10_program_fmt( 278 struct output_pixel_processor *opp, 279 struct bit_depth_reduction_params *fmt_bit_depth, 280 struct clamping_and_pixel_encoding_params *clamping) 281 { 282 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 283 284 if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420) 285 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); 286 287 /* dithering is affected by <CrtcSourceSelect>, hence should be 288 * programmed afterwards */ 289 oppn10_program_bit_depth_reduction( 290 opp, 291 fmt_bit_depth); 292 293 opp_program_clamping_and_pixel_encoding( 294 opp, 295 clamping); 296 297 return; 298 } 299 300 301 302 static void oppn10_set_stereo_polarity( 303 struct output_pixel_processor *opp, 304 bool enable, bool rightEyePolarity) 305 { 306 struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); 307 308 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable); 309 } 310 311 /*****************************************/ 312 /* Constructor, Destructor */ 313 /*****************************************/ 314 315 static void dcn10_opp_destroy(struct output_pixel_processor **opp) 316 { 317 kfree(TO_DCN10_OPP(*opp)); 318 *opp = NULL; 319 } 320 321 static struct opp_funcs dcn10_opp_funcs = { 322 .opp_set_dyn_expansion = oppn10_set_dyn_expansion, 323 .opp_program_fmt = oppn10_program_fmt, 324 .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction, 325 .opp_set_stereo_polarity = oppn10_set_stereo_polarity, 326 .opp_destroy = dcn10_opp_destroy 327 }; 328 329 void dcn10_opp_construct(struct dcn10_opp *oppn10, 330 struct dc_context *ctx, 331 uint32_t inst, 332 const struct dcn10_opp_registers *regs, 333 const struct dcn10_opp_shift *opp_shift, 334 const struct dcn10_opp_mask *opp_mask) 335 { 336 int i; 337 oppn10->base.ctx = ctx; 338 oppn10->base.inst = inst; 339 oppn10->base.funcs = &dcn10_opp_funcs; 340 341 oppn10->base.mpc_tree.dpp[0] = inst; 342 oppn10->base.mpc_tree.mpcc[0] = inst; 343 oppn10->base.mpc_tree.num_pipes = 1; 344 for (i = 0; i < MAX_PIPES; i++) 345 oppn10->base.mpcc_disconnect_pending[i] = false; 346 347 oppn10->regs = regs; 348 oppn10->opp_shift = opp_shift; 349 oppn10->opp_mask = opp_mask; 350 } 351 352