1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MPCC_DCN10_H__ 26 #define __DC_MPCC_DCN10_H__ 27 28 #include "mpc.h" 29 30 #define TO_DCN10_MPC(mpc_base) \ 31 container_of(mpc_base, struct dcn10_mpc, base) 32 33 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ 34 SRII(MPCC_TOP_SEL, MPCC, inst),\ 35 SRII(MPCC_BOT_SEL, MPCC, inst),\ 36 SRII(MPCC_CONTROL, MPCC, inst),\ 37 SRII(MPCC_STATUS, MPCC, inst),\ 38 SRII(MPCC_OPP_ID, MPCC, inst),\ 39 SRII(MPCC_BG_G_Y, MPCC, inst),\ 40 SRII(MPCC_BG_R_CR, MPCC, inst),\ 41 SRII(MPCC_BG_B_CB, MPCC, inst),\ 42 SRII(MPCC_BG_B_CB, MPCC, inst),\ 43 SRII(MPCC_SM_CONTROL, MPCC, inst) 44 45 #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \ 46 SRII(MUX, MPC_OUT, inst) 47 48 #define MPC_COMMON_REG_VARIABLE_LIST \ 49 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \ 50 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \ 51 uint32_t MPCC_CONTROL[MAX_MPCC]; \ 52 uint32_t MPCC_STATUS[MAX_MPCC]; \ 53 uint32_t MPCC_OPP_ID[MAX_MPCC]; \ 54 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \ 55 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \ 56 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \ 57 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \ 58 uint32_t MUX[MAX_OPP]; 59 60 #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 61 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ 62 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ 63 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ 64 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ 65 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ 66 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ 67 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\ 68 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\ 69 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ 70 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ 71 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ 72 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ 73 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ 74 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ 75 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ 76 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ 77 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ 78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ 79 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ 80 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ 81 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) 82 83 #define MPC_REG_FIELD_LIST(type) \ 84 type MPCC_TOP_SEL;\ 85 type MPCC_BOT_SEL;\ 86 type MPCC_MODE;\ 87 type MPCC_ALPHA_BLND_MODE;\ 88 type MPCC_ALPHA_MULTIPLIED_MODE;\ 89 type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\ 90 type MPCC_GLOBAL_ALPHA;\ 91 type MPCC_GLOBAL_GAIN;\ 92 type MPCC_IDLE;\ 93 type MPCC_BUSY;\ 94 type MPCC_OPP_ID;\ 95 type MPCC_BG_G_Y;\ 96 type MPCC_BG_R_CR;\ 97 type MPCC_BG_B_CB;\ 98 type MPCC_SM_EN;\ 99 type MPCC_SM_MODE;\ 100 type MPCC_SM_FRAME_ALT;\ 101 type MPCC_SM_FIELD_ALT;\ 102 type MPCC_SM_FORCE_NEXT_FRAME_POL;\ 103 type MPCC_SM_FORCE_NEXT_TOP_POL;\ 104 type MPC_OUT_MUX; 105 106 struct dcn_mpc_registers { 107 MPC_COMMON_REG_VARIABLE_LIST 108 }; 109 110 struct dcn_mpc_shift { 111 MPC_REG_FIELD_LIST(uint8_t) 112 }; 113 114 struct dcn_mpc_mask { 115 MPC_REG_FIELD_LIST(uint32_t) 116 }; 117 118 struct dcn10_mpc { 119 struct mpc base; 120 121 int mpcc_in_use_mask; 122 int num_mpcc; 123 const struct dcn_mpc_registers *mpc_regs; 124 const struct dcn_mpc_shift *mpc_shift; 125 const struct dcn_mpc_mask *mpc_mask; 126 }; 127 128 void dcn10_mpc_construct(struct dcn10_mpc *mpcc10, 129 struct dc_context *ctx, 130 const struct dcn_mpc_registers *mpc_regs, 131 const struct dcn_mpc_shift *mpc_shift, 132 const struct dcn_mpc_mask *mpc_mask, 133 int num_mpcc); 134 135 struct mpcc *mpc1_insert_plane( 136 struct mpc *mpc, 137 struct mpc_tree *tree, 138 struct mpcc_blnd_cfg *blnd_cfg, 139 struct mpcc_sm_cfg *sm_cfg, 140 struct mpcc *insert_above_mpcc, 141 int dpp_id, 142 int mpcc_id); 143 144 void mpc1_remove_mpcc( 145 struct mpc *mpc, 146 struct mpc_tree *tree, 147 struct mpcc *mpcc); 148 149 void mpc1_mpc_init( 150 struct mpc *mpc); 151 152 void mpc1_mpc_init_single_inst( 153 struct mpc *mpc, 154 unsigned int mpcc_id); 155 156 void mpc1_assert_idle_mpcc( 157 struct mpc *mpc, 158 int id); 159 160 void mpc1_set_bg_color( 161 struct mpc *mpc, 162 struct tg_color *bg_color, 163 int id); 164 165 void mpc1_update_stereo_mix( 166 struct mpc *mpc, 167 struct mpcc_sm_cfg *sm_cfg, 168 int mpcc_id); 169 170 bool mpc1_is_mpcc_idle( 171 struct mpc *mpc, 172 int mpcc_id); 173 174 void mpc1_assert_mpcc_idle_before_connect( 175 struct mpc *mpc, 176 int mpcc_id); 177 178 void mpc1_init_mpcc_list_from_hw( 179 struct mpc *mpc, 180 struct mpc_tree *tree); 181 182 struct mpcc *mpc1_get_mpcc( 183 struct mpc *mpc, 184 int mpcc_id); 185 186 struct mpcc *mpc1_get_mpcc_for_dpp( 187 struct mpc_tree *tree, 188 int dpp_id); 189 190 void mpc1_read_mpcc_state( 191 struct mpc *mpc, 192 int mpcc_inst, 193 struct mpcc_state *s); 194 195 #endif 196