1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MPC_DCN10_H__ 26 #define __DC_MPC_DCN10_H__ 27 28 #include "mpc.h" 29 30 #define TO_DCN10_MPC(mpc_base)\ 31 container_of(mpc_base, struct dcn10_mpc, base) 32 33 #define MAX_MPCC 4 34 #define MAX_MPC_OUT 4 35 #define MAX_OPP 4 36 37 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ 38 SRII(MPCC_TOP_SEL, MPCC, inst),\ 39 SRII(MPCC_BOT_SEL, MPCC, inst),\ 40 SRII(MPCC_CONTROL, MPCC, inst),\ 41 SRII(MPCC_STATUS, MPCC, inst),\ 42 SRII(MPCC_OPP_ID, MPCC, inst),\ 43 SRII(MPCC_BG_G_Y, MPCC, inst),\ 44 SRII(MPCC_BG_R_CR, MPCC, inst),\ 45 SRII(MPCC_BG_B_CB, MPCC, inst),\ 46 SRII(MPCC_BG_B_CB, MPCC, inst),\ 47 SRII(MUX, MPC_OUT, inst),\ 48 SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst) 49 50 struct dcn_mpc_registers { 51 uint32_t MPCC_TOP_SEL[MAX_MPCC]; 52 uint32_t MPCC_BOT_SEL[MAX_MPCC]; 53 uint32_t MPCC_CONTROL[MAX_MPCC]; 54 uint32_t MPCC_STATUS[MAX_MPCC]; 55 uint32_t MPCC_OPP_ID[MAX_MPCC]; 56 uint32_t MPCC_BG_G_Y[MAX_MPCC]; 57 uint32_t MPCC_BG_R_CR[MAX_MPCC]; 58 uint32_t MPCC_BG_B_CB[MAX_MPCC]; 59 uint32_t MUX[MAX_MPC_OUT]; 60 uint32_t OPP_PIPE_CONTROL[MAX_OPP]; 61 }; 62 63 #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ 65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ 66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ 67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ 68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ 69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ 70 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ 71 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ 72 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ 73 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ 74 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ 75 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ 76 SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) 77 78 #define MPC_REG_FIELD_LIST(type) \ 79 type MPCC_TOP_SEL;\ 80 type MPCC_BOT_SEL;\ 81 type MPCC_MODE;\ 82 type MPCC_ALPHA_BLND_MODE;\ 83 type MPCC_ALPHA_MULTIPLIED_MODE;\ 84 type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\ 85 type MPCC_IDLE;\ 86 type MPCC_OPP_ID;\ 87 type MPCC_BG_G_Y;\ 88 type MPCC_BG_R_CR;\ 89 type MPCC_BG_B_CB;\ 90 type MPC_OUT_MUX;\ 91 type OPP_PIPE_CLOCK_EN;\ 92 93 struct dcn_mpc_shift { 94 MPC_REG_FIELD_LIST(uint8_t) 95 }; 96 97 struct dcn_mpc_mask { 98 MPC_REG_FIELD_LIST(uint32_t) 99 }; 100 101 struct dcn10_mpc { 102 struct mpc base; 103 const struct dcn_mpc_registers *mpc_regs; 104 const struct dcn_mpc_shift *mpc_shift; 105 const struct dcn_mpc_mask *mpc_mask; 106 }; 107 108 void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc, 109 uint8_t dpp_idx, 110 uint8_t mpcc_idx, 111 uint8_t opp_idx); 112 113 void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc, 114 struct mpc_tree_cfg *tree_cfg); 115 116 bool dcn10_remove_dpp(struct dcn10_mpc *mpc, 117 struct mpc_tree_cfg *tree_cfg, 118 uint8_t idx); 119 120 void dcn10_add_dpp(struct dcn10_mpc *mpc, 121 struct mpc_tree_cfg *tree_cfg, 122 uint8_t dpp_idx, 123 uint8_t mpcc_idx, 124 uint8_t position); 125 126 void wait_mpcc_idle(struct dcn10_mpc *mpc, 127 uint8_t mpcc_id); 128 129 void dcn10_set_mpc_tree(struct dcn10_mpc *mpc, 130 struct mpc_tree_cfg *tree_cfg); 131 132 void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc, 133 unsigned int mpcc_inst, 134 struct tg_color *bg_color); 135 #endif 136