1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn10_mpc.h" 28 #include "dc.h" 29 #include "mem_input.h" 30 31 #define REG(reg)\ 32 mpc10->mpc_regs->reg 33 34 #define CTX \ 35 mpc10->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name 40 41 #define MODE_TOP_ONLY 1 42 #define MODE_BLEND 3 43 #define BLND_PP_ALPHA 0 44 #define BLND_GLOBAL_ALPHA 2 45 46 47 static void mpc10_set_bg_color( 48 struct dcn10_mpc *mpc10, 49 struct tg_color *bg_color, 50 int id) 51 { 52 /* mpc color is 12 bit. tg_color is 10 bit */ 53 /* todo: might want to use 16 bit to represent color and have each 54 * hw block translate to correct color depth. 55 */ 56 uint32_t bg_r_cr = bg_color->color_r_cr << 2; 57 uint32_t bg_g_y = bg_color->color_g_y << 2; 58 uint32_t bg_b_cb = bg_color->color_b_cb << 2; 59 60 REG_SET(MPCC_BG_R_CR[id], 0, 61 MPCC_BG_R_CR, bg_r_cr); 62 REG_SET(MPCC_BG_G_Y[id], 0, 63 MPCC_BG_G_Y, bg_g_y); 64 REG_SET(MPCC_BG_B_CB[id], 0, 65 MPCC_BG_B_CB, bg_b_cb); 66 } 67 68 static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) 69 { 70 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 71 72 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); 73 REG_WAIT(MPCC_STATUS[id], 74 MPCC_IDLE, 1, 75 1, 100000); 76 } 77 78 static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10) 79 { 80 int i; 81 int last_free_mpcc_id = -1; 82 83 for (i = 0; i < mpc10->num_mpcc; i++) { 84 uint32_t is_idle = 0; 85 86 if (mpc10->mpcc_in_use_mask & 1 << i) 87 continue; 88 89 last_free_mpcc_id = i; 90 REG_GET(MPCC_STATUS[i], MPCC_IDLE, &is_idle); 91 if (is_idle) 92 return i; 93 } 94 95 /* This assert should never trigger, we have mpcc leak if it does */ 96 ASSERT(last_free_mpcc_id != -1); 97 98 mpc10_assert_idle_mpcc(&mpc10->base, last_free_mpcc_id); 99 return last_free_mpcc_id; 100 } 101 102 static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int id) 103 { 104 unsigned int top_sel, mpc_busy, mpc_idle; 105 106 REG_GET(MPCC_TOP_SEL[id], 107 MPCC_TOP_SEL, &top_sel); 108 109 if (top_sel == 0xf) { 110 REG_GET_2(MPCC_STATUS[id], 111 MPCC_BUSY, &mpc_busy, 112 MPCC_IDLE, &mpc_idle); 113 114 ASSERT(mpc_busy == 0); 115 ASSERT(mpc_idle == 1); 116 } 117 } 118 119 static void mpc10_mpcc_remove( 120 struct mpc *mpc, 121 struct output_pixel_processor *opp, 122 int dpp_id) 123 { 124 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 125 int mpcc_id, z_idx; 126 127 for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) 128 if (opp->mpc_tree.dpp[z_idx] == dpp_id) 129 break; 130 if (z_idx == opp->mpc_tree.num_pipes) { 131 ASSERT(0); 132 return; 133 } 134 mpcc_id = opp->mpc_tree.mpcc[z_idx]; 135 136 REG_SET(MPCC_OPP_ID[mpcc_id], 0, 137 MPCC_OPP_ID, 0xf); 138 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, 139 MPCC_TOP_SEL, 0xf); 140 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, 141 MPCC_BOT_SEL, 0xf); 142 143 if (z_idx > 0) { 144 int top_mpcc_id = opp->mpc_tree.mpcc[z_idx - 1]; 145 146 if (z_idx + 1 < opp->mpc_tree.num_pipes) 147 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 148 MPCC_BOT_SEL, opp->mpc_tree.mpcc[z_idx + 1]); 149 else { 150 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 151 MPCC_BOT_SEL, 0xf); 152 REG_UPDATE(MPCC_CONTROL[top_mpcc_id], 153 MPCC_MODE, MODE_TOP_ONLY); 154 } 155 } else if (opp->mpc_tree.num_pipes > 1) 156 REG_SET(MUX[opp->inst], 0, 157 MPC_OUT_MUX, opp->mpc_tree.mpcc[z_idx + 1]); 158 else 159 REG_SET(MUX[opp->inst], 0, MPC_OUT_MUX, 0xf); 160 161 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); 162 opp->mpc_tree.num_pipes--; 163 for (; z_idx < opp->mpc_tree.num_pipes; z_idx++) { 164 opp->mpc_tree.dpp[z_idx] = opp->mpc_tree.dpp[z_idx + 1]; 165 opp->mpc_tree.mpcc[z_idx] = opp->mpc_tree.mpcc[z_idx + 1]; 166 } 167 opp->mpc_tree.dpp[opp->mpc_tree.num_pipes] = 0xdeadbeef; 168 opp->mpc_tree.mpcc[opp->mpc_tree.num_pipes] = 0xdeadbeef; 169 } 170 171 static void mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg) 172 { 173 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 174 int alpha_blnd_mode = cfg->per_pixel_alpha ? 175 BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; 176 int mpcc_mode = MODE_TOP_ONLY; 177 int mpcc_id, z_idx; 178 179 ASSERT(cfg->z_index < mpc10->num_mpcc); 180 181 for (z_idx = 0; z_idx < cfg->opp->mpc_tree.num_pipes; z_idx++) 182 if (cfg->opp->mpc_tree.dpp[z_idx] == cfg->mi->inst) 183 break; 184 if (z_idx == cfg->opp->mpc_tree.num_pipes) { 185 ASSERT(cfg->z_index <= cfg->opp->mpc_tree.num_pipes); 186 mpcc_id = mpc10_get_idle_mpcc_id(mpc10); 187 /*todo: remove hack*/ 188 mpcc_id = cfg->mi->inst; 189 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); 190 191 if (mpc->ctx->dc->debug.sanity_checks) 192 mpc10_assert_mpcc_idle_before_connect(mpc10, mpcc_id); 193 } else { 194 ASSERT(cfg->z_index < cfg->opp->mpc_tree.num_pipes); 195 mpcc_id = cfg->opp->mpc_tree.mpcc[z_idx]; 196 mpc10_mpcc_remove(mpc, cfg->opp, cfg->mi->inst); 197 } 198 199 REG_SET(MPCC_OPP_ID[mpcc_id], 0, 200 MPCC_OPP_ID, cfg->opp->inst); 201 202 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, 203 MPCC_TOP_SEL, cfg->mi->inst); 204 205 if (cfg->z_index > 0) { 206 int top_mpcc_id = cfg->opp->mpc_tree.mpcc[cfg->z_index - 1]; 207 208 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 209 MPCC_BOT_SEL, mpcc_id); 210 REG_UPDATE(MPCC_CONTROL[top_mpcc_id], 211 MPCC_MODE, MODE_BLEND); 212 } else 213 REG_SET(MUX[cfg->opp->inst], 0, MPC_OUT_MUX, mpcc_id); 214 215 if (cfg->z_index < cfg->opp->mpc_tree.num_pipes) { 216 int bot_mpcc_id = cfg->opp->mpc_tree.mpcc[cfg->z_index]; 217 218 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, 219 MPCC_BOT_SEL, bot_mpcc_id); 220 mpcc_mode = MODE_BLEND; 221 } 222 223 REG_SET_4(MPCC_CONTROL[mpcc_id], 0xffffffff, 224 MPCC_MODE, mpcc_mode, 225 MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, 226 MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha, 227 MPCC_BLND_ACTIVE_OVERLAP_ONLY, false); 228 229 mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id); 230 231 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 232 for (z_idx = cfg->z_index; z_idx < cfg->opp->mpc_tree.num_pipes; z_idx++) { 233 cfg->opp->mpc_tree.dpp[z_idx + 1] = cfg->opp->mpc_tree.dpp[z_idx]; 234 cfg->opp->mpc_tree.mpcc[z_idx + 1] = cfg->opp->mpc_tree.mpcc[z_idx]; 235 } 236 cfg->opp->mpc_tree.dpp[cfg->z_index] = cfg->mi->inst; 237 cfg->opp->mpc_tree.mpcc[cfg->z_index] = mpcc_id; 238 cfg->opp->mpc_tree.num_pipes++; 239 cfg->mi->opp_id = cfg->opp->inst; 240 cfg->mi->mpcc_id = mpcc_id; 241 } 242 243 const struct mpc_funcs dcn10_mpc_funcs = { 244 .add = mpc10_mpcc_add, 245 .remove = mpc10_mpcc_remove, 246 .wait_for_idle = mpc10_assert_idle_mpcc 247 }; 248 249 void dcn10_mpc_construct(struct dcn10_mpc *mpc10, 250 struct dc_context *ctx, 251 const struct dcn_mpc_registers *mpc_regs, 252 const struct dcn_mpc_shift *mpc_shift, 253 const struct dcn_mpc_mask *mpc_mask, 254 int num_mpcc) 255 { 256 mpc10->base.ctx = ctx; 257 258 mpc10->base.funcs = &dcn10_mpc_funcs; 259 260 mpc10->mpc_regs = mpc_regs; 261 mpc10->mpc_shift = mpc_shift; 262 mpc10->mpc_mask = mpc_mask; 263 264 mpc10->mpcc_in_use_mask = 0; 265 mpc10->num_mpcc = num_mpcc; 266 } 267