1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn10_mpc.h" 28 29 #define REG(reg)\ 30 mpc10->mpc_regs->reg 31 32 #define CTX \ 33 mpc10->base.ctx 34 35 #undef FN 36 #define FN(reg_name, field_name) \ 37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name 38 39 40 void mpc1_set_bg_color(struct mpc *mpc, 41 struct tg_color *bg_color, 42 int mpcc_id) 43 { 44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); 46 uint32_t bg_r_cr, bg_g_y, bg_b_cb; 47 48 bottommost_mpcc->blnd_cfg.black_color = *bg_color; 49 50 /* find bottommost mpcc. */ 51 while (bottommost_mpcc->mpcc_bot) { 52 /* avoid circular linked link */ 53 ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot); 54 if (bottommost_mpcc == bottommost_mpcc->mpcc_bot) 55 break; 56 57 bottommost_mpcc = bottommost_mpcc->mpcc_bot; 58 } 59 60 /* mpc color is 12 bit. tg_color is 10 bit */ 61 /* todo: might want to use 16 bit to represent color and have each 62 * hw block translate to correct color depth. 63 */ 64 bg_r_cr = bg_color->color_r_cr << 2; 65 bg_g_y = bg_color->color_g_y << 2; 66 bg_b_cb = bg_color->color_b_cb << 2; 67 68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, 69 MPCC_BG_R_CR, bg_r_cr); 70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, 71 MPCC_BG_G_Y, bg_g_y); 72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, 73 MPCC_BG_B_CB, bg_b_cb); 74 } 75 76 static void mpc1_update_blending( 77 struct mpc *mpc, 78 struct mpcc_blnd_cfg *blnd_cfg, 79 int mpcc_id) 80 { 81 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 83 84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], 85 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, 86 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, 87 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, 88 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, 89 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); 90 91 mpcc->blnd_cfg = *blnd_cfg; 92 } 93 94 void mpc1_update_stereo_mix( 95 struct mpc *mpc, 96 struct mpcc_sm_cfg *sm_cfg, 97 int mpcc_id) 98 { 99 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 100 101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], 102 MPCC_SM_EN, sm_cfg->enable, 103 MPCC_SM_MODE, sm_cfg->sm_mode, 104 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt, 105 MPCC_SM_FIELD_ALT, sm_cfg->field_alt, 106 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity, 107 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity); 108 } 109 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) 110 { 111 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 112 113 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); 114 REG_WAIT(MPCC_STATUS[id], 115 MPCC_IDLE, 1, 116 1, 100000); 117 } 118 119 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) 120 { 121 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 122 123 ASSERT(mpcc_id < mpc10->num_mpcc); 124 return &(mpc->mpcc_array[mpcc_id]); 125 } 126 127 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) 128 { 129 struct mpcc *tmp_mpcc = tree->opp_list; 130 131 while (tmp_mpcc != NULL) { 132 if (tmp_mpcc->dpp_id == dpp_id) 133 return tmp_mpcc; 134 tmp_mpcc = tmp_mpcc->mpcc_bot; 135 } 136 return NULL; 137 } 138 139 bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) 140 { 141 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 142 unsigned int top_sel; 143 unsigned int opp_id; 144 unsigned int idle; 145 146 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); 147 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 148 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); 149 if (top_sel == 0xf && opp_id == 0xf && idle) 150 return true; 151 else 152 return false; 153 } 154 155 void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) 156 { 157 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 158 unsigned int top_sel, mpc_busy, mpc_idle; 159 160 REG_GET(MPCC_TOP_SEL[mpcc_id], 161 MPCC_TOP_SEL, &top_sel); 162 163 if (top_sel == 0xf) { 164 REG_GET_2(MPCC_STATUS[mpcc_id], 165 MPCC_BUSY, &mpc_busy, 166 MPCC_IDLE, &mpc_idle); 167 168 ASSERT(mpc_busy == 0); 169 ASSERT(mpc_idle == 1); 170 } 171 } 172 173 /* 174 * Insert DPP into MPC tree based on specified blending position. 175 * Only used for planes that are part of blending chain for OPP output 176 * 177 * Parameters: 178 * [in/out] mpc - MPC context. 179 * [in/out] tree - MPC tree structure that plane will be added to. 180 * [in] blnd_cfg - MPCC blending configuration for the new blending layer. 181 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. 182 * stereo mix must disable for the very bottom layer of the tree config. 183 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. 184 * [in] dpp_id - DPP instance for the plane to be added. 185 * [in] mpcc_id - The MPCC physical instance to use for blending. 186 * 187 * Return: struct mpcc* - MPCC that was added. 188 */ 189 struct mpcc *mpc1_insert_plane( 190 struct mpc *mpc, 191 struct mpc_tree *tree, 192 struct mpcc_blnd_cfg *blnd_cfg, 193 struct mpcc_sm_cfg *sm_cfg, 194 struct mpcc *insert_above_mpcc, 195 int dpp_id, 196 int mpcc_id) 197 { 198 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 199 struct mpcc *new_mpcc = NULL; 200 201 /* sanity check parameters */ 202 ASSERT(mpcc_id < mpc10->num_mpcc); 203 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); 204 205 if (insert_above_mpcc) { 206 /* check insert_above_mpcc exist in tree->opp_list */ 207 struct mpcc *temp_mpcc = tree->opp_list; 208 209 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) 210 temp_mpcc = temp_mpcc->mpcc_bot; 211 if (temp_mpcc == NULL) 212 return NULL; 213 } 214 215 /* Get and update MPCC struct parameters */ 216 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id); 217 new_mpcc->dpp_id = dpp_id; 218 219 /* program mux and MPCC_MODE */ 220 if (insert_above_mpcc) { 221 new_mpcc->mpcc_bot = insert_above_mpcc; 222 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); 223 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); 224 } else { 225 new_mpcc->mpcc_bot = NULL; 226 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 227 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY); 228 } 229 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); 230 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); 231 232 /* Configure VUPDATE lock set for this MPCC to map to the OPP */ 233 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); 234 235 /* update mpc tree mux setting */ 236 if (tree->opp_list == insert_above_mpcc) { 237 /* insert the toppest mpcc */ 238 tree->opp_list = new_mpcc; 239 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); 240 } else { 241 /* find insert position */ 242 struct mpcc *temp_mpcc = tree->opp_list; 243 244 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) 245 temp_mpcc = temp_mpcc->mpcc_bot; 246 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) { 247 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); 248 temp_mpcc->mpcc_bot = new_mpcc; 249 if (!insert_above_mpcc) 250 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], 251 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); 252 } 253 } 254 255 /* update the blending configuration */ 256 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id); 257 258 /* update the stereo mix settings, if provided */ 259 if (sm_cfg != NULL) { 260 new_mpcc->sm_cfg = *sm_cfg; 261 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id); 262 } 263 264 /* mark this mpcc as in use */ 265 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 266 267 return new_mpcc; 268 } 269 270 /* 271 * Remove a specified MPCC from the MPC tree. 272 * 273 * Parameters: 274 * [in/out] mpc - MPC context. 275 * [in/out] tree - MPC tree structure that plane will be removed from. 276 * [in/out] mpcc - MPCC to be removed from tree. 277 * 278 * Return: void 279 */ 280 void mpc1_remove_mpcc( 281 struct mpc *mpc, 282 struct mpc_tree *tree, 283 struct mpcc *mpcc_to_remove) 284 { 285 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 286 bool found = false; 287 int mpcc_id = mpcc_to_remove->mpcc_id; 288 289 if (tree->opp_list == mpcc_to_remove) { 290 found = true; 291 /* remove MPCC from top of tree */ 292 if (mpcc_to_remove->mpcc_bot) { 293 /* set the next MPCC in list to be the top MPCC */ 294 tree->opp_list = mpcc_to_remove->mpcc_bot; 295 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); 296 } else { 297 /* there are no other MPCC is list */ 298 tree->opp_list = NULL; 299 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); 300 } 301 } else { 302 /* find mpcc to remove MPCC list */ 303 struct mpcc *temp_mpcc = tree->opp_list; 304 305 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove) 306 temp_mpcc = temp_mpcc->mpcc_bot; 307 308 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) { 309 found = true; 310 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot; 311 if (mpcc_to_remove->mpcc_bot) { 312 /* remove MPCC in middle of list */ 313 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, 314 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id); 315 } else { 316 /* remove MPCC from bottom of list */ 317 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, 318 MPCC_BOT_SEL, 0xf); 319 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], 320 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); 321 } 322 } 323 } 324 325 if (found) { 326 /* turn off MPCC mux registers */ 327 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 328 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 329 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 330 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf); 331 332 /* mark this mpcc as not in use */ 333 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); 334 mpcc_to_remove->dpp_id = 0xf; 335 mpcc_to_remove->mpcc_bot = NULL; 336 } else { 337 /* In case of resume from S3/S4, remove mpcc from bios left over */ 338 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 339 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 340 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 341 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf); 342 } 343 } 344 345 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) 346 { 347 mpcc->mpcc_id = mpcc_inst; 348 mpcc->dpp_id = 0xf; 349 mpcc->mpcc_bot = NULL; 350 mpcc->blnd_cfg.overlap_only = false; 351 mpcc->blnd_cfg.global_alpha = 0xff; 352 mpcc->blnd_cfg.global_gain = 0xff; 353 mpcc->sm_cfg.enable = false; 354 } 355 356 /* 357 * Reset the MPCC HW status by disconnecting all muxes. 358 * 359 * Parameters: 360 * [in/out] mpc - MPC context. 361 * 362 * Return: void 363 */ 364 void mpc1_mpc_init(struct mpc *mpc) 365 { 366 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 367 int mpcc_id; 368 int opp_id; 369 370 mpc10->mpcc_in_use_mask = 0; 371 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { 372 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 373 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 374 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 375 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf); 376 377 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); 378 } 379 380 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { 381 if (REG(MUX[opp_id])) 382 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); 383 } 384 } 385 386 void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) 387 { 388 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 389 int opp_id; 390 391 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 392 393 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 394 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 395 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 396 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf); 397 398 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); 399 400 if (opp_id < MAX_OPP && REG(MUX[opp_id])) 401 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); 402 } 403 404 405 void mpc1_init_mpcc_list_from_hw( 406 struct mpc *mpc, 407 struct mpc_tree *tree) 408 { 409 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 410 unsigned int opp_id; 411 unsigned int top_sel; 412 unsigned int bot_sel; 413 unsigned int out_mux; 414 struct mpcc *mpcc; 415 int mpcc_id; 416 int bot_mpcc_id; 417 418 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); 419 420 if (out_mux != 0xf) { 421 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { 422 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 423 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); 424 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); 425 426 if (bot_sel == mpcc_id) 427 bot_sel = 0xf; 428 429 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { 430 mpcc = mpc1_get_mpcc(mpc, mpcc_id); 431 mpcc->dpp_id = top_sel; 432 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 433 434 if (out_mux == mpcc_id) 435 tree->opp_list = mpcc; 436 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) { 437 bot_mpcc_id = bot_sel; 438 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); 439 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); 440 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { 441 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id); 442 443 mpcc->mpcc_bot = mpcc_bottom; 444 } 445 } 446 } 447 } 448 } 449 } 450 451 void mpc1_read_mpcc_state( 452 struct mpc *mpc, 453 int mpcc_inst, 454 struct mpcc_state *s) 455 { 456 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 457 458 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); 459 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); 460 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); 461 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, 462 MPCC_ALPHA_BLND_MODE, &s->alpha_mode, 463 MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha, 464 MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only); 465 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, 466 MPCC_BUSY, &s->busy); 467 } 468 469 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) 470 { 471 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 472 473 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0); 474 } 475 476 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id) 477 { 478 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 479 uint32_t val = 0xf; 480 481 if (opp_id < MAX_OPP && REG(MUX[opp_id])) 482 REG_GET(MUX[opp_id], MPC_OUT_MUX, &val); 483 484 return val; 485 } 486 487 static const struct mpc_funcs dcn10_mpc_funcs = { 488 .read_mpcc_state = mpc1_read_mpcc_state, 489 .insert_plane = mpc1_insert_plane, 490 .remove_mpcc = mpc1_remove_mpcc, 491 .mpc_init = mpc1_mpc_init, 492 .mpc_init_single_inst = mpc1_mpc_init_single_inst, 493 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, 494 .wait_for_idle = mpc1_assert_idle_mpcc, 495 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, 496 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, 497 .update_blending = mpc1_update_blending, 498 .cursor_lock = mpc1_cursor_lock, 499 .set_denorm = NULL, 500 .set_denorm_clamp = NULL, 501 .set_output_csc = NULL, 502 .set_output_gamma = NULL, 503 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 504 .set_bg_color = mpc1_set_bg_color, 505 }; 506 507 void dcn10_mpc_construct(struct dcn10_mpc *mpc10, 508 struct dc_context *ctx, 509 const struct dcn_mpc_registers *mpc_regs, 510 const struct dcn_mpc_shift *mpc_shift, 511 const struct dcn_mpc_mask *mpc_mask, 512 int num_mpcc) 513 { 514 int i; 515 516 mpc10->base.ctx = ctx; 517 518 mpc10->base.funcs = &dcn10_mpc_funcs; 519 520 mpc10->mpc_regs = mpc_regs; 521 mpc10->mpc_shift = mpc_shift; 522 mpc10->mpc_mask = mpc_mask; 523 524 mpc10->mpcc_in_use_mask = 0; 525 mpc10->num_mpcc = num_mpcc; 526 527 for (i = 0; i < MAX_MPCC; i++) 528 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i); 529 } 530 531