1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn10_mpc.h" 28 29 #define REG(reg)\ 30 mpc10->mpc_regs->reg 31 32 #define CTX \ 33 mpc10->base.ctx 34 35 #undef FN 36 #define FN(reg_name, field_name) \ 37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name 38 39 40 void mpc1_set_bg_color(struct mpc *mpc, 41 struct tg_color *bg_color, 42 int mpcc_id) 43 { 44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 45 46 /* mpc color is 12 bit. tg_color is 10 bit */ 47 /* todo: might want to use 16 bit to represent color and have each 48 * hw block translate to correct color depth. 49 */ 50 uint32_t bg_r_cr = bg_color->color_r_cr << 2; 51 uint32_t bg_g_y = bg_color->color_g_y << 2; 52 uint32_t bg_b_cb = bg_color->color_b_cb << 2; 53 54 REG_SET(MPCC_BG_R_CR[mpcc_id], 0, 55 MPCC_BG_R_CR, bg_r_cr); 56 REG_SET(MPCC_BG_G_Y[mpcc_id], 0, 57 MPCC_BG_G_Y, bg_g_y); 58 REG_SET(MPCC_BG_B_CB[mpcc_id], 0, 59 MPCC_BG_B_CB, bg_b_cb); 60 } 61 62 static void mpc1_update_blending( 63 struct mpc *mpc, 64 struct mpcc_blnd_cfg *blnd_cfg, 65 int mpcc_id) 66 { 67 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 68 69 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], 70 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, 71 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, 72 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, 73 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, 74 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); 75 76 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); 77 } 78 79 void mpc1_update_stereo_mix( 80 struct mpc *mpc, 81 struct mpcc_sm_cfg *sm_cfg, 82 int mpcc_id) 83 { 84 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 85 86 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], 87 MPCC_SM_EN, sm_cfg->enable, 88 MPCC_SM_MODE, sm_cfg->sm_mode, 89 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt, 90 MPCC_SM_FIELD_ALT, sm_cfg->field_alt, 91 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity, 92 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity); 93 } 94 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) 95 { 96 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 97 98 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); 99 REG_WAIT(MPCC_STATUS[id], 100 MPCC_IDLE, 1, 101 1, 100000); 102 } 103 104 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) 105 { 106 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 107 108 ASSERT(mpcc_id < mpc10->num_mpcc); 109 return &(mpc->mpcc_array[mpcc_id]); 110 } 111 112 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) 113 { 114 struct mpcc *tmp_mpcc = tree->opp_list; 115 116 while (tmp_mpcc != NULL) { 117 if (tmp_mpcc->dpp_id == dpp_id) 118 return tmp_mpcc; 119 tmp_mpcc = tmp_mpcc->mpcc_bot; 120 } 121 return NULL; 122 } 123 124 bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id) 125 { 126 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 127 unsigned int top_sel; 128 unsigned int opp_id; 129 unsigned int idle; 130 131 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); 132 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 133 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); 134 if (top_sel == 0xf && opp_id == 0xf && idle) 135 return true; 136 else 137 return false; 138 } 139 140 void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) 141 { 142 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 143 unsigned int top_sel, mpc_busy, mpc_idle; 144 145 REG_GET(MPCC_TOP_SEL[mpcc_id], 146 MPCC_TOP_SEL, &top_sel); 147 148 if (top_sel == 0xf) { 149 REG_GET_2(MPCC_STATUS[mpcc_id], 150 MPCC_BUSY, &mpc_busy, 151 MPCC_IDLE, &mpc_idle); 152 153 ASSERT(mpc_busy == 0); 154 ASSERT(mpc_idle == 1); 155 } 156 } 157 158 /* 159 * Insert DPP into MPC tree based on specified blending position. 160 * Only used for planes that are part of blending chain for OPP output 161 * 162 * Parameters: 163 * [in/out] mpc - MPC context. 164 * [in/out] tree - MPC tree structure that plane will be added to. 165 * [in] blnd_cfg - MPCC blending configuration for the new blending layer. 166 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. 167 * stereo mix must disable for the very bottom layer of the tree config. 168 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. 169 * [in] dpp_id - DPP instance for the plane to be added. 170 * [in] mpcc_id - The MPCC physical instance to use for blending. 171 * 172 * Return: struct mpcc* - MPCC that was added. 173 */ 174 struct mpcc *mpc1_insert_plane( 175 struct mpc *mpc, 176 struct mpc_tree *tree, 177 struct mpcc_blnd_cfg *blnd_cfg, 178 struct mpcc_sm_cfg *sm_cfg, 179 struct mpcc *insert_above_mpcc, 180 int dpp_id, 181 int mpcc_id) 182 { 183 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 184 struct mpcc *new_mpcc = NULL; 185 186 /* sanity check parameters */ 187 ASSERT(mpcc_id < mpc10->num_mpcc); 188 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); 189 190 if (insert_above_mpcc) { 191 /* check insert_above_mpcc exist in tree->opp_list */ 192 struct mpcc *temp_mpcc = tree->opp_list; 193 194 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) 195 temp_mpcc = temp_mpcc->mpcc_bot; 196 if (temp_mpcc == NULL) 197 return NULL; 198 } 199 200 /* Get and update MPCC struct parameters */ 201 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id); 202 new_mpcc->dpp_id = dpp_id; 203 204 /* program mux and MPCC_MODE */ 205 if (insert_above_mpcc) { 206 new_mpcc->mpcc_bot = insert_above_mpcc; 207 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); 208 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); 209 } else { 210 new_mpcc->mpcc_bot = NULL; 211 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 212 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); 213 } 214 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); 215 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); 216 217 /* update mpc tree mux setting */ 218 if (tree->opp_list == insert_above_mpcc) { 219 /* insert the toppest mpcc */ 220 tree->opp_list = new_mpcc; 221 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); 222 } else { 223 /* find insert position */ 224 struct mpcc *temp_mpcc = tree->opp_list; 225 226 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) 227 temp_mpcc = temp_mpcc->mpcc_bot; 228 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) { 229 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); 230 temp_mpcc->mpcc_bot = new_mpcc; 231 if (!insert_above_mpcc) 232 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], 233 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); 234 } 235 } 236 237 /* update the blending configuration */ 238 new_mpcc->blnd_cfg = *blnd_cfg; 239 mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id); 240 241 /* update the stereo mix settings, if provided */ 242 if (sm_cfg != NULL) { 243 new_mpcc->sm_cfg = *sm_cfg; 244 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id); 245 } 246 247 /* mark this mpcc as in use */ 248 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 249 250 return new_mpcc; 251 } 252 253 /* 254 * Remove a specified MPCC from the MPC tree. 255 * 256 * Parameters: 257 * [in/out] mpc - MPC context. 258 * [in/out] tree - MPC tree structure that plane will be removed from. 259 * [in/out] mpcc - MPCC to be removed from tree. 260 * 261 * Return: void 262 */ 263 void mpc1_remove_mpcc( 264 struct mpc *mpc, 265 struct mpc_tree *tree, 266 struct mpcc *mpcc_to_remove) 267 { 268 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 269 bool found = false; 270 int mpcc_id = mpcc_to_remove->mpcc_id; 271 272 if (tree->opp_list == mpcc_to_remove) { 273 found = true; 274 /* remove MPCC from top of tree */ 275 if (mpcc_to_remove->mpcc_bot) { 276 /* set the next MPCC in list to be the top MPCC */ 277 tree->opp_list = mpcc_to_remove->mpcc_bot; 278 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); 279 } else { 280 /* there are no other MPCC is list */ 281 tree->opp_list = NULL; 282 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); 283 } 284 } else { 285 /* find mpcc to remove MPCC list */ 286 struct mpcc *temp_mpcc = tree->opp_list; 287 288 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove) 289 temp_mpcc = temp_mpcc->mpcc_bot; 290 291 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) { 292 found = true; 293 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot; 294 if (mpcc_to_remove->mpcc_bot) { 295 /* remove MPCC in middle of list */ 296 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, 297 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id); 298 } else { 299 /* remove MPCC from bottom of list */ 300 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, 301 MPCC_BOT_SEL, 0xf); 302 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], 303 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH); 304 } 305 } 306 } 307 308 if (found) { 309 /* turn off MPCC mux registers */ 310 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 311 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 312 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 313 314 /* mark this mpcc as not in use */ 315 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); 316 mpcc_to_remove->dpp_id = 0xf; 317 mpcc_to_remove->mpcc_bot = NULL; 318 } else { 319 /* In case of resume from S3/S4, remove mpcc from bios left over */ 320 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 321 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 322 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 323 } 324 } 325 326 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) 327 { 328 mpcc->mpcc_id = mpcc_inst; 329 mpcc->dpp_id = 0xf; 330 mpcc->mpcc_bot = NULL; 331 mpcc->blnd_cfg.overlap_only = false; 332 mpcc->blnd_cfg.global_alpha = 0xff; 333 mpcc->blnd_cfg.global_gain = 0xff; 334 mpcc->sm_cfg.enable = false; 335 } 336 337 /* 338 * Reset the MPCC HW status by disconnecting all muxes. 339 * 340 * Parameters: 341 * [in/out] mpc - MPC context. 342 * 343 * Return: void 344 */ 345 void mpc1_mpc_init(struct mpc *mpc) 346 { 347 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 348 int mpcc_id; 349 int opp_id; 350 351 mpc10->mpcc_in_use_mask = 0; 352 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { 353 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); 354 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); 355 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); 356 357 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id); 358 } 359 360 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { 361 if (REG(MUX[opp_id])) 362 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); 363 } 364 } 365 366 void mpc1_init_mpcc_list_from_hw( 367 struct mpc *mpc, 368 struct mpc_tree *tree) 369 { 370 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 371 unsigned int opp_id; 372 unsigned int top_sel; 373 unsigned int bot_sel; 374 unsigned int out_mux; 375 struct mpcc *mpcc; 376 int mpcc_id; 377 int bot_mpcc_id; 378 379 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); 380 381 if (out_mux != 0xf) { 382 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) { 383 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 384 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); 385 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); 386 387 if (bot_sel == mpcc_id) 388 bot_sel = 0xf; 389 390 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { 391 mpcc = mpc1_get_mpcc(mpc, mpcc_id); 392 mpcc->dpp_id = top_sel; 393 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 394 395 if (out_mux == mpcc_id) 396 tree->opp_list = mpcc; 397 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) { 398 bot_mpcc_id = bot_sel; 399 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); 400 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); 401 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { 402 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id); 403 404 mpcc->mpcc_bot = mpcc_bottom; 405 } 406 } 407 } 408 } 409 } 410 } 411 412 const struct mpc_funcs dcn10_mpc_funcs = { 413 .insert_plane = mpc1_insert_plane, 414 .remove_mpcc = mpc1_remove_mpcc, 415 .mpc_init = mpc1_mpc_init, 416 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, 417 .wait_for_idle = mpc1_assert_idle_mpcc, 418 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect, 419 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, 420 .update_blending = mpc1_update_blending, 421 }; 422 423 void dcn10_mpc_construct(struct dcn10_mpc *mpc10, 424 struct dc_context *ctx, 425 const struct dcn_mpc_registers *mpc_regs, 426 const struct dcn_mpc_shift *mpc_shift, 427 const struct dcn_mpc_mask *mpc_mask, 428 int num_mpcc) 429 { 430 int i; 431 432 mpc10->base.ctx = ctx; 433 434 mpc10->base.funcs = &dcn10_mpc_funcs; 435 436 mpc10->mpc_regs = mpc_regs; 437 mpc10->mpc_shift = mpc_shift; 438 mpc10->mpc_mask = mpc_mask; 439 440 mpc10->mpcc_in_use_mask = 0; 441 mpc10->num_mpcc = num_mpcc; 442 443 for (i = 0; i < MAX_MPCC; i++) 444 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i); 445 } 446 447