1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn10_mpc.h" 28 #include "dc.h" 29 #include "mem_input.h" 30 31 #define REG(reg)\ 32 mpc10->mpc_regs->reg 33 34 #define CTX \ 35 mpc10->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name 40 41 #define MODE_TOP_ONLY 1 42 #define MODE_BLEND 3 43 #define BLND_PP_ALPHA 0 44 #define BLND_GLOBAL_ALPHA 2 45 46 47 static void mpc10_set_bg_color( 48 struct dcn10_mpc *mpc10, 49 struct tg_color *bg_color, 50 int id) 51 { 52 /* mpc color is 12 bit. tg_color is 10 bit */ 53 /* todo: might want to use 16 bit to represent color and have each 54 * hw block translate to correct color depth. 55 */ 56 uint32_t bg_r_cr = bg_color->color_r_cr << 2; 57 uint32_t bg_g_y = bg_color->color_g_y << 2; 58 uint32_t bg_b_cb = bg_color->color_b_cb << 2; 59 60 REG_SET(MPCC_BG_R_CR[id], 0, 61 MPCC_BG_R_CR, bg_r_cr); 62 REG_SET(MPCC_BG_G_Y[id], 0, 63 MPCC_BG_G_Y, bg_g_y); 64 REG_SET(MPCC_BG_B_CB[id], 0, 65 MPCC_BG_B_CB, bg_b_cb); 66 } 67 68 static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) 69 { 70 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 71 72 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); 73 REG_WAIT(MPCC_STATUS[id], 74 MPCC_IDLE, 1, 75 1, 100000); 76 } 77 78 static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10) 79 { 80 int i; 81 int last_free_mpcc_id = -1; 82 83 for (i = 0; i < mpc10->num_mpcc; i++) { 84 uint32_t is_idle = 0; 85 86 if (mpc10->mpcc_in_use_mask & 1 << i) 87 continue; 88 89 last_free_mpcc_id = i; 90 REG_GET(MPCC_STATUS[i], MPCC_IDLE, &is_idle); 91 if (is_idle) 92 return i; 93 } 94 95 /* This assert should never trigger, we have mpcc leak if it does */ 96 ASSERT(last_free_mpcc_id != -1); 97 98 mpc10_assert_idle_mpcc(&mpc10->base, last_free_mpcc_id); 99 return last_free_mpcc_id; 100 } 101 102 static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int id) 103 { 104 unsigned int top_sel, mpc_busy, mpc_idle; 105 106 REG_GET(MPCC_TOP_SEL[id], 107 MPCC_TOP_SEL, &top_sel); 108 109 if (top_sel == 0xf) { 110 REG_GET_2(MPCC_STATUS[id], 111 MPCC_BUSY, &mpc_busy, 112 MPCC_IDLE, &mpc_idle); 113 114 ASSERT(mpc_busy == 0); 115 ASSERT(mpc_idle == 1); 116 } 117 } 118 119 static void mpc10_mpcc_remove( 120 struct mpc *mpc, 121 struct output_pixel_processor *opp, 122 int dpp_id) 123 { 124 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 125 int mpcc_id, z_idx; 126 127 for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) 128 if (opp->mpc_tree.dpp[z_idx] == dpp_id) 129 break; 130 131 if (z_idx == opp->mpc_tree.num_pipes) { 132 /* In case of resume from S3/S4, remove mpcc from bios left over */ 133 REG_SET(MPCC_OPP_ID[dpp_id], 0, 134 MPCC_OPP_ID, 0xf); 135 REG_SET(MPCC_TOP_SEL[dpp_id], 0, 136 MPCC_TOP_SEL, 0xf); 137 REG_SET(MPCC_BOT_SEL[dpp_id], 0, 138 MPCC_BOT_SEL, 0xf); 139 return; 140 } 141 142 mpcc_id = opp->mpc_tree.mpcc[z_idx]; 143 144 REG_SET(MPCC_OPP_ID[mpcc_id], 0, 145 MPCC_OPP_ID, 0xf); 146 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, 147 MPCC_TOP_SEL, 0xf); 148 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, 149 MPCC_BOT_SEL, 0xf); 150 151 if (z_idx > 0) { 152 int top_mpcc_id = opp->mpc_tree.mpcc[z_idx - 1]; 153 154 if (z_idx + 1 < opp->mpc_tree.num_pipes) 155 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 156 MPCC_BOT_SEL, opp->mpc_tree.mpcc[z_idx + 1]); 157 else { 158 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 159 MPCC_BOT_SEL, 0xf); 160 REG_UPDATE(MPCC_CONTROL[top_mpcc_id], 161 MPCC_MODE, MODE_TOP_ONLY); 162 } 163 } else if (opp->mpc_tree.num_pipes > 1) 164 REG_SET(MUX[opp->inst], 0, 165 MPC_OUT_MUX, opp->mpc_tree.mpcc[z_idx + 1]); 166 else 167 REG_SET(MUX[opp->inst], 0, MPC_OUT_MUX, 0xf); 168 169 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id); 170 opp->mpc_tree.num_pipes--; 171 for (; z_idx < opp->mpc_tree.num_pipes; z_idx++) { 172 opp->mpc_tree.dpp[z_idx] = opp->mpc_tree.dpp[z_idx + 1]; 173 opp->mpc_tree.mpcc[z_idx] = opp->mpc_tree.mpcc[z_idx + 1]; 174 } 175 opp->mpc_tree.dpp[opp->mpc_tree.num_pipes] = 0xdeadbeef; 176 opp->mpc_tree.mpcc[opp->mpc_tree.num_pipes] = 0xdeadbeef; 177 } 178 179 static void mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg) 180 { 181 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); 182 int alpha_blnd_mode = cfg->per_pixel_alpha ? 183 BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; 184 int mpcc_mode = MODE_TOP_ONLY; 185 int mpcc_id, z_idx; 186 187 ASSERT(cfg->z_index < mpc10->num_mpcc); 188 189 for (z_idx = 0; z_idx < cfg->opp->mpc_tree.num_pipes; z_idx++) 190 if (cfg->opp->mpc_tree.dpp[z_idx] == cfg->mi->inst) 191 break; 192 if (z_idx == cfg->opp->mpc_tree.num_pipes) { 193 ASSERT(cfg->z_index <= cfg->opp->mpc_tree.num_pipes); 194 mpcc_id = mpc10_get_idle_mpcc_id(mpc10); 195 /*todo: remove hack*/ 196 mpcc_id = cfg->mi->inst; 197 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); 198 199 if (mpc->ctx->dc->debug.sanity_checks) 200 mpc10_assert_mpcc_idle_before_connect(mpc10, mpcc_id); 201 } else { 202 ASSERT(cfg->z_index < cfg->opp->mpc_tree.num_pipes); 203 mpcc_id = cfg->opp->mpc_tree.mpcc[z_idx]; 204 mpc10_mpcc_remove(mpc, cfg->opp, cfg->mi->inst); 205 } 206 207 REG_SET(MPCC_OPP_ID[mpcc_id], 0, 208 MPCC_OPP_ID, cfg->opp->inst); 209 210 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, 211 MPCC_TOP_SEL, cfg->mi->inst); 212 213 if (cfg->z_index > 0) { 214 int top_mpcc_id = cfg->opp->mpc_tree.mpcc[cfg->z_index - 1]; 215 216 REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0, 217 MPCC_BOT_SEL, mpcc_id); 218 REG_UPDATE(MPCC_CONTROL[top_mpcc_id], 219 MPCC_MODE, MODE_BLEND); 220 } else 221 REG_SET(MUX[cfg->opp->inst], 0, MPC_OUT_MUX, mpcc_id); 222 223 if (cfg->z_index < cfg->opp->mpc_tree.num_pipes) { 224 int bot_mpcc_id = cfg->opp->mpc_tree.mpcc[cfg->z_index]; 225 226 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, 227 MPCC_BOT_SEL, bot_mpcc_id); 228 mpcc_mode = MODE_BLEND; 229 } 230 231 REG_SET_4(MPCC_CONTROL[mpcc_id], 0xffffffff, 232 MPCC_MODE, mpcc_mode, 233 MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, 234 MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha, 235 MPCC_BLND_ACTIVE_OVERLAP_ONLY, false); 236 237 mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id); 238 239 mpc10->mpcc_in_use_mask |= 1 << mpcc_id; 240 for (z_idx = cfg->opp->mpc_tree.num_pipes; z_idx > cfg->z_index; z_idx--) { 241 cfg->opp->mpc_tree.dpp[z_idx] = cfg->opp->mpc_tree.dpp[z_idx - 1]; 242 cfg->opp->mpc_tree.mpcc[z_idx] = cfg->opp->mpc_tree.mpcc[z_idx - 1]; 243 } 244 cfg->opp->mpc_tree.dpp[cfg->z_index] = cfg->mi->inst; 245 cfg->opp->mpc_tree.mpcc[cfg->z_index] = mpcc_id; 246 cfg->opp->mpc_tree.num_pipes++; 247 cfg->mi->opp_id = cfg->opp->inst; 248 cfg->mi->mpcc_id = mpcc_id; 249 } 250 251 const struct mpc_funcs dcn10_mpc_funcs = { 252 .add = mpc10_mpcc_add, 253 .remove = mpc10_mpcc_remove, 254 .wait_for_idle = mpc10_assert_idle_mpcc 255 }; 256 257 void dcn10_mpc_construct(struct dcn10_mpc *mpc10, 258 struct dc_context *ctx, 259 const struct dcn_mpc_registers *mpc_regs, 260 const struct dcn_mpc_shift *mpc_shift, 261 const struct dcn_mpc_mask *mpc_mask, 262 int num_mpcc) 263 { 264 mpc10->base.ctx = ctx; 265 266 mpc10->base.funcs = &dcn10_mpc_funcs; 267 268 mpc10->mpc_regs = mpc_regs; 269 mpc10->mpc_shift = mpc_shift; 270 mpc10->mpc_mask = mpc_mask; 271 272 mpc10->mpcc_in_use_mask = 0; 273 mpc10->num_mpcc = num_mpcc; 274 } 275