1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_ENCODER__DCN10_H__ 27 #define __DC_LINK_ENCODER__DCN10_H__ 28 29 #include "link_encoder.h" 30 31 #define TO_DCN10_LINK_ENC(link_encoder)\ 32 container_of(link_encoder, struct dcn10_link_encoder, base) 33 34 #define AUX_REG_LIST(id)\ 35 SRI(AUX_CONTROL, DP_AUX, id), \ 36 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ 37 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id) 38 39 #define HPD_REG_LIST(id)\ 40 SRI(DC_HPD_CONTROL, HPD, id) 41 42 #define LE_DCN_COMMON_REG_LIST(id) \ 43 SRI(DIG_BE_CNTL, DIG, id), \ 44 SRI(DIG_BE_EN_CNTL, DIG, id), \ 45 SRI(DIG_CLOCK_PATTERN, DIG, id), \ 46 SRI(TMDS_CTL_BITS, DIG, id), \ 47 SRI(DP_CONFIG, DP, id), \ 48 SRI(DP_DPHY_CNTL, DP, id), \ 49 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 50 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 51 SRI(DP_DPHY_SYM0, DP, id), \ 52 SRI(DP_DPHY_SYM1, DP, id), \ 53 SRI(DP_DPHY_SYM2, DP, id), \ 54 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 55 SRI(DP_LINK_CNTL, DP, id), \ 56 SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 57 SRI(DP_MSE_SAT0, DP, id), \ 58 SRI(DP_MSE_SAT1, DP, id), \ 59 SRI(DP_MSE_SAT2, DP, id), \ 60 SRI(DP_MSE_SAT_UPDATE, DP, id), \ 61 SRI(DP_SEC_CNTL, DP, id), \ 62 SRI(DP_VID_STREAM_CNTL, DP, id), \ 63 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 64 SRI(DP_SEC_CNTL1, DP, id), \ 65 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 66 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 67 68 69 #define LE_DCN10_REG_LIST(id)\ 70 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 71 LE_DCN_COMMON_REG_LIST(id) 72 73 struct dcn10_link_enc_aux_registers { 74 uint32_t AUX_CONTROL; 75 uint32_t AUX_DPHY_RX_CONTROL0; 76 uint32_t AUX_DPHY_TX_CONTROL; 77 uint32_t AUX_DPHY_RX_CONTROL1; 78 }; 79 80 struct dcn10_link_enc_hpd_registers { 81 uint32_t DC_HPD_CONTROL; 82 }; 83 84 struct dcn10_link_enc_registers { 85 uint32_t DIG_BE_CNTL; 86 uint32_t DIG_BE_EN_CNTL; 87 uint32_t DIG_CLOCK_PATTERN; 88 uint32_t DP_CONFIG; 89 uint32_t DP_DPHY_CNTL; 90 uint32_t DP_DPHY_INTERNAL_CTRL; 91 uint32_t DP_DPHY_PRBS_CNTL; 92 uint32_t DP_DPHY_SCRAM_CNTL; 93 uint32_t DP_DPHY_SYM0; 94 uint32_t DP_DPHY_SYM1; 95 uint32_t DP_DPHY_SYM2; 96 uint32_t DP_DPHY_TRAINING_PATTERN_SEL; 97 uint32_t DP_LINK_CNTL; 98 uint32_t DP_LINK_FRAMING_CNTL; 99 uint32_t DP_MSE_SAT0; 100 uint32_t DP_MSE_SAT1; 101 uint32_t DP_MSE_SAT2; 102 uint32_t DP_MSE_SAT_UPDATE; 103 uint32_t DP_SEC_CNTL; 104 uint32_t DP_VID_STREAM_CNTL; 105 uint32_t DP_DPHY_FAST_TRAINING; 106 uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 107 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 108 uint32_t DP_SEC_CNTL1; 109 uint32_t TMDS_CTL_BITS; 110 /* DCCG */ 111 uint32_t CLOCK_ENABLE; 112 /* DIG */ 113 uint32_t DIG_LANE_ENABLE; 114 /* UNIPHY */ 115 uint32_t CHANNEL_XBAR_CNTL; 116 /* DPCS */ 117 uint32_t RDPCSTX_PHY_CNTL3; 118 uint32_t RDPCSTX_PHY_CNTL4; 119 uint32_t RDPCSTX_PHY_CNTL5; 120 uint32_t RDPCSTX_PHY_CNTL6; 121 uint32_t RDPCSTX_PHY_CNTL7; 122 uint32_t RDPCSTX_PHY_CNTL8; 123 uint32_t RDPCSTX_PHY_CNTL9; 124 uint32_t RDPCSTX_PHY_CNTL10; 125 uint32_t RDPCSTX_PHY_CNTL11; 126 uint32_t RDPCSTX_PHY_CNTL12; 127 uint32_t RDPCSTX_PHY_CNTL13; 128 uint32_t RDPCSTX_PHY_CNTL14; 129 uint32_t RDPCSTX_PHY_CNTL15; 130 uint32_t RDPCSTX_CNTL; 131 uint32_t RDPCSTX_CLOCK_CNTL; 132 uint32_t RDPCSTX_PHY_CNTL0; 133 uint32_t RDPCSTX_PHY_CNTL2; 134 uint32_t RDPCSTX_PLL_UPDATE_DATA; 135 uint32_t RDPCS_TX_CR_ADDR; 136 uint32_t RDPCS_TX_CR_DATA; 137 uint32_t DPCSTX_TX_CLOCK_CNTL; 138 uint32_t DPCSTX_TX_CNTL; 139 uint32_t RDPCSTX_INTERRUPT_CONTROL; 140 uint32_t RDPCSTX_PHY_FUSE0; 141 uint32_t RDPCSTX_PHY_FUSE1; 142 uint32_t RDPCSTX_PHY_FUSE2; 143 uint32_t RDPCSTX_PHY_FUSE3; 144 uint32_t RDPCSTX_PHY_RX_LD_VAL; 145 uint32_t DPCSTX_DEBUG_CONFIG; 146 uint32_t RDPCSTX_DEBUG_CONFIG; 147 uint32_t RDPCSTX0_RDPCSTX_SCRATCH; 148 uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG; 149 uint32_t DCIO_SOFT_RESET; 150 /* indirect registers */ 151 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2; 152 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3; 153 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2; 154 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3; 155 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2; 156 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3; 157 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2; 158 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3; 159 uint32_t TMDS_DCBALANCER_CONTROL; 160 uint32_t PHYA_LINK_CNTL2; 161 uint32_t PHYB_LINK_CNTL2; 162 uint32_t PHYC_LINK_CNTL2; 163 }; 164 165 #define LE_SF(reg_name, field_name, post_fix)\ 166 .field_name = reg_name ## __ ## field_name ## post_fix 167 168 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\ 169 LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\ 170 LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ 171 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ 172 LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ 173 LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ 174 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ 175 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ 176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ 177 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ 178 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ 179 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ 180 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ 181 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ 182 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ 183 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ 184 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ 185 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ 186 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ 187 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ 188 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ 189 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ 190 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ 191 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ 192 LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ 193 LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ 194 LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ 195 LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ 196 LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ 197 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ 198 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ 199 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ 200 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ 201 LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ 202 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ 203 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ 204 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ 205 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ 206 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ 207 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ 208 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ 209 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ 210 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ 211 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ 212 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ 213 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ 214 LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ 215 LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ 216 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ 217 LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh) 218 219 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \ 220 type DIG_ENABLE;\ 221 type DIG_HPD_SELECT;\ 222 type DIG_MODE;\ 223 type DIG_FE_SOURCE_SELECT;\ 224 type DIG_CLOCK_PATTERN;\ 225 type DPHY_BYPASS;\ 226 type DPHY_ATEST_SEL_LANE0;\ 227 type DPHY_ATEST_SEL_LANE1;\ 228 type DPHY_ATEST_SEL_LANE2;\ 229 type DPHY_ATEST_SEL_LANE3;\ 230 type DPHY_PRBS_EN;\ 231 type DPHY_PRBS_SEL;\ 232 type DPHY_SYM1;\ 233 type DPHY_SYM2;\ 234 type DPHY_SYM3;\ 235 type DPHY_SYM4;\ 236 type DPHY_SYM5;\ 237 type DPHY_SYM6;\ 238 type DPHY_SYM7;\ 239 type DPHY_SYM8;\ 240 type DPHY_SCRAMBLER_BS_COUNT;\ 241 type DPHY_SCRAMBLER_ADVANCE;\ 242 type DPHY_RX_FAST_TRAINING_CAPABLE;\ 243 type DPHY_LOAD_BS_COUNT;\ 244 type DPHY_TRAINING_PATTERN_SEL;\ 245 type DP_DPHY_HBR2_PATTERN_CONTROL;\ 246 type DP_LINK_TRAINING_COMPLETE;\ 247 type DP_IDLE_BS_INTERVAL;\ 248 type DP_VBID_DISABLE;\ 249 type DP_VID_ENHANCED_FRAME_MODE;\ 250 type DP_VID_STREAM_ENABLE;\ 251 type DP_UDI_LANES;\ 252 type DP_SEC_GSP0_LINE_NUM;\ 253 type DP_SEC_GSP0_PRIORITY;\ 254 type DP_MSE_SAT_SRC0;\ 255 type DP_MSE_SAT_SRC1;\ 256 type DP_MSE_SAT_SRC2;\ 257 type DP_MSE_SAT_SRC3;\ 258 type DP_MSE_SAT_SLOT_COUNT0;\ 259 type DP_MSE_SAT_SLOT_COUNT1;\ 260 type DP_MSE_SAT_SLOT_COUNT2;\ 261 type DP_MSE_SAT_SLOT_COUNT3;\ 262 type DP_MSE_SAT_UPDATE;\ 263 type DP_MSE_16_MTP_KEEPOUT;\ 264 type DC_HPD_EN;\ 265 type TMDS_CTL0;\ 266 type AUX_HPD_SEL;\ 267 type AUX_LS_READ_EN;\ 268 type AUX_RX_RECEIVE_WINDOW 269 270 271 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \ 272 type RDPCS_PHY_DP_TX0_DATA_EN;\ 273 type RDPCS_PHY_DP_TX1_DATA_EN;\ 274 type RDPCS_PHY_DP_TX2_DATA_EN;\ 275 type RDPCS_PHY_DP_TX3_DATA_EN;\ 276 type RDPCS_PHY_DP_TX0_PSTATE;\ 277 type RDPCS_PHY_DP_TX1_PSTATE;\ 278 type RDPCS_PHY_DP_TX2_PSTATE;\ 279 type RDPCS_PHY_DP_TX3_PSTATE;\ 280 type RDPCS_PHY_DP_TX0_MPLL_EN;\ 281 type RDPCS_PHY_DP_TX1_MPLL_EN;\ 282 type RDPCS_PHY_DP_TX2_MPLL_EN;\ 283 type RDPCS_PHY_DP_TX3_MPLL_EN;\ 284 type RDPCS_TX_FIFO_LANE0_EN;\ 285 type RDPCS_TX_FIFO_LANE1_EN;\ 286 type RDPCS_TX_FIFO_LANE2_EN;\ 287 type RDPCS_TX_FIFO_LANE3_EN;\ 288 type RDPCS_EXT_REFCLK_EN;\ 289 type RDPCS_TX_FIFO_EN;\ 290 type UNIPHY_LINK_ENABLE;\ 291 type UNIPHY_CHANNEL0_XBAR_SOURCE;\ 292 type UNIPHY_CHANNEL1_XBAR_SOURCE;\ 293 type UNIPHY_CHANNEL2_XBAR_SOURCE;\ 294 type UNIPHY_CHANNEL3_XBAR_SOURCE;\ 295 type UNIPHY_CHANNEL0_INVERT;\ 296 type UNIPHY_CHANNEL1_INVERT;\ 297 type UNIPHY_CHANNEL2_INVERT;\ 298 type UNIPHY_CHANNEL3_INVERT;\ 299 type UNIPHY_LINK_ENABLE_HPD_MASK;\ 300 type UNIPHY_LANE_STAGGER_DELAY;\ 301 type RDPCS_SRAMCLK_BYPASS;\ 302 type RDPCS_SRAMCLK_EN;\ 303 type RDPCS_SRAMCLK_CLOCK_ON;\ 304 type DPCS_TX_FIFO_EN;\ 305 type RDPCS_PHY_DP_TX0_DISABLE;\ 306 type RDPCS_PHY_DP_TX1_DISABLE;\ 307 type RDPCS_PHY_DP_TX2_DISABLE;\ 308 type RDPCS_PHY_DP_TX3_DISABLE;\ 309 type RDPCS_PHY_DP_TX0_CLK_RDY;\ 310 type RDPCS_PHY_DP_TX1_CLK_RDY;\ 311 type RDPCS_PHY_DP_TX2_CLK_RDY;\ 312 type RDPCS_PHY_DP_TX3_CLK_RDY;\ 313 type RDPCS_PHY_DP_TX0_REQ;\ 314 type RDPCS_PHY_DP_TX1_REQ;\ 315 type RDPCS_PHY_DP_TX2_REQ;\ 316 type RDPCS_PHY_DP_TX3_REQ;\ 317 type RDPCS_PHY_DP_TX0_ACK;\ 318 type RDPCS_PHY_DP_TX1_ACK;\ 319 type RDPCS_PHY_DP_TX2_ACK;\ 320 type RDPCS_PHY_DP_TX3_ACK;\ 321 type RDPCS_PHY_DP_TX0_RESET;\ 322 type RDPCS_PHY_DP_TX1_RESET;\ 323 type RDPCS_PHY_DP_TX2_RESET;\ 324 type RDPCS_PHY_DP_TX3_RESET;\ 325 type RDPCS_PHY_RESET;\ 326 type RDPCS_PHY_CR_MUX_SEL;\ 327 type RDPCS_PHY_REF_RANGE;\ 328 type RDPCS_PHY_DP4_POR;\ 329 type RDPCS_SRAM_BYPASS;\ 330 type RDPCS_SRAM_EXT_LD_DONE;\ 331 type RDPCS_PHY_DP_TX0_TERM_CTRL;\ 332 type RDPCS_PHY_DP_TX1_TERM_CTRL;\ 333 type RDPCS_PHY_DP_TX2_TERM_CTRL;\ 334 type RDPCS_PHY_DP_TX3_TERM_CTRL;\ 335 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\ 336 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\ 337 type RDPCS_PHY_DP_MPLLB_SSC_EN;\ 338 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\ 339 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\ 340 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\ 341 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\ 342 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\ 343 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\ 344 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\ 345 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\ 346 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\ 347 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\ 348 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\ 349 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\ 350 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\ 351 type RDPCS_PHY_TX_VBOOST_LVL;\ 352 type RDPCS_PHY_HDMIMODE_ENABLE;\ 353 type RDPCS_PHY_DP_REF_CLK_EN;\ 354 type RDPCS_PLL_UPDATE_DATA;\ 355 type RDPCS_SRAM_INIT_DONE;\ 356 type RDPCS_TX_CR_ADDR;\ 357 type RDPCS_TX_CR_DATA;\ 358 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\ 359 type RDPCS_PHY_DP_MPLLB_STATE;\ 360 type RDPCS_PHY_DP_TX0_WIDTH;\ 361 type RDPCS_PHY_DP_TX0_RATE;\ 362 type RDPCS_PHY_DP_TX1_WIDTH;\ 363 type RDPCS_PHY_DP_TX1_RATE;\ 364 type RDPCS_PHY_DP_TX2_WIDTH;\ 365 type RDPCS_PHY_DP_TX2_RATE;\ 366 type RDPCS_PHY_DP_TX3_WIDTH;\ 367 type RDPCS_PHY_DP_TX3_RATE;\ 368 type DPCS_SYMCLK_CLOCK_ON;\ 369 type DPCS_SYMCLK_GATE_DIS;\ 370 type DPCS_SYMCLK_EN;\ 371 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\ 372 type RDPCS_SYMCLK_DIV2_GATE_DIS;\ 373 type RDPCS_SYMCLK_DIV2_EN;\ 374 type DPCS_TX_DATA_SWAP;\ 375 type DPCS_TX_DATA_ORDER_INVERT;\ 376 type DPCS_TX_FIFO_RD_START_DELAY;\ 377 type RDPCS_TX_FIFO_RD_START_DELAY;\ 378 type RDPCS_REG_FIFO_ERROR_MASK;\ 379 type RDPCS_TX_FIFO_ERROR_MASK;\ 380 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\ 381 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\ 382 type RDPCS_PHY_DPALT_DP4;\ 383 type RDPCS_PHY_DPALT_DISABLE;\ 384 type RDPCS_PHY_DPALT_DISABLE_ACK;\ 385 type RDPCS_PHY_DP_MPLLB_V2I;\ 386 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\ 387 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\ 388 type RDPCS_PHY_RX_VREF_CTRL;\ 389 type RDPCS_PHY_DP_MPLLB_CP_INT;\ 390 type RDPCS_PHY_DP_MPLLB_CP_PROP;\ 391 type RDPCS_PHY_RX_REF_LD_VAL;\ 392 type RDPCS_PHY_RX_VCO_LD_VAL;\ 393 type DPCSTX_DEBUG_CONFIG; \ 394 type RDPCSTX_DEBUG_CONFIG; \ 395 type RDPCS_PHY_DP_TX0_EQ_MAIN;\ 396 type RDPCS_PHY_DP_TX0_EQ_PRE;\ 397 type RDPCS_PHY_DP_TX0_EQ_POST;\ 398 type RDPCS_PHY_DP_TX1_EQ_MAIN;\ 399 type RDPCS_PHY_DP_TX1_EQ_PRE;\ 400 type RDPCS_PHY_DP_TX1_EQ_POST;\ 401 type RDPCS_PHY_DP_TX2_EQ_MAIN;\ 402 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\ 403 type RDPCS_PHY_DP_TX2_EQ_PRE;\ 404 type RDPCS_PHY_DP_TX2_EQ_POST;\ 405 type RDPCS_PHY_DP_TX3_EQ_MAIN;\ 406 type RDPCS_PHY_DCO_RANGE;\ 407 type RDPCS_PHY_DCO_FINETUNE;\ 408 type RDPCS_PHY_DP_TX3_EQ_PRE;\ 409 type RDPCS_PHY_DP_TX3_EQ_POST;\ 410 type RDPCS_PHY_SUP_PRE_HP;\ 411 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\ 412 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\ 413 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\ 414 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\ 415 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\ 416 type UNIPHYA_SOFT_RESET;\ 417 type UNIPHYB_SOFT_RESET;\ 418 type UNIPHYC_SOFT_RESET;\ 419 type UNIPHYD_SOFT_RESET;\ 420 type UNIPHYE_SOFT_RESET;\ 421 type UNIPHYF_SOFT_RESET 422 423 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \ 424 type DIG_LANE0EN;\ 425 type DIG_LANE1EN;\ 426 type DIG_LANE2EN;\ 427 type DIG_LANE3EN;\ 428 type DIG_CLK_EN;\ 429 type SYMCLKA_CLOCK_ENABLE;\ 430 type DPHY_FEC_EN;\ 431 type DPHY_FEC_READY_SHADOW;\ 432 type DPHY_FEC_ACTIVE_STATUS;\ 433 DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\ 434 type VCO_LD_VAL_OVRD;\ 435 type VCO_LD_VAL_OVRD_EN;\ 436 type REF_LD_VAL_OVRD;\ 437 type REF_LD_VAL_OVRD_EN;\ 438 type AUX_RX_START_WINDOW; \ 439 type AUX_RX_HALF_SYM_DETECT_LEN; \ 440 type AUX_RX_TRANSITION_FILTER_EN; \ 441 type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \ 442 type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \ 443 type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \ 444 type AUX_RX_PHASE_DETECT_LEN; \ 445 type AUX_RX_DETECTION_THRESHOLD; \ 446 type AUX_TX_PRECHARGE_LEN; \ 447 type AUX_TX_PRECHARGE_SYMBOLS; \ 448 type AUX_MODE_DET_CHECK_DELAY;\ 449 type DPCS_DBG_CBUS_DIS;\ 450 type AUX_RX_PRECHARGE_SKIP;\ 451 type AUX_RX_TIMEOUT_LEN;\ 452 type AUX_RX_TIMEOUT_LEN_MUL 453 454 #define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \ 455 type TMDS_SYNC_DCBAL_EN;\ 456 type PHY_HPO_DIG_SRC_SEL;\ 457 type PHY_HPO_ENC_SRC_SEL;\ 458 type DPCS_TX_HDMI_FRL_MODE;\ 459 type DPCS_TX_DATA_SWAP_10_BIT;\ 460 type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\ 461 type RDPCS_TX_CLK_EN 462 463 struct dcn10_link_enc_shift { 464 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 465 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 466 DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 467 }; 468 469 struct dcn10_link_enc_mask { 470 DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 471 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 472 DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 473 }; 474 475 struct dcn10_link_encoder { 476 struct link_encoder base; 477 const struct dcn10_link_enc_registers *link_regs; 478 const struct dcn10_link_enc_aux_registers *aux_regs; 479 const struct dcn10_link_enc_hpd_registers *hpd_regs; 480 const struct dcn10_link_enc_shift *link_shift; 481 const struct dcn10_link_enc_mask *link_mask; 482 }; 483 484 485 void dcn10_link_encoder_construct( 486 struct dcn10_link_encoder *enc10, 487 const struct encoder_init_data *init_data, 488 const struct encoder_feature_support *enc_features, 489 const struct dcn10_link_enc_registers *link_regs, 490 const struct dcn10_link_enc_aux_registers *aux_regs, 491 const struct dcn10_link_enc_hpd_registers *hpd_regs, 492 const struct dcn10_link_enc_shift *link_shift, 493 const struct dcn10_link_enc_mask *link_mask); 494 495 bool dcn10_link_encoder_validate_dvi_output( 496 const struct dcn10_link_encoder *enc10, 497 enum signal_type connector_signal, 498 enum signal_type signal, 499 const struct dc_crtc_timing *crtc_timing); 500 501 bool dcn10_link_encoder_validate_rgb_output( 502 const struct dcn10_link_encoder *enc10, 503 const struct dc_crtc_timing *crtc_timing); 504 505 bool dcn10_link_encoder_validate_dp_output( 506 const struct dcn10_link_encoder *enc10, 507 const struct dc_crtc_timing *crtc_timing); 508 509 bool dcn10_link_encoder_validate_wireless_output( 510 const struct dcn10_link_encoder *enc10, 511 const struct dc_crtc_timing *crtc_timing); 512 513 bool dcn10_link_encoder_validate_output_with_stream( 514 struct link_encoder *enc, 515 const struct dc_stream_state *stream); 516 517 /****************** HW programming ************************/ 518 519 /* initialize HW */ /* why do we initialze aux in here? */ 520 void dcn10_link_encoder_hw_init(struct link_encoder *enc); 521 522 void dcn10_link_encoder_destroy(struct link_encoder **enc); 523 524 /* program DIG_MODE in DIG_BE */ 525 /* TODO can this be combined with enable_output? */ 526 void dcn10_link_encoder_setup( 527 struct link_encoder *enc, 528 enum signal_type signal); 529 530 void enc1_configure_encoder( 531 struct dcn10_link_encoder *enc10, 532 const struct dc_link_settings *link_settings); 533 534 /* enables TMDS PHY output */ 535 /* TODO: still need depth or just pass in adjusted pixel clock? */ 536 void dcn10_link_encoder_enable_tmds_output( 537 struct link_encoder *enc, 538 enum clock_source_id clock_source, 539 enum dc_color_depth color_depth, 540 enum signal_type signal, 541 uint32_t pixel_clock); 542 543 void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( 544 struct link_encoder *enc, 545 enum clock_source_id clock_source, 546 enum dc_color_depth color_depth, 547 enum signal_type signal, 548 uint32_t pixel_clock); 549 550 /* enables DP PHY output */ 551 void dcn10_link_encoder_enable_dp_output( 552 struct link_encoder *enc, 553 const struct dc_link_settings *link_settings, 554 enum clock_source_id clock_source); 555 556 /* enables DP PHY output in MST mode */ 557 void dcn10_link_encoder_enable_dp_mst_output( 558 struct link_encoder *enc, 559 const struct dc_link_settings *link_settings, 560 enum clock_source_id clock_source); 561 562 /* disable PHY output */ 563 void dcn10_link_encoder_disable_output( 564 struct link_encoder *enc, 565 enum signal_type signal); 566 567 /* set DP lane settings */ 568 void dcn10_link_encoder_dp_set_lane_settings( 569 struct link_encoder *enc, 570 const struct link_training_settings *link_settings); 571 572 void dcn10_link_encoder_dp_set_phy_pattern( 573 struct link_encoder *enc, 574 const struct encoder_set_dp_phy_pattern_param *param); 575 576 /* programs DP MST VC payload allocation */ 577 void dcn10_link_encoder_update_mst_stream_allocation_table( 578 struct link_encoder *enc, 579 const struct link_mst_stream_allocation_table *table); 580 581 void dcn10_link_encoder_connect_dig_be_to_fe( 582 struct link_encoder *enc, 583 enum engine_id engine, 584 bool connect); 585 586 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( 587 struct link_encoder *enc, 588 uint32_t index); 589 590 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc); 591 592 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc); 593 594 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 595 bool exit_link_training_required); 596 597 void dcn10_psr_program_secondary_packet(struct link_encoder *enc, 598 unsigned int sdp_transmit_line_num_deadline); 599 600 bool dcn10_is_dig_enabled(struct link_encoder *enc); 601 602 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc); 603 604 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10); 605 606 enum signal_type dcn10_get_dig_mode( 607 struct link_encoder *enc); 608 609 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, 610 struct dc_link_settings *link_settings); 611 #endif /* __DC_LINK_ENCODER__DCN10_H__ */ 612