1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DCN10_IPP_H_ 27 #define _DCN10_IPP_H_ 28 29 #include "ipp.h" 30 31 #define TO_DCN10_IPP(ipp)\ 32 container_of(ipp, struct dcn10_ipp, base) 33 34 #define IPP_REG_LIST_DCN(id) \ 35 SRI(CM_ICSC_CONTROL, CM, id), \ 36 SRI(CM_ICSC_C11_C12, CM, id), \ 37 SRI(CM_ICSC_C13_C14, CM, id), \ 38 SRI(CM_ICSC_C21_C22, CM, id), \ 39 SRI(CM_ICSC_C23_C24, CM, id), \ 40 SRI(CM_ICSC_C31_C32, CM, id), \ 41 SRI(CM_ICSC_C33_C34, CM, id), \ 42 SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ 43 SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ 44 SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ 45 SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 46 SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 47 SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 48 SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ 49 SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ 50 SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ 51 SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ 52 SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ 53 SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ 54 SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ 55 SRI(CM_DGAM_RAMB_REGION_2_3, CM, id), \ 56 SRI(CM_DGAM_RAMB_REGION_4_5, CM, id), \ 57 SRI(CM_DGAM_RAMB_REGION_6_7, CM, id), \ 58 SRI(CM_DGAM_RAMB_REGION_8_9, CM, id), \ 59 SRI(CM_DGAM_RAMB_REGION_10_11, CM, id), \ 60 SRI(CM_DGAM_RAMB_REGION_12_13, CM, id), \ 61 SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ 62 SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ 63 SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ 64 SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ 65 SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ 66 SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ 67 SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ 68 SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ 69 SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ 70 SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ 71 SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ 72 SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ 73 SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ 74 SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ 75 SRI(CM_DGAM_RAMA_REGION_2_3, CM, id), \ 76 SRI(CM_DGAM_RAMA_REGION_4_5, CM, id), \ 77 SRI(CM_DGAM_RAMA_REGION_6_7, CM, id), \ 78 SRI(CM_DGAM_RAMA_REGION_8_9, CM, id), \ 79 SRI(CM_DGAM_RAMA_REGION_10_11, CM, id), \ 80 SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \ 81 SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ 82 SRI(CM_MEM_PWR_CTRL, CM, id), \ 83 SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ 84 SRI(CM_DGAM_LUT_INDEX, CM, id), \ 85 SRI(CM_DGAM_LUT_DATA, CM, id), \ 86 SRI(CM_CONTROL, CM, id), \ 87 SRI(CM_DGAM_CONTROL, CM, id), \ 88 SRI(FORMAT_CONTROL, CNVC_CFG, id), \ 89 SRI(DPP_CONTROL, DPP_TOP, id), \ 90 SRI(CURSOR_SETTINS, HUBPREQ, id), \ 91 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 92 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ 93 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ 94 SRI(CURSOR0_COLOR1, CNVC_CUR, id) 95 96 #define IPP_REG_LIST_DCN10(id) \ 97 IPP_REG_LIST_DCN(id), \ 98 SRI(CM_IGAM_CONTROL, CM, id), \ 99 SRI(CM_COMA_C11_C12, CM, id), \ 100 SRI(CM_COMA_C13_C14, CM, id), \ 101 SRI(CM_COMA_C21_C22, CM, id), \ 102 SRI(CM_COMA_C23_C24, CM, id), \ 103 SRI(CM_COMA_C31_C32, CM, id), \ 104 SRI(CM_COMA_C33_C34, CM, id), \ 105 SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ 106 SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ 107 SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ 108 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ 109 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ 110 SRI(CURSOR_SIZE, CURSOR, id), \ 111 SRI(CURSOR_CONTROL, CURSOR, id), \ 112 SRI(CURSOR_POSITION, CURSOR, id), \ 113 SRI(CURSOR_HOT_SPOT, CURSOR, id), \ 114 SRI(CURSOR_DST_OFFSET, CURSOR, id) 115 116 #define IPP_SF(reg_name, field_name, post_fix)\ 117 .field_name = reg_name ## __ ## field_name ## post_fix 118 119 #define IPP_MASK_SH_LIST_DCN(mask_sh) \ 120 IPP_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ 121 IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ 122 IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ 123 IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \ 124 IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \ 125 IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \ 126 IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \ 127 IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \ 128 IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \ 129 IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \ 130 IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \ 131 IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ 132 IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ 133 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ 134 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ 135 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ 136 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ 137 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ 138 IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ 139 IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 140 IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 141 IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 142 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ 143 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ 144 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ 145 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ 146 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ 147 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ 148 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ 149 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ 150 IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ 151 IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ 152 IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 153 IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ 154 IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 155 IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ 156 IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ 157 IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ 158 IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ 159 IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ 160 IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ 161 IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ 162 IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ 163 IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ 164 IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ 165 IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ 166 IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ 167 IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ 168 IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ 169 IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ 170 IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ 171 IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ 172 IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ 173 IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ 174 IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ 175 IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ 176 IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ 177 IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ 178 IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ 179 IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ 180 IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 181 IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ 182 IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 183 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ 184 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ 185 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ 186 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ 187 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ 188 IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ 189 IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 190 IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 191 IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 192 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ 193 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ 194 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ 195 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ 196 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ 197 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ 198 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ 199 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ 200 IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ 201 IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ 202 IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 203 IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ 204 IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 205 IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ 206 IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ 207 IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ 208 IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ 209 IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ 210 IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ 211 IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ 212 IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ 213 IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ 214 IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ 215 IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ 216 IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ 217 IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ 218 IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ 219 IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ 220 IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ 221 IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ 222 IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ 223 IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ 224 IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ 225 IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ 226 IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ 227 IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ 228 IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ 229 IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ 230 IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 231 IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ 232 IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 233 IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ 234 IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ 235 IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ 236 IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ 237 IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ 238 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ 239 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ 240 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ 241 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ 242 IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ 243 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ 244 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ 245 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ 246 IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ 247 IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ 248 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ 249 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh) 250 251 #define IPP_MASK_SH_LIST_DCN10(mask_sh) \ 252 IPP_MASK_SH_LIST_DCN(mask_sh),\ 253 IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \ 254 IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \ 255 IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \ 256 IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \ 257 IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \ 258 IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \ 259 IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \ 260 IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \ 261 IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \ 262 IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \ 263 IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \ 264 IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \ 265 IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ 266 IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ 267 IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ 268 IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ 269 IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ 270 IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ 271 IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ 272 IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ 273 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 274 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 275 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ 276 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ 277 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 278 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 279 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 280 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 281 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ 282 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 283 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 284 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 285 IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ 286 IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ 287 IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ 288 IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ 289 IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ 290 IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ 291 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh) 292 293 #define IPP_DCN10_REG_FIELD_LIST(type) \ 294 type CM_DGAM_CONFIG_STATUS; \ 295 type CM_ICSC_MODE; \ 296 type CM_ICSC_C11; \ 297 type CM_ICSC_C12; \ 298 type CM_ICSC_C13; \ 299 type CM_ICSC_C14; \ 300 type CM_ICSC_C21; \ 301 type CM_ICSC_C22; \ 302 type CM_ICSC_C23; \ 303 type CM_ICSC_C24; \ 304 type CM_ICSC_C31; \ 305 type CM_ICSC_C32; \ 306 type CM_ICSC_C33; \ 307 type CM_ICSC_C34; \ 308 type CM_COMA_C11; \ 309 type CM_COMA_C12; \ 310 type CM_COMA_C13; \ 311 type CM_COMA_C14; \ 312 type CM_COMA_C21; \ 313 type CM_COMA_C22; \ 314 type CM_COMA_C23; \ 315 type CM_COMA_C24; \ 316 type CM_COMA_C31; \ 317 type CM_COMA_C32; \ 318 type CM_COMA_C33; \ 319 type CM_COMA_C34; \ 320 type CM_DGAM_RAMB_EXP_REGION_START_B; \ 321 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 322 type CM_DGAM_RAMB_EXP_REGION_START_G; \ 323 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 324 type CM_DGAM_RAMB_EXP_REGION_START_R; \ 325 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 326 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 327 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 328 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 329 type CM_DGAM_RAMB_EXP_REGION_END_B; \ 330 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 331 type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \ 332 type CM_DGAM_RAMB_EXP_REGION_END_G; \ 333 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 334 type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \ 335 type CM_DGAM_RAMB_EXP_REGION_END_R; \ 336 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 337 type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \ 338 type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 339 type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 340 type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 341 type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 342 type CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ 343 type CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ 344 type CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ 345 type CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ 346 type CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ 347 type CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ 348 type CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ 349 type CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ 350 type CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ 351 type CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ 352 type CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ 353 type CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ 354 type CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ 355 type CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ 356 type CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ 357 type CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ 358 type CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ 359 type CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ 360 type CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ 361 type CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ 362 type CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ 363 type CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ 364 type CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ 365 type CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ 366 type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ 367 type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 368 type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ 369 type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 370 type CM_DGAM_RAMA_EXP_REGION_START_B; \ 371 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 372 type CM_DGAM_RAMA_EXP_REGION_START_G; \ 373 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 374 type CM_DGAM_RAMA_EXP_REGION_START_R; \ 375 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 376 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 377 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 378 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 379 type CM_DGAM_RAMA_EXP_REGION_END_B; \ 380 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 381 type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \ 382 type CM_DGAM_RAMA_EXP_REGION_END_G; \ 383 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 384 type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \ 385 type CM_DGAM_RAMA_EXP_REGION_END_R; \ 386 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 387 type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \ 388 type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 389 type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 390 type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 391 type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 392 type CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ 393 type CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 394 type CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ 395 type CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 396 type CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ 397 type CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 398 type CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ 399 type CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 400 type CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ 401 type CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 402 type CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ 403 type CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 404 type CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ 405 type CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 406 type CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ 407 type CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 408 type CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ 409 type CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 410 type CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ 411 type CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 412 type CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ 413 type CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 414 type CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ 415 type CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 416 type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 417 type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 418 type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 419 type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 420 type SHARED_MEM_PWR_DIS; \ 421 type CM_IGAM_LUT_FORMAT_R; \ 422 type CM_IGAM_LUT_FORMAT_G; \ 423 type CM_IGAM_LUT_FORMAT_B; \ 424 type CM_IGAM_LUT_HOST_EN; \ 425 type CM_IGAM_LUT_RW_INDEX; \ 426 type CM_IGAM_LUT_RW_MODE; \ 427 type CM_IGAM_LUT_WRITE_EN_MASK; \ 428 type CM_IGAM_LUT_SEL; \ 429 type CM_IGAM_LUT_SEQ_COLOR; \ 430 type CM_IGAM_DGAM_CONFIG_STATUS; \ 431 type CM_DGAM_LUT_WRITE_EN_MASK; \ 432 type CM_DGAM_LUT_WRITE_SEL; \ 433 type CM_DGAM_LUT_INDEX; \ 434 type CM_DGAM_LUT_DATA; \ 435 type CM_BYPASS_EN; \ 436 type CM_BYPASS; \ 437 type CNVC_SURFACE_PIXEL_FORMAT; \ 438 type CNVC_BYPASS; \ 439 type ALPHA_EN; \ 440 type FORMAT_EXPANSION_MODE; \ 441 type CM_DGAM_LUT_MODE; \ 442 type CM_IGAM_LUT_MODE; \ 443 type CURSOR0_DST_Y_OFFSET; \ 444 type CURSOR0_CHUNK_HDL_ADJUST; \ 445 type CUR0_MODE; \ 446 type CUR0_COLOR0; \ 447 type CUR0_COLOR1; \ 448 type CUR0_EXPANSION_MODE; \ 449 type CURSOR_SURFACE_ADDRESS_HIGH; \ 450 type CURSOR_SURFACE_ADDRESS; \ 451 type CURSOR_WIDTH; \ 452 type CURSOR_HEIGHT; \ 453 type CURSOR_MODE; \ 454 type CURSOR_PITCH; \ 455 type CURSOR_LINES_PER_CHUNK; \ 456 type CURSOR_ENABLE; \ 457 type CUR0_ENABLE; \ 458 type CURSOR_X_POSITION; \ 459 type CURSOR_Y_POSITION; \ 460 type CURSOR_HOT_SPOT_X; \ 461 type CURSOR_HOT_SPOT_Y; \ 462 type CURSOR_DST_X_OFFSET; \ 463 type CM_IGAM_INPUT_FORMAT; \ 464 type OUTPUT_FP 465 466 struct dcn10_ipp_shift { 467 IPP_DCN10_REG_FIELD_LIST(uint8_t); 468 }; 469 470 struct dcn10_ipp_mask { 471 IPP_DCN10_REG_FIELD_LIST(uint32_t); 472 }; 473 474 struct dcn10_ipp_registers { 475 uint32_t CM_ICSC_CONTROL; 476 uint32_t CM_ICSC_C11_C12; 477 uint32_t CM_ICSC_C13_C14; 478 uint32_t CM_ICSC_C21_C22; 479 uint32_t CM_ICSC_C23_C24; 480 uint32_t CM_ICSC_C31_C32; 481 uint32_t CM_ICSC_C33_C34; 482 uint32_t CM_COMA_C11_C12; 483 uint32_t CM_COMA_C13_C14; 484 uint32_t CM_COMA_C21_C22; 485 uint32_t CM_COMA_C23_C24; 486 uint32_t CM_COMA_C31_C32; 487 uint32_t CM_COMA_C33_C34; 488 uint32_t CM_DGAM_RAMB_START_CNTL_B; 489 uint32_t CM_DGAM_RAMB_START_CNTL_G; 490 uint32_t CM_DGAM_RAMB_START_CNTL_R; 491 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; 492 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; 493 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; 494 uint32_t CM_DGAM_RAMB_END_CNTL1_B; 495 uint32_t CM_DGAM_RAMB_END_CNTL2_B; 496 uint32_t CM_DGAM_RAMB_END_CNTL1_G; 497 uint32_t CM_DGAM_RAMB_END_CNTL2_G; 498 uint32_t CM_DGAM_RAMB_END_CNTL1_R; 499 uint32_t CM_DGAM_RAMB_END_CNTL2_R; 500 uint32_t CM_DGAM_RAMB_REGION_0_1; 501 uint32_t CM_DGAM_RAMB_REGION_2_3; 502 uint32_t CM_DGAM_RAMB_REGION_4_5; 503 uint32_t CM_DGAM_RAMB_REGION_6_7; 504 uint32_t CM_DGAM_RAMB_REGION_8_9; 505 uint32_t CM_DGAM_RAMB_REGION_10_11; 506 uint32_t CM_DGAM_RAMB_REGION_12_13; 507 uint32_t CM_DGAM_RAMB_REGION_14_15; 508 uint32_t CM_DGAM_RAMA_START_CNTL_B; 509 uint32_t CM_DGAM_RAMA_START_CNTL_G; 510 uint32_t CM_DGAM_RAMA_START_CNTL_R; 511 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; 512 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; 513 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; 514 uint32_t CM_DGAM_RAMA_END_CNTL1_B; 515 uint32_t CM_DGAM_RAMA_END_CNTL2_B; 516 uint32_t CM_DGAM_RAMA_END_CNTL1_G; 517 uint32_t CM_DGAM_RAMA_END_CNTL2_G; 518 uint32_t CM_DGAM_RAMA_END_CNTL1_R; 519 uint32_t CM_DGAM_RAMA_END_CNTL2_R; 520 uint32_t CM_DGAM_RAMA_REGION_0_1; 521 uint32_t CM_DGAM_RAMA_REGION_2_3; 522 uint32_t CM_DGAM_RAMA_REGION_4_5; 523 uint32_t CM_DGAM_RAMA_REGION_6_7; 524 uint32_t CM_DGAM_RAMA_REGION_8_9; 525 uint32_t CM_DGAM_RAMA_REGION_10_11; 526 uint32_t CM_DGAM_RAMA_REGION_12_13; 527 uint32_t CM_DGAM_RAMA_REGION_14_15; 528 uint32_t CM_MEM_PWR_CTRL; 529 uint32_t CM_IGAM_LUT_RW_CONTROL; 530 uint32_t CM_IGAM_LUT_RW_INDEX; 531 uint32_t CM_IGAM_LUT_SEQ_COLOR; 532 uint32_t CM_DGAM_LUT_WRITE_EN_MASK; 533 uint32_t CM_DGAM_LUT_INDEX; 534 uint32_t CM_DGAM_LUT_DATA; 535 uint32_t CM_CONTROL; 536 uint32_t CM_DGAM_CONTROL; 537 uint32_t CM_IGAM_CONTROL; 538 uint32_t DPP_CONTROL; 539 uint32_t CURSOR_SETTINS; 540 uint32_t CNVC_SURFACE_PIXEL_FORMAT; 541 uint32_t CURSOR0_CONTROL; 542 uint32_t CURSOR0_COLOR0; 543 uint32_t CURSOR0_COLOR1; 544 uint32_t FORMAT_CONTROL; 545 uint32_t CURSOR_SURFACE_ADDRESS_HIGH; 546 uint32_t CURSOR_SURFACE_ADDRESS; 547 uint32_t CURSOR_SIZE; 548 uint32_t CURSOR_CONTROL; 549 uint32_t CURSOR_POSITION; 550 uint32_t CURSOR_HOT_SPOT; 551 uint32_t CURSOR_DST_OFFSET; 552 }; 553 554 struct dcn10_ipp { 555 struct input_pixel_processor base; 556 557 const struct dcn10_ipp_registers *regs; 558 const struct dcn10_ipp_shift *ipp_shift; 559 const struct dcn10_ipp_mask *ipp_mask; 560 561 struct dc_cursor_attributes curs_attr; 562 }; 563 564 void dcn10_ipp_construct(struct dcn10_ipp *ippn10, 565 struct dc_context *ctx, 566 int inst, 567 const struct dcn10_ipp_registers *regs, 568 const struct dcn10_ipp_shift *ipp_shift, 569 const struct dcn10_ipp_mask *ipp_mask); 570 571 #endif /* _DCN10_IPP_H_ */ 572