1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MEM_INPUT_DCN10_H__ 26 #define __DC_MEM_INPUT_DCN10_H__ 27 28 #include "hubp.h" 29 30 #define TO_DCN10_HUBP(hubp)\ 31 container_of(hubp, struct dcn10_hubp, base) 32 33 /* Register address initialization macro for all ASICs (including those with reduced functionality) */ 34 #define HUBP_REG_LIST_DCN(id)\ 35 SRI(DCHUBP_CNTL, HUBP, id),\ 36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ 37 SRI(HUBPREQ_DEBUG, HUBP, id),\ 38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ 39 SRI(DCSURF_TILING_CONFIG, HUBP, id),\ 40 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ 41 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ 42 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ 43 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ 44 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ 45 SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ 46 SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ 47 SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ 48 SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ 49 SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ 50 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 51 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\ 52 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 53 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\ 54 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 55 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ 56 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ 57 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ 58 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 59 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ 60 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ 61 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ 62 SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\ 63 SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\ 64 SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\ 65 SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\ 66 SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\ 67 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\ 68 SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\ 69 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\ 70 SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\ 71 SRI(HUBPRET_CONTROL, HUBPRET, id),\ 72 SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\ 73 SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\ 74 SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\ 75 SRI(BLANK_OFFSET_0, HUBPREQ, id),\ 76 SRI(BLANK_OFFSET_1, HUBPREQ, id),\ 77 SRI(DST_DIMENSIONS, HUBPREQ, id),\ 78 SRI(DST_AFTER_SCALER, HUBPREQ, id),\ 79 SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\ 80 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\ 81 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\ 82 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\ 83 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\ 84 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\ 85 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\ 86 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\ 87 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\ 88 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\ 89 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\ 90 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\ 91 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\ 92 SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\ 93 SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\ 94 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ 95 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ 96 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ 97 SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ 98 SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ 99 SRI(HUBP_CLK_CNTL, HUBP, id) 100 101 /* Register address initialization macro for ASICs with VM */ 102 #define HUBP_REG_LIST_DCN_VM(id)\ 103 SRI(NOM_PARAMETERS_0, HUBPREQ, id),\ 104 SRI(NOM_PARAMETERS_1, HUBPREQ, id),\ 105 SRI(NOM_PARAMETERS_2, HUBPREQ, id),\ 106 SRI(NOM_PARAMETERS_3, HUBPREQ, id),\ 107 SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) 108 109 #define HUBP_REG_LIST_DCN10(id)\ 110 HUBP_REG_LIST_DCN(id),\ 111 HUBP_REG_LIST_DCN_VM(id),\ 112 SRI(PREFETCH_SETTINS, HUBPREQ, id),\ 113 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ 114 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ 115 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ 116 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ 117 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ 118 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ 119 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ 120 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ 121 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ 122 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ 123 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ 124 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ 125 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ 126 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ 127 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ 128 SR(DCHUBBUB_SDPIF_FB_BASE),\ 129 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 130 SRI(CURSOR_SETTINS, HUBPREQ, id), \ 131 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ 132 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ 133 SRI(CURSOR_SIZE, CURSOR, id), \ 134 SRI(CURSOR_CONTROL, CURSOR, id), \ 135 SRI(CURSOR_POSITION, CURSOR, id), \ 136 SRI(CURSOR_HOT_SPOT, CURSOR, id), \ 137 SRI(CURSOR_DST_OFFSET, CURSOR, id) 138 139 #define HUBP_COMMON_REG_VARIABLE_LIST \ 140 uint32_t DCHUBP_CNTL; \ 141 uint32_t HUBPREQ_DEBUG_DB; \ 142 uint32_t HUBPREQ_DEBUG; \ 143 uint32_t DCSURF_ADDR_CONFIG; \ 144 uint32_t DCSURF_TILING_CONFIG; \ 145 uint32_t DCSURF_SURFACE_PITCH; \ 146 uint32_t DCSURF_SURFACE_PITCH_C; \ 147 uint32_t DCSURF_SURFACE_CONFIG; \ 148 uint32_t DCSURF_FLIP_CONTROL; \ 149 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \ 150 uint32_t DCSURF_PRI_VIEWPORT_START; \ 151 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \ 152 uint32_t DCSURF_SEC_VIEWPORT_START; \ 153 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \ 154 uint32_t DCSURF_PRI_VIEWPORT_START_C; \ 155 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \ 156 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \ 157 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \ 158 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \ 159 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \ 160 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \ 161 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \ 162 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \ 163 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \ 164 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \ 165 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \ 166 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \ 167 uint32_t DCSURF_SURFACE_INUSE; \ 168 uint32_t DCSURF_SURFACE_INUSE_HIGH; \ 169 uint32_t DCSURF_SURFACE_INUSE_C; \ 170 uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \ 171 uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \ 172 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \ 173 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ 174 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ 175 uint32_t DCSURF_SURFACE_CONTROL; \ 176 uint32_t HUBPRET_CONTROL; \ 177 uint32_t DCN_EXPANSION_MODE; \ 178 uint32_t DCHUBP_REQ_SIZE_CONFIG; \ 179 uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \ 180 uint32_t BLANK_OFFSET_0; \ 181 uint32_t BLANK_OFFSET_1; \ 182 uint32_t DST_DIMENSIONS; \ 183 uint32_t DST_AFTER_SCALER; \ 184 uint32_t PREFETCH_SETTINS; \ 185 uint32_t PREFETCH_SETTINGS; \ 186 uint32_t VBLANK_PARAMETERS_0; \ 187 uint32_t REF_FREQ_TO_PIX_FREQ; \ 188 uint32_t VBLANK_PARAMETERS_1; \ 189 uint32_t VBLANK_PARAMETERS_3; \ 190 uint32_t NOM_PARAMETERS_0; \ 191 uint32_t NOM_PARAMETERS_1; \ 192 uint32_t NOM_PARAMETERS_4; \ 193 uint32_t NOM_PARAMETERS_5; \ 194 uint32_t PER_LINE_DELIVERY_PRE; \ 195 uint32_t PER_LINE_DELIVERY; \ 196 uint32_t PREFETCH_SETTINS_C; \ 197 uint32_t PREFETCH_SETTINGS_C; \ 198 uint32_t VBLANK_PARAMETERS_2; \ 199 uint32_t VBLANK_PARAMETERS_4; \ 200 uint32_t NOM_PARAMETERS_2; \ 201 uint32_t NOM_PARAMETERS_3; \ 202 uint32_t NOM_PARAMETERS_6; \ 203 uint32_t NOM_PARAMETERS_7; \ 204 uint32_t DCN_TTU_QOS_WM; \ 205 uint32_t DCN_GLOBAL_TTU_CNTL; \ 206 uint32_t DCN_SURF0_TTU_CNTL0; \ 207 uint32_t DCN_SURF0_TTU_CNTL1; \ 208 uint32_t DCN_SURF1_TTU_CNTL0; \ 209 uint32_t DCN_SURF1_TTU_CNTL1; \ 210 uint32_t DCN_CUR0_TTU_CNTL0; \ 211 uint32_t DCN_CUR0_TTU_CNTL1; \ 212 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ 213 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ 214 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ 215 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \ 216 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \ 217 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \ 218 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \ 219 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \ 220 uint32_t DCN_VM_MX_L1_TLB_CNTL; \ 221 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \ 222 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \ 223 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \ 224 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \ 225 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \ 226 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ 227 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ 228 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ 229 uint32_t DCHUBBUB_SDPIF_FB_BASE; \ 230 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \ 231 uint32_t DCN_VM_FB_LOCATION_TOP; \ 232 uint32_t DCN_VM_FB_LOCATION_BASE; \ 233 uint32_t DCN_VM_FB_OFFSET; \ 234 uint32_t DCN_VM_AGP_BASE; \ 235 uint32_t DCN_VM_AGP_BOT; \ 236 uint32_t DCN_VM_AGP_TOP; \ 237 uint32_t CURSOR_SETTINS; \ 238 uint32_t CURSOR_SETTINGS; \ 239 uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ 240 uint32_t CURSOR_SURFACE_ADDRESS; \ 241 uint32_t CURSOR_SIZE; \ 242 uint32_t CURSOR_CONTROL; \ 243 uint32_t CURSOR_POSITION; \ 244 uint32_t CURSOR_HOT_SPOT; \ 245 uint32_t CURSOR_DST_OFFSET; \ 246 uint32_t HUBP_CLK_CNTL 247 248 #define HUBP_SF(reg_name, field_name, post_fix)\ 249 .field_name = reg_name ## __ ## field_name ## post_fix 250 251 /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ 252 #define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ 253 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ 254 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ 255 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ 256 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ 257 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ 258 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ 259 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ 260 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ 261 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ 262 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ 263 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ 264 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ 265 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ 266 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ 267 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ 268 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ 269 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ 270 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ 271 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ 272 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ 273 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ 274 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ 275 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ 276 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ 277 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ 278 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ 279 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ 280 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ 281 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ 282 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ 283 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ 284 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ 285 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ 286 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ 287 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ 288 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ 289 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ 290 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ 291 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ 292 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 293 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ 294 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 295 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ 296 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ 297 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ 298 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ 299 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ 300 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 301 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ 302 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ 303 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ 304 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ 305 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ 306 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ 307 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ 308 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ 309 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ 310 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ 311 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ 312 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ 313 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ 314 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ 315 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ 316 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ 317 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ 318 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ 319 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ 320 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ 321 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ 322 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ 323 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ 324 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ 325 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ 326 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ 327 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ 328 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ 329 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ 330 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ 331 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ 332 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ 333 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ 334 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ 335 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ 336 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ 337 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ 338 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ 339 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ 340 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ 341 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ 342 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ 343 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ 344 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ 345 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ 346 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ 347 HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ 348 HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ 349 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ 350 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ 351 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ 352 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ 353 HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ 354 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ 355 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ 356 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ 357 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ 358 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ 359 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ 360 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ 361 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ 362 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ 363 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ 364 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ 365 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ 366 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ 367 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ 368 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ 369 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ 370 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ 371 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ 372 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ 373 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ 374 HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) 375 376 #define HUBP_MASK_SH_LIST_DCN(mask_sh)\ 377 HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh),\ 378 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ 379 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) 380 381 /* Mask/shift struct generation macro for ASICs with VM */ 382 #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ 383 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ 384 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ 385 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ 386 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ 387 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ 388 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ 389 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ 390 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ 391 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ 392 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) 393 394 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ 395 HUBP_MASK_SH_LIST_DCN(mask_sh),\ 396 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ 397 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ 398 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ 399 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ 400 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ 401 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ 402 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ 403 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ 404 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ 405 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ 406 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ 407 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ 408 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ 409 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ 410 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ 411 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ 412 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ 413 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ 414 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ 415 HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ 416 HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ 417 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ 418 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ 419 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ 420 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ 421 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ 422 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 423 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 424 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ 425 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ 426 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 427 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 428 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 429 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 430 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 431 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ 432 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 433 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 434 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 435 HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) 436 437 #define DCN_HUBP_REG_FIELD_LIST(type) \ 438 type HUBP_BLANK_EN;\ 439 type HUBP_DISABLE;\ 440 type HUBP_TTU_DISABLE;\ 441 type HUBP_NO_OUTSTANDING_REQ;\ 442 type HUBP_VTG_SEL;\ 443 type HUBP_UNDERFLOW_STATUS;\ 444 type HUBP_UNDERFLOW_CLEAR;\ 445 type NUM_PIPES;\ 446 type NUM_BANKS;\ 447 type PIPE_INTERLEAVE;\ 448 type NUM_SE;\ 449 type NUM_RB_PER_SE;\ 450 type MAX_COMPRESSED_FRAGS;\ 451 type SW_MODE;\ 452 type META_LINEAR;\ 453 type RB_ALIGNED;\ 454 type PIPE_ALIGNED;\ 455 type PITCH;\ 456 type META_PITCH;\ 457 type PITCH_C;\ 458 type META_PITCH_C;\ 459 type ROTATION_ANGLE;\ 460 type H_MIRROR_EN;\ 461 type SURFACE_PIXEL_FORMAT;\ 462 type ALPHA_PLANE_EN;\ 463 type SURFACE_FLIP_TYPE;\ 464 type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ 465 type SURFACE_FLIP_IN_STEREOSYNC;\ 466 type SURFACE_UPDATE_LOCK;\ 467 type SURFACE_FLIP_PENDING;\ 468 type PRI_VIEWPORT_WIDTH; \ 469 type PRI_VIEWPORT_HEIGHT; \ 470 type PRI_VIEWPORT_X_START; \ 471 type PRI_VIEWPORT_Y_START; \ 472 type SEC_VIEWPORT_WIDTH; \ 473 type SEC_VIEWPORT_HEIGHT; \ 474 type SEC_VIEWPORT_X_START; \ 475 type SEC_VIEWPORT_Y_START; \ 476 type PRI_VIEWPORT_WIDTH_C; \ 477 type PRI_VIEWPORT_HEIGHT_C; \ 478 type PRI_VIEWPORT_X_START_C; \ 479 type PRI_VIEWPORT_Y_START_C; \ 480 type PRIMARY_SURFACE_ADDRESS_HIGH;\ 481 type PRIMARY_SURFACE_ADDRESS;\ 482 type SECONDARY_SURFACE_ADDRESS_HIGH;\ 483 type SECONDARY_SURFACE_ADDRESS;\ 484 type PRIMARY_META_SURFACE_ADDRESS_HIGH;\ 485 type PRIMARY_META_SURFACE_ADDRESS;\ 486 type SECONDARY_META_SURFACE_ADDRESS_HIGH;\ 487 type SECONDARY_META_SURFACE_ADDRESS;\ 488 type PRIMARY_SURFACE_ADDRESS_HIGH_C;\ 489 type PRIMARY_SURFACE_ADDRESS_C;\ 490 type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\ 491 type PRIMARY_META_SURFACE_ADDRESS_C;\ 492 type SURFACE_INUSE_ADDRESS;\ 493 type SURFACE_INUSE_ADDRESS_HIGH;\ 494 type SURFACE_INUSE_ADDRESS_C;\ 495 type SURFACE_INUSE_ADDRESS_HIGH_C;\ 496 type SURFACE_EARLIEST_INUSE_ADDRESS;\ 497 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\ 498 type SURFACE_EARLIEST_INUSE_ADDRESS_C;\ 499 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\ 500 type PRIMARY_SURFACE_TMZ;\ 501 type PRIMARY_SURFACE_TMZ_C;\ 502 type SECONDARY_SURFACE_TMZ;\ 503 type SECONDARY_SURFACE_TMZ_C;\ 504 type PRIMARY_META_SURFACE_TMZ;\ 505 type PRIMARY_META_SURFACE_TMZ_C;\ 506 type SECONDARY_META_SURFACE_TMZ;\ 507 type SECONDARY_META_SURFACE_TMZ_C;\ 508 type PRIMARY_SURFACE_DCC_EN;\ 509 type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ 510 type SECONDARY_SURFACE_DCC_EN;\ 511 type SECONDARY_SURFACE_DCC_IND_64B_BLK;\ 512 type DET_BUF_PLANE1_BASE_ADDRESS;\ 513 type CROSSBAR_SRC_CB_B;\ 514 type CROSSBAR_SRC_CR_R;\ 515 type DRQ_EXPANSION_MODE;\ 516 type PRQ_EXPANSION_MODE;\ 517 type MRQ_EXPANSION_MODE;\ 518 type CRQ_EXPANSION_MODE;\ 519 type CHUNK_SIZE;\ 520 type MIN_CHUNK_SIZE;\ 521 type META_CHUNK_SIZE;\ 522 type MIN_META_CHUNK_SIZE;\ 523 type DPTE_GROUP_SIZE;\ 524 type MPTE_GROUP_SIZE;\ 525 type SWATH_HEIGHT;\ 526 type PTE_ROW_HEIGHT_LINEAR;\ 527 type CHUNK_SIZE_C;\ 528 type MIN_CHUNK_SIZE_C;\ 529 type META_CHUNK_SIZE_C;\ 530 type MIN_META_CHUNK_SIZE_C;\ 531 type DPTE_GROUP_SIZE_C;\ 532 type MPTE_GROUP_SIZE_C;\ 533 type SWATH_HEIGHT_C;\ 534 type PTE_ROW_HEIGHT_LINEAR_C;\ 535 type REFCYC_H_BLANK_END;\ 536 type DLG_V_BLANK_END;\ 537 type MIN_DST_Y_NEXT_START;\ 538 type REFCYC_PER_HTOTAL;\ 539 type REFCYC_X_AFTER_SCALER;\ 540 type DST_Y_AFTER_SCALER;\ 541 type DST_Y_PREFETCH;\ 542 type VRATIO_PREFETCH;\ 543 type DST_Y_PER_VM_VBLANK;\ 544 type DST_Y_PER_ROW_VBLANK;\ 545 type REF_FREQ_TO_PIX_FREQ;\ 546 type REFCYC_PER_PTE_GROUP_VBLANK_L;\ 547 type REFCYC_PER_META_CHUNK_VBLANK_L;\ 548 type DST_Y_PER_PTE_ROW_NOM_L;\ 549 type REFCYC_PER_PTE_GROUP_NOM_L;\ 550 type DST_Y_PER_META_ROW_NOM_L;\ 551 type REFCYC_PER_META_CHUNK_NOM_L;\ 552 type REFCYC_PER_LINE_DELIVERY_PRE_L;\ 553 type REFCYC_PER_LINE_DELIVERY_PRE_C;\ 554 type REFCYC_PER_LINE_DELIVERY_L;\ 555 type REFCYC_PER_LINE_DELIVERY_C;\ 556 type VRATIO_PREFETCH_C;\ 557 type REFCYC_PER_PTE_GROUP_VBLANK_C;\ 558 type REFCYC_PER_META_CHUNK_VBLANK_C;\ 559 type DST_Y_PER_PTE_ROW_NOM_C;\ 560 type REFCYC_PER_PTE_GROUP_NOM_C;\ 561 type DST_Y_PER_META_ROW_NOM_C;\ 562 type REFCYC_PER_META_CHUNK_NOM_C;\ 563 type QoS_LEVEL_LOW_WM;\ 564 type QoS_LEVEL_HIGH_WM;\ 565 type MIN_TTU_VBLANK;\ 566 type QoS_LEVEL_FLIP;\ 567 type REFCYC_PER_REQ_DELIVERY;\ 568 type QoS_LEVEL_FIXED;\ 569 type QoS_RAMP_DISABLE;\ 570 type REFCYC_PER_REQ_DELIVERY_PRE;\ 571 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\ 572 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\ 573 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\ 574 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\ 575 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\ 576 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\ 577 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ 578 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\ 579 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ 580 type ENABLE_L1_TLB;\ 581 type SYSTEM_ACCESS_MODE;\ 582 type HUBP_CLOCK_ENABLE;\ 583 type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ 584 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ 585 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ 586 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\ 587 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\ 588 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\ 589 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ 590 type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ 591 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ 592 type SDPIF_FB_TOP;\ 593 type SDPIF_FB_BASE;\ 594 type SDPIF_FB_OFFSET;\ 595 type SDPIF_AGP_BASE;\ 596 type SDPIF_AGP_BOT;\ 597 type SDPIF_AGP_TOP;\ 598 type FB_TOP;\ 599 type FB_BASE;\ 600 type FB_OFFSET;\ 601 type AGP_BASE;\ 602 type AGP_BOT;\ 603 type AGP_TOP;\ 604 type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ 605 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ 606 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ 607 /* todo: get these from GVM instead of reading registers ourselves */\ 608 type PAGE_DIRECTORY_ENTRY_HI32;\ 609 type PAGE_DIRECTORY_ENTRY_LO32;\ 610 type LOGICAL_PAGE_NUMBER_HI4;\ 611 type LOGICAL_PAGE_NUMBER_LO32;\ 612 type PHYSICAL_PAGE_ADDR_HI4;\ 613 type PHYSICAL_PAGE_ADDR_LO32;\ 614 type PHYSICAL_PAGE_NUMBER_MSB;\ 615 type PHYSICAL_PAGE_NUMBER_LSB;\ 616 type LOGICAL_ADDR;\ 617 type CURSOR0_DST_Y_OFFSET; \ 618 type CURSOR0_CHUNK_HDL_ADJUST; \ 619 type CURSOR_SURFACE_ADDRESS_HIGH; \ 620 type CURSOR_SURFACE_ADDRESS; \ 621 type CURSOR_WIDTH; \ 622 type CURSOR_HEIGHT; \ 623 type CURSOR_MODE; \ 624 type CURSOR_2X_MAGNIFY; \ 625 type CURSOR_PITCH; \ 626 type CURSOR_LINES_PER_CHUNK; \ 627 type CURSOR_ENABLE; \ 628 type CURSOR_X_POSITION; \ 629 type CURSOR_Y_POSITION; \ 630 type CURSOR_HOT_SPOT_X; \ 631 type CURSOR_HOT_SPOT_Y; \ 632 type CURSOR_DST_X_OFFSET; \ 633 type OUTPUT_FP 634 635 struct dcn_mi_registers { 636 HUBP_COMMON_REG_VARIABLE_LIST; 637 }; 638 639 struct dcn_mi_shift { 640 DCN_HUBP_REG_FIELD_LIST(uint8_t); 641 }; 642 643 struct dcn_mi_mask { 644 DCN_HUBP_REG_FIELD_LIST(uint32_t); 645 }; 646 647 struct dcn_hubp_state { 648 struct _vcs_dpi_display_dlg_regs_st dlg_attr; 649 struct _vcs_dpi_display_ttu_regs_st ttu_attr; 650 struct _vcs_dpi_display_rq_regs_st rq_regs; 651 uint32_t pixel_format; 652 uint32_t inuse_addr_hi; 653 uint32_t inuse_addr_lo; 654 uint32_t viewport_width; 655 uint32_t viewport_height; 656 uint32_t rotation_angle; 657 uint32_t h_mirror_en; 658 uint32_t sw_mode; 659 uint32_t dcc_en; 660 uint32_t blank_en; 661 uint32_t underflow_status; 662 uint32_t ttu_disable; 663 uint32_t min_ttu_vblank; 664 uint32_t qos_level_low_wm; 665 uint32_t qos_level_high_wm; 666 }; 667 668 struct dcn10_hubp { 669 struct hubp base; 670 struct dcn_hubp_state state; 671 const struct dcn_mi_registers *hubp_regs; 672 const struct dcn_mi_shift *hubp_shift; 673 const struct dcn_mi_mask *hubp_mask; 674 }; 675 676 void hubp1_program_surface_config( 677 struct hubp *hubp, 678 enum surface_pixel_format format, 679 union dc_tiling_info *tiling_info, 680 union plane_size *plane_size, 681 enum dc_rotation_angle rotation, 682 struct dc_plane_dcc_param *dcc, 683 bool horizontal_mirror, 684 unsigned int compat_level); 685 686 void hubp1_program_deadline( 687 struct hubp *hubp, 688 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 689 struct _vcs_dpi_display_ttu_regs_st *ttu_attr); 690 691 void hubp1_program_requestor( 692 struct hubp *hubp, 693 struct _vcs_dpi_display_rq_regs_st *rq_regs); 694 695 void hubp1_program_pixel_format( 696 struct hubp *hubp, 697 enum surface_pixel_format format); 698 699 void hubp1_program_size( 700 struct hubp *hubp, 701 enum surface_pixel_format format, 702 const union plane_size *plane_size, 703 struct dc_plane_dcc_param *dcc); 704 705 void hubp1_program_rotation( 706 struct hubp *hubp, 707 enum dc_rotation_angle rotation, 708 bool horizontal_mirror); 709 710 void hubp1_program_tiling( 711 struct hubp *hubp, 712 const union dc_tiling_info *info, 713 const enum surface_pixel_format pixel_format); 714 715 void hubp1_dcc_control(struct hubp *hubp, 716 bool enable, 717 bool independent_64b_blks); 718 719 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 720 bool hubp1_program_surface_flip_and_addr( 721 struct hubp *hubp, 722 const struct dc_plane_address *address, 723 bool flip_immediate); 724 725 #endif 726 bool hubp1_is_flip_pending(struct hubp *hubp); 727 728 void hubp1_cursor_set_attributes( 729 struct hubp *hubp, 730 const struct dc_cursor_attributes *attr); 731 732 void hubp1_cursor_set_position( 733 struct hubp *hubp, 734 const struct dc_cursor_position *pos, 735 const struct dc_cursor_mi_param *param); 736 737 void hubp1_set_blank(struct hubp *hubp, bool blank); 738 739 void min_set_viewport(struct hubp *hubp, 740 const struct rect *viewport, 741 const struct rect *viewport_c); 742 743 void hubp1_clk_cntl(struct hubp *hubp, bool enable); 744 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); 745 746 void dcn10_hubp_construct( 747 struct dcn10_hubp *hubp1, 748 struct dc_context *ctx, 749 uint32_t inst, 750 const struct dcn_mi_registers *hubp_regs, 751 const struct dcn_mi_shift *hubp_shift, 752 const struct dcn_mi_mask *hubp_mask); 753 754 void hubp1_read_state(struct hubp *hubp); 755 void hubp1_clear_underflow(struct hubp *hubp); 756 757 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch); 758 759 void hubp1_vready_workaround(struct hubp *hubp, 760 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 761 762 void hubp1_init(struct hubp *hubp); 763 764 #endif 765