1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = 0xf; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 103 { 104 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 105 uint32_t blank_en = blank ? 1 : 0; 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 108 } 109 110 static void hubp1_vready_workaround(struct hubp *hubp, 111 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 112 { 113 uint32_t value = 0; 114 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 115 116 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 117 value = REG_READ(HUBPREQ_DEBUG_DB); 118 119 /* hack mode disable */ 120 value |= 0x100; 121 value &= ~0x1000; 122 123 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 124 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 125 /* if (eco_fix_needed(otg_global_sync_timing) 126 * set HBUBREQ_DEBUG_DB[12] = 1 */ 127 value |= 0x1000; 128 } 129 130 REG_WRITE(HUBPREQ_DEBUG_DB, value); 131 } 132 133 void hubp1_program_tiling( 134 struct hubp *hubp, 135 const union dc_tiling_info *info, 136 const enum surface_pixel_format pixel_format) 137 { 138 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 139 140 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 141 NUM_PIPES, log_2(info->gfx9.num_pipes), 142 NUM_BANKS, log_2(info->gfx9.num_banks), 143 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 144 NUM_SE, log_2(info->gfx9.num_shader_engines), 145 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 146 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 147 148 REG_UPDATE_4(DCSURF_TILING_CONFIG, 149 SW_MODE, info->gfx9.swizzle, 150 META_LINEAR, info->gfx9.meta_linear, 151 RB_ALIGNED, info->gfx9.rb_aligned, 152 PIPE_ALIGNED, info->gfx9.pipe_aligned); 153 } 154 155 void hubp1_program_size_and_rotation( 156 struct hubp *hubp, 157 enum dc_rotation_angle rotation, 158 enum surface_pixel_format format, 159 const union plane_size *plane_size, 160 struct dc_plane_dcc_param *dcc, 161 bool horizontal_mirror) 162 { 163 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 164 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror; 165 166 /* Program data and meta surface pitch (calculation from addrlib) 167 * 444 or 420 luma 168 */ 169 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 170 ASSERT(plane_size->video.chroma_pitch != 0); 171 /* Chroma pitch zero can cause system hang! */ 172 173 pitch = plane_size->video.luma_pitch - 1; 174 meta_pitch = dcc->video.meta_pitch_l - 1; 175 pitch_c = plane_size->video.chroma_pitch - 1; 176 meta_pitch_c = dcc->video.meta_pitch_c - 1; 177 } else { 178 pitch = plane_size->grph.surface_pitch - 1; 179 meta_pitch = dcc->grph.meta_pitch - 1; 180 pitch_c = 0; 181 meta_pitch_c = 0; 182 } 183 184 if (!dcc->enable) { 185 meta_pitch = 0; 186 meta_pitch_c = 0; 187 } 188 189 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 190 PITCH, pitch, META_PITCH, meta_pitch); 191 192 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 193 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 194 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 195 196 if (horizontal_mirror) 197 mirror = 1; 198 else 199 mirror = 0; 200 201 202 /* Program rotation angle and horz mirror - no mirror */ 203 if (rotation == ROTATION_ANGLE_0) 204 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 205 ROTATION_ANGLE, 0, 206 H_MIRROR_EN, mirror); 207 else if (rotation == ROTATION_ANGLE_90) 208 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 209 ROTATION_ANGLE, 1, 210 H_MIRROR_EN, mirror); 211 else if (rotation == ROTATION_ANGLE_180) 212 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 213 ROTATION_ANGLE, 2, 214 H_MIRROR_EN, mirror); 215 else if (rotation == ROTATION_ANGLE_270) 216 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 217 ROTATION_ANGLE, 3, 218 H_MIRROR_EN, mirror); 219 } 220 221 void hubp1_program_pixel_format( 222 struct hubp *hubp, 223 enum surface_pixel_format format) 224 { 225 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 226 uint32_t red_bar = 3; 227 uint32_t blue_bar = 2; 228 229 /* swap for ABGR format */ 230 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 231 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 232 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 233 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 234 red_bar = 2; 235 blue_bar = 3; 236 } 237 238 REG_UPDATE_2(HUBPRET_CONTROL, 239 CROSSBAR_SRC_CB_B, blue_bar, 240 CROSSBAR_SRC_CR_R, red_bar); 241 242 /* Mapping is same as ipp programming (cnvc) */ 243 244 switch (format) { 245 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 246 REG_UPDATE(DCSURF_SURFACE_CONFIG, 247 SURFACE_PIXEL_FORMAT, 1); 248 break; 249 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 250 REG_UPDATE(DCSURF_SURFACE_CONFIG, 251 SURFACE_PIXEL_FORMAT, 3); 252 break; 253 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 255 REG_UPDATE(DCSURF_SURFACE_CONFIG, 256 SURFACE_PIXEL_FORMAT, 8); 257 break; 258 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 259 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 260 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 261 REG_UPDATE(DCSURF_SURFACE_CONFIG, 262 SURFACE_PIXEL_FORMAT, 10); 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 265 REG_UPDATE(DCSURF_SURFACE_CONFIG, 266 SURFACE_PIXEL_FORMAT, 22); 267 break; 268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 270 REG_UPDATE(DCSURF_SURFACE_CONFIG, 271 SURFACE_PIXEL_FORMAT, 24); 272 break; 273 274 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 275 REG_UPDATE(DCSURF_SURFACE_CONFIG, 276 SURFACE_PIXEL_FORMAT, 65); 277 break; 278 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 279 REG_UPDATE(DCSURF_SURFACE_CONFIG, 280 SURFACE_PIXEL_FORMAT, 64); 281 break; 282 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 283 REG_UPDATE(DCSURF_SURFACE_CONFIG, 284 SURFACE_PIXEL_FORMAT, 67); 285 break; 286 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 287 REG_UPDATE(DCSURF_SURFACE_CONFIG, 288 SURFACE_PIXEL_FORMAT, 66); 289 break; 290 default: 291 BREAK_TO_DEBUGGER(); 292 break; 293 } 294 295 /* don't see the need of program the xbar in DCN 1.0 */ 296 } 297 298 bool hubp1_program_surface_flip_and_addr( 299 struct hubp *hubp, 300 const struct dc_plane_address *address, 301 bool flip_immediate) 302 { 303 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 304 305 /* program flip type */ 306 REG_SET(DCSURF_FLIP_CONTROL, 0, 307 SURFACE_FLIP_TYPE, flip_immediate); 308 309 /* HW automatically latch rest of address register on write to 310 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 311 * 312 * program high first and then the low addr, order matters! 313 */ 314 switch (address->type) { 315 case PLN_ADDR_TYPE_GRAPHICS: 316 /* DCN1.0 does not support const color 317 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 318 * base on address->grph.dcc_const_color 319 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 320 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 321 */ 322 323 if (address->grph.addr.quad_part == 0) 324 break; 325 326 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 327 PRIMARY_SURFACE_TMZ, address->tmz_surface, 328 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 329 330 if (address->grph.meta_addr.quad_part != 0) { 331 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 332 PRIMARY_META_SURFACE_ADDRESS_HIGH, 333 address->grph.meta_addr.high_part); 334 335 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 336 PRIMARY_META_SURFACE_ADDRESS, 337 address->grph.meta_addr.low_part); 338 } 339 340 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 341 PRIMARY_SURFACE_ADDRESS_HIGH, 342 address->grph.addr.high_part); 343 344 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 345 PRIMARY_SURFACE_ADDRESS, 346 address->grph.addr.low_part); 347 break; 348 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 349 if (address->video_progressive.luma_addr.quad_part == 0 350 || address->video_progressive.chroma_addr.quad_part == 0) 351 break; 352 353 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 354 PRIMARY_SURFACE_TMZ, address->tmz_surface, 355 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 356 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 357 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 358 359 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 360 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 361 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 362 address->video_progressive.chroma_meta_addr.high_part); 363 364 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 365 PRIMARY_META_SURFACE_ADDRESS_C, 366 address->video_progressive.chroma_meta_addr.low_part); 367 368 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 369 PRIMARY_META_SURFACE_ADDRESS_HIGH, 370 address->video_progressive.luma_meta_addr.high_part); 371 372 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 373 PRIMARY_META_SURFACE_ADDRESS, 374 address->video_progressive.luma_meta_addr.low_part); 375 } 376 377 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 378 PRIMARY_SURFACE_ADDRESS_HIGH_C, 379 address->video_progressive.chroma_addr.high_part); 380 381 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 382 PRIMARY_SURFACE_ADDRESS_C, 383 address->video_progressive.chroma_addr.low_part); 384 385 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 386 PRIMARY_SURFACE_ADDRESS_HIGH, 387 address->video_progressive.luma_addr.high_part); 388 389 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 390 PRIMARY_SURFACE_ADDRESS, 391 address->video_progressive.luma_addr.low_part); 392 break; 393 case PLN_ADDR_TYPE_GRPH_STEREO: 394 if (address->grph_stereo.left_addr.quad_part == 0) 395 break; 396 if (address->grph_stereo.right_addr.quad_part == 0) 397 break; 398 399 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 400 PRIMARY_SURFACE_TMZ, address->tmz_surface, 401 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 402 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 403 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 404 SECONDARY_SURFACE_TMZ, address->tmz_surface, 405 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 406 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 407 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 408 409 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 410 411 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 412 SECONDARY_META_SURFACE_ADDRESS_HIGH, 413 address->grph_stereo.right_meta_addr.high_part); 414 415 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 416 SECONDARY_META_SURFACE_ADDRESS, 417 address->grph_stereo.right_meta_addr.low_part); 418 } 419 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 420 421 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 422 PRIMARY_META_SURFACE_ADDRESS_HIGH, 423 address->grph_stereo.left_meta_addr.high_part); 424 425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 426 PRIMARY_META_SURFACE_ADDRESS, 427 address->grph_stereo.left_meta_addr.low_part); 428 } 429 430 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 431 SECONDARY_SURFACE_ADDRESS_HIGH, 432 address->grph_stereo.right_addr.high_part); 433 434 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 435 SECONDARY_SURFACE_ADDRESS, 436 address->grph_stereo.right_addr.low_part); 437 438 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 439 PRIMARY_SURFACE_ADDRESS_HIGH, 440 address->grph_stereo.left_addr.high_part); 441 442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 443 PRIMARY_SURFACE_ADDRESS, 444 address->grph_stereo.left_addr.low_part); 445 break; 446 default: 447 BREAK_TO_DEBUGGER(); 448 break; 449 } 450 451 hubp->request_address = *address; 452 453 if (flip_immediate) 454 hubp->current_address = *address; 455 456 return true; 457 } 458 459 void hubp1_dcc_control(struct hubp *hubp, bool enable, 460 bool independent_64b_blks) 461 { 462 uint32_t dcc_en = enable ? 1 : 0; 463 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 464 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 465 466 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 467 PRIMARY_SURFACE_DCC_EN, dcc_en, 468 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 469 SECONDARY_SURFACE_DCC_EN, dcc_en, 470 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 471 } 472 473 void hubp1_program_surface_config( 474 struct hubp *hubp, 475 enum surface_pixel_format format, 476 union dc_tiling_info *tiling_info, 477 union plane_size *plane_size, 478 enum dc_rotation_angle rotation, 479 struct dc_plane_dcc_param *dcc, 480 bool horizontal_mirror) 481 { 482 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 483 hubp1_program_tiling(hubp, tiling_info, format); 484 hubp1_program_size_and_rotation( 485 hubp, rotation, format, plane_size, dcc, horizontal_mirror); 486 hubp1_program_pixel_format(hubp, format); 487 } 488 489 void hubp1_program_requestor( 490 struct hubp *hubp, 491 struct _vcs_dpi_display_rq_regs_st *rq_regs) 492 { 493 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 494 495 REG_UPDATE(HUBPRET_CONTROL, 496 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 497 REG_SET_4(DCN_EXPANSION_MODE, 0, 498 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 499 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 500 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 501 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 502 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 503 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 504 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 505 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 506 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 507 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 508 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 509 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 510 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 511 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 512 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 513 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 514 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 515 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 516 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 517 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 518 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 519 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 520 } 521 522 523 void hubp1_program_deadline( 524 struct hubp *hubp, 525 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 526 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 527 { 528 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 529 530 /* DLG - Per hubp */ 531 REG_SET_2(BLANK_OFFSET_0, 0, 532 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 533 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 534 535 REG_SET(BLANK_OFFSET_1, 0, 536 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 537 538 REG_SET(DST_DIMENSIONS, 0, 539 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 540 541 REG_SET_2(DST_AFTER_SCALER, 0, 542 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 543 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 544 545 if (REG(PREFETCH_SETTINS)) 546 REG_SET_2(PREFETCH_SETTINS, 0, 547 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 548 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 549 else 550 REG_SET_2(PREFETCH_SETTINGS, 0, 551 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 552 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 553 554 REG_SET_2(VBLANK_PARAMETERS_0, 0, 555 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 556 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 557 558 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 559 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 560 561 /* DLG - Per luma/chroma */ 562 REG_SET(VBLANK_PARAMETERS_1, 0, 563 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 564 565 REG_SET(VBLANK_PARAMETERS_3, 0, 566 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 567 568 if (REG(NOM_PARAMETERS_0)) 569 REG_SET(NOM_PARAMETERS_0, 0, 570 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 571 572 if (REG(NOM_PARAMETERS_1)) 573 REG_SET(NOM_PARAMETERS_1, 0, 574 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 575 576 REG_SET(NOM_PARAMETERS_4, 0, 577 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 578 579 REG_SET(NOM_PARAMETERS_5, 0, 580 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 581 582 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 583 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 584 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 585 586 REG_SET_2(PER_LINE_DELIVERY, 0, 587 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 588 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 589 590 if (REG(PREFETCH_SETTINS_C)) 591 REG_SET(PREFETCH_SETTINS_C, 0, 592 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 593 else 594 REG_SET(PREFETCH_SETTINGS_C, 0, 595 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 596 597 REG_SET(VBLANK_PARAMETERS_2, 0, 598 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 599 600 REG_SET(VBLANK_PARAMETERS_4, 0, 601 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 602 603 if (REG(NOM_PARAMETERS_2)) 604 REG_SET(NOM_PARAMETERS_2, 0, 605 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 606 607 if (REG(NOM_PARAMETERS_3)) 608 REG_SET(NOM_PARAMETERS_3, 0, 609 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 610 611 REG_SET(NOM_PARAMETERS_6, 0, 612 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 613 614 REG_SET(NOM_PARAMETERS_7, 0, 615 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 616 617 /* TTU - per hubp */ 618 REG_SET_2(DCN_TTU_QOS_WM, 0, 619 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 620 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 621 622 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 623 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 624 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 625 626 /* TTU - per luma/chroma */ 627 /* Assumed surf0 is luma and 1 is chroma */ 628 629 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 630 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 631 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 632 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 633 634 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 635 REFCYC_PER_REQ_DELIVERY_PRE, 636 ttu_attr->refcyc_per_req_delivery_pre_l); 637 638 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 639 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 640 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 641 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 642 643 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 644 REFCYC_PER_REQ_DELIVERY_PRE, 645 ttu_attr->refcyc_per_req_delivery_pre_c); 646 647 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 648 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 649 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 650 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 651 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 652 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 653 } 654 655 static void hubp1_setup( 656 struct hubp *hubp, 657 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 658 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 659 struct _vcs_dpi_display_rq_regs_st *rq_regs, 660 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 661 { 662 /* otg is locked when this func is called. Register are double buffered. 663 * disable the requestors is not needed 664 */ 665 hubp1_program_requestor(hubp, rq_regs); 666 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 667 hubp1_vready_workaround(hubp, pipe_dest); 668 } 669 670 bool hubp1_is_flip_pending(struct hubp *hubp) 671 { 672 uint32_t flip_pending = 0; 673 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 674 struct dc_plane_address earliest_inuse_address; 675 676 REG_GET(DCSURF_FLIP_CONTROL, 677 SURFACE_FLIP_PENDING, &flip_pending); 678 679 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 680 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 681 682 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 683 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 684 685 if (flip_pending) 686 return true; 687 688 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 689 return true; 690 691 hubp->current_address = hubp->request_address; 692 return false; 693 } 694 695 uint32_t aperture_default_system = 1; 696 uint32_t context0_default_system; /* = 0;*/ 697 698 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 699 struct vm_system_aperture_param *apt) 700 { 701 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 702 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 703 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 704 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 705 706 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 707 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 708 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 709 710 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 711 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 712 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 713 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 714 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 715 716 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 717 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 718 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 719 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 720 721 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 722 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 723 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 724 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 725 } 726 727 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 728 const struct vm_context0_param *vm0) 729 { 730 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 731 /* pte base */ 732 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 733 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 734 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 735 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 736 737 /* pte start */ 738 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 739 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 740 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 741 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 742 743 /* pte end */ 744 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 745 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 746 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 747 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 748 749 /* fault handling */ 750 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 751 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 752 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 753 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 754 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 755 756 /* control: enable VM PTE*/ 757 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 758 ENABLE_L1_TLB, 1, 759 SYSTEM_ACCESS_MODE, 3); 760 } 761 762 void min_set_viewport( 763 struct hubp *hubp, 764 const struct rect *viewport, 765 const struct rect *viewport_c) 766 { 767 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 768 769 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 770 PRI_VIEWPORT_WIDTH, viewport->width, 771 PRI_VIEWPORT_HEIGHT, viewport->height); 772 773 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 774 PRI_VIEWPORT_X_START, viewport->x, 775 PRI_VIEWPORT_Y_START, viewport->y); 776 777 /*for stereo*/ 778 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 779 SEC_VIEWPORT_WIDTH, viewport->width, 780 SEC_VIEWPORT_HEIGHT, viewport->height); 781 782 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 783 SEC_VIEWPORT_X_START, viewport->x, 784 SEC_VIEWPORT_Y_START, viewport->y); 785 786 /* DC supports NV12 only at the moment */ 787 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 788 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 789 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 790 791 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 792 PRI_VIEWPORT_X_START_C, viewport_c->x, 793 PRI_VIEWPORT_Y_START_C, viewport_c->y); 794 } 795 796 void hubp1_read_state(struct hubp *hubp) 797 { 798 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 799 struct dcn_hubp_state *s = &hubp1->state; 800 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 801 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 802 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 803 804 /* Requester */ 805 REG_GET(HUBPRET_CONTROL, 806 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 807 REG_GET_4(DCN_EXPANSION_MODE, 808 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 809 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 810 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 811 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 812 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 813 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 814 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 815 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 816 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 817 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 818 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 819 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 820 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 821 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 822 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 823 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 824 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 825 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 826 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 827 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 828 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 829 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 830 831 /* DLG - Per hubp */ 832 REG_GET_2(BLANK_OFFSET_0, 833 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 834 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 835 836 REG_GET(BLANK_OFFSET_1, 837 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 838 839 REG_GET(DST_DIMENSIONS, 840 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 841 842 REG_GET_2(DST_AFTER_SCALER, 843 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 844 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 845 846 if (REG(PREFETCH_SETTINS)) 847 REG_GET_2(PREFETCH_SETTINS, 848 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 849 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 850 else 851 REG_GET_2(PREFETCH_SETTINGS, 852 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 853 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 854 855 REG_GET_2(VBLANK_PARAMETERS_0, 856 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 857 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 858 859 REG_GET(REF_FREQ_TO_PIX_FREQ, 860 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 861 862 /* DLG - Per luma/chroma */ 863 REG_GET(VBLANK_PARAMETERS_1, 864 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 865 866 REG_GET(VBLANK_PARAMETERS_3, 867 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 868 869 if (REG(NOM_PARAMETERS_0)) 870 REG_GET(NOM_PARAMETERS_0, 871 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 872 873 if (REG(NOM_PARAMETERS_1)) 874 REG_GET(NOM_PARAMETERS_1, 875 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 876 877 REG_GET(NOM_PARAMETERS_4, 878 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 879 880 REG_GET(NOM_PARAMETERS_5, 881 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 882 883 REG_GET_2(PER_LINE_DELIVERY_PRE, 884 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 885 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 886 887 REG_GET_2(PER_LINE_DELIVERY, 888 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 889 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 890 891 if (REG(PREFETCH_SETTINS_C)) 892 REG_GET(PREFETCH_SETTINS_C, 893 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 894 else 895 REG_GET(PREFETCH_SETTINGS_C, 896 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 897 898 REG_GET(VBLANK_PARAMETERS_2, 899 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 900 901 REG_GET(VBLANK_PARAMETERS_4, 902 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 903 904 if (REG(NOM_PARAMETERS_2)) 905 REG_GET(NOM_PARAMETERS_2, 906 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 907 908 if (REG(NOM_PARAMETERS_3)) 909 REG_GET(NOM_PARAMETERS_3, 910 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 911 912 REG_GET(NOM_PARAMETERS_6, 913 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 914 915 REG_GET(NOM_PARAMETERS_7, 916 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 917 918 /* TTU - per hubp */ 919 REG_GET_2(DCN_TTU_QOS_WM, 920 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 921 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 922 923 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 924 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 925 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 926 927 /* TTU - per luma/chroma */ 928 /* Assumed surf0 is luma and 1 is chroma */ 929 930 REG_GET_3(DCN_SURF0_TTU_CNTL0, 931 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 932 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 933 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 934 935 REG_GET(DCN_SURF0_TTU_CNTL1, 936 REFCYC_PER_REQ_DELIVERY_PRE, 937 &ttu_attr->refcyc_per_req_delivery_pre_l); 938 939 REG_GET_3(DCN_SURF1_TTU_CNTL0, 940 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 941 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 942 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 943 944 REG_GET(DCN_SURF1_TTU_CNTL1, 945 REFCYC_PER_REQ_DELIVERY_PRE, 946 &ttu_attr->refcyc_per_req_delivery_pre_c); 947 948 /* Rest of hubp */ 949 REG_GET(DCSURF_SURFACE_CONFIG, 950 SURFACE_PIXEL_FORMAT, &s->pixel_format); 951 952 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 953 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 954 955 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 956 PRI_VIEWPORT_WIDTH, &s->viewport_width, 957 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 958 959 REG_GET_2(DCSURF_SURFACE_CONFIG, 960 ROTATION_ANGLE, &s->rotation_angle, 961 H_MIRROR_EN, &s->h_mirror_en); 962 963 REG_GET(DCSURF_TILING_CONFIG, 964 SW_MODE, &s->sw_mode); 965 966 REG_GET(DCSURF_SURFACE_CONTROL, 967 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 968 969 REG_GET_3(DCHUBP_CNTL, 970 HUBP_BLANK_EN, &s->blank_en, 971 HUBP_TTU_DISABLE, &s->ttu_disable, 972 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 973 974 REG_GET(DCN_GLOBAL_TTU_CNTL, 975 MIN_TTU_VBLANK, &s->min_ttu_vblank); 976 977 REG_GET_2(DCN_TTU_QOS_WM, 978 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 979 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 980 } 981 982 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 983 { 984 enum cursor_pitch hw_pitch; 985 986 switch (pitch) { 987 case 64: 988 hw_pitch = CURSOR_PITCH_64_PIXELS; 989 break; 990 case 128: 991 hw_pitch = CURSOR_PITCH_128_PIXELS; 992 break; 993 case 256: 994 hw_pitch = CURSOR_PITCH_256_PIXELS; 995 break; 996 default: 997 DC_ERR("Invalid cursor pitch of %d. " 998 "Only 64/128/256 is supported on DCN.\n", pitch); 999 hw_pitch = CURSOR_PITCH_64_PIXELS; 1000 break; 1001 } 1002 return hw_pitch; 1003 } 1004 1005 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1006 unsigned int cur_width, 1007 enum dc_cursor_color_format format) 1008 { 1009 enum cursor_lines_per_chunk line_per_chunk; 1010 1011 if (format == CURSOR_MODE_MONO) 1012 /* impl B. expansion in CUR Buffer reader */ 1013 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1014 else if (cur_width <= 32) 1015 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1016 else if (cur_width <= 64) 1017 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1018 else if (cur_width <= 128) 1019 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1020 else 1021 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1022 1023 return line_per_chunk; 1024 } 1025 1026 void hubp1_cursor_set_attributes( 1027 struct hubp *hubp, 1028 const struct dc_cursor_attributes *attr) 1029 { 1030 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1031 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1032 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1033 attr->width, attr->color_format); 1034 1035 hubp->curs_attr = *attr; 1036 1037 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1038 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1039 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1040 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1041 1042 REG_UPDATE_2(CURSOR_SIZE, 1043 CURSOR_WIDTH, attr->width, 1044 CURSOR_HEIGHT, attr->height); 1045 1046 REG_UPDATE_3(CURSOR_CONTROL, 1047 CURSOR_MODE, attr->color_format, 1048 CURSOR_PITCH, hw_pitch, 1049 CURSOR_LINES_PER_CHUNK, lpc); 1050 1051 REG_SET_2(CURSOR_SETTINS, 0, 1052 /* no shift of the cursor HDL schedule */ 1053 CURSOR0_DST_Y_OFFSET, 0, 1054 /* used to shift the cursor chunk request deadline */ 1055 CURSOR0_CHUNK_HDL_ADJUST, 3); 1056 } 1057 1058 void hubp1_cursor_set_position( 1059 struct hubp *hubp, 1060 const struct dc_cursor_position *pos, 1061 const struct dc_cursor_mi_param *param) 1062 { 1063 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1064 int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start; 1065 uint32_t cur_en = pos->enable ? 1 : 0; 1066 uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1067 1068 /* 1069 * Guard aganst cursor_set_position() from being called with invalid 1070 * attributes 1071 * 1072 * TODO: Look at combining cursor_set_position() and 1073 * cursor_set_attributes() into cursor_update() 1074 */ 1075 if (hubp->curs_attr.address.quad_part == 0) 1076 return; 1077 1078 dst_x_offset *= param->ref_clk_khz; 1079 dst_x_offset /= param->pixel_clk_khz; 1080 1081 ASSERT(param->h_scale_ratio.value); 1082 1083 if (param->h_scale_ratio.value) 1084 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1085 dc_fixpt_from_int(dst_x_offset), 1086 param->h_scale_ratio)); 1087 1088 if (src_x_offset >= (int)param->viewport_width) 1089 cur_en = 0; /* not visible beyond right edge*/ 1090 1091 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1092 cur_en = 0; /* not visible beyond left edge*/ 1093 1094 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1095 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1096 1097 REG_UPDATE(CURSOR_CONTROL, 1098 CURSOR_ENABLE, cur_en); 1099 1100 REG_SET_2(CURSOR_POSITION, 0, 1101 CURSOR_X_POSITION, pos->x, 1102 CURSOR_Y_POSITION, pos->y); 1103 1104 REG_SET_2(CURSOR_HOT_SPOT, 0, 1105 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1106 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1107 1108 REG_SET(CURSOR_DST_OFFSET, 0, 1109 CURSOR_DST_X_OFFSET, dst_x_offset); 1110 /* TODO Handle surface pixel formats other than 4:4:4 */ 1111 } 1112 1113 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1114 { 1115 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1116 uint32_t clk_enable = enable ? 1 : 0; 1117 1118 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1119 } 1120 1121 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1122 { 1123 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1124 1125 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1126 } 1127 1128 static const struct hubp_funcs dcn10_hubp_funcs = { 1129 .hubp_program_surface_flip_and_addr = 1130 hubp1_program_surface_flip_and_addr, 1131 .hubp_program_surface_config = 1132 hubp1_program_surface_config, 1133 .hubp_is_flip_pending = hubp1_is_flip_pending, 1134 .hubp_setup = hubp1_setup, 1135 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1136 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1137 .set_blank = hubp1_set_blank, 1138 .dcc_control = hubp1_dcc_control, 1139 .mem_program_viewport = min_set_viewport, 1140 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1141 .set_cursor_attributes = hubp1_cursor_set_attributes, 1142 .set_cursor_position = hubp1_cursor_set_position, 1143 .hubp_disconnect = hubp1_disconnect, 1144 .hubp_clk_cntl = hubp1_clk_cntl, 1145 .hubp_vtg_sel = hubp1_vtg_sel, 1146 .hubp_read_state = hubp1_read_state, 1147 .hubp_disable_control = hubp1_disable_control, 1148 .hubp_get_underflow_status = hubp1_get_underflow_status, 1149 1150 }; 1151 1152 /*****************************************/ 1153 /* Constructor, Destructor */ 1154 /*****************************************/ 1155 1156 void dcn10_hubp_construct( 1157 struct dcn10_hubp *hubp1, 1158 struct dc_context *ctx, 1159 uint32_t inst, 1160 const struct dcn_mi_registers *hubp_regs, 1161 const struct dcn_mi_shift *hubp_shift, 1162 const struct dcn_mi_mask *hubp_mask) 1163 { 1164 hubp1->base.funcs = &dcn10_hubp_funcs; 1165 hubp1->base.ctx = ctx; 1166 hubp1->hubp_regs = hubp_regs; 1167 hubp1->hubp_shift = hubp_shift; 1168 hubp1->hubp_mask = hubp_mask; 1169 hubp1->base.inst = inst; 1170 hubp1->base.opp_id = 0xf; 1171 hubp1->base.mpcc_id = 0xf; 1172 } 1173 1174 1175