1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = 0xf; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 103 { 104 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 105 uint32_t blank_en = blank ? 1 : 0; 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 108 } 109 110 static void hubp1_vready_workaround(struct hubp *hubp, 111 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 112 { 113 uint32_t value = 0; 114 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 115 116 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 117 value = REG_READ(HUBPREQ_DEBUG_DB); 118 119 /* hack mode disable */ 120 value |= 0x100; 121 value &= ~0x1000; 122 123 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 124 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 125 /* if (eco_fix_needed(otg_global_sync_timing) 126 * set HBUBREQ_DEBUG_DB[12] = 1 */ 127 value |= 0x1000; 128 } 129 130 REG_WRITE(HUBPREQ_DEBUG_DB, value); 131 } 132 133 void hubp1_program_tiling( 134 struct hubp *hubp, 135 const union dc_tiling_info *info, 136 const enum surface_pixel_format pixel_format) 137 { 138 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 139 140 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 141 NUM_PIPES, log_2(info->gfx9.num_pipes), 142 NUM_BANKS, log_2(info->gfx9.num_banks), 143 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 144 NUM_SE, log_2(info->gfx9.num_shader_engines), 145 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 146 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 147 148 REG_UPDATE_4(DCSURF_TILING_CONFIG, 149 SW_MODE, info->gfx9.swizzle, 150 META_LINEAR, info->gfx9.meta_linear, 151 RB_ALIGNED, info->gfx9.rb_aligned, 152 PIPE_ALIGNED, info->gfx9.pipe_aligned); 153 } 154 155 void hubp1_program_size_and_rotation( 156 struct hubp *hubp, 157 enum dc_rotation_angle rotation, 158 enum surface_pixel_format format, 159 const union plane_size *plane_size, 160 struct dc_plane_dcc_param *dcc, 161 bool horizontal_mirror) 162 { 163 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 164 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror; 165 166 /* Program data and meta surface pitch (calculation from addrlib) 167 * 444 or 420 luma 168 */ 169 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 170 ASSERT(plane_size->video.chroma_pitch != 0); 171 /* Chroma pitch zero can cause system hang! */ 172 173 pitch = plane_size->video.luma_pitch - 1; 174 meta_pitch = dcc->video.meta_pitch_l - 1; 175 pitch_c = plane_size->video.chroma_pitch - 1; 176 meta_pitch_c = dcc->video.meta_pitch_c - 1; 177 } else { 178 pitch = plane_size->grph.surface_pitch - 1; 179 meta_pitch = dcc->grph.meta_pitch - 1; 180 pitch_c = 0; 181 meta_pitch_c = 0; 182 } 183 184 if (!dcc->enable) { 185 meta_pitch = 0; 186 meta_pitch_c = 0; 187 } 188 189 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 190 PITCH, pitch, META_PITCH, meta_pitch); 191 192 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 193 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 194 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 195 196 if (horizontal_mirror) 197 mirror = 1; 198 else 199 mirror = 0; 200 201 202 /* Program rotation angle and horz mirror - no mirror */ 203 if (rotation == ROTATION_ANGLE_0) 204 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 205 ROTATION_ANGLE, 0, 206 H_MIRROR_EN, mirror); 207 else if (rotation == ROTATION_ANGLE_90) 208 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 209 ROTATION_ANGLE, 1, 210 H_MIRROR_EN, mirror); 211 else if (rotation == ROTATION_ANGLE_180) 212 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 213 ROTATION_ANGLE, 2, 214 H_MIRROR_EN, mirror); 215 else if (rotation == ROTATION_ANGLE_270) 216 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 217 ROTATION_ANGLE, 3, 218 H_MIRROR_EN, mirror); 219 } 220 221 void hubp1_program_pixel_format( 222 struct hubp *hubp, 223 enum surface_pixel_format format) 224 { 225 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 226 uint32_t red_bar = 3; 227 uint32_t blue_bar = 2; 228 229 /* swap for ABGR format */ 230 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 231 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 232 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 233 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 234 red_bar = 2; 235 blue_bar = 3; 236 } 237 238 REG_UPDATE_2(HUBPRET_CONTROL, 239 CROSSBAR_SRC_CB_B, blue_bar, 240 CROSSBAR_SRC_CR_R, red_bar); 241 242 /* Mapping is same as ipp programming (cnvc) */ 243 244 switch (format) { 245 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 246 REG_UPDATE(DCSURF_SURFACE_CONFIG, 247 SURFACE_PIXEL_FORMAT, 1); 248 break; 249 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 250 REG_UPDATE(DCSURF_SURFACE_CONFIG, 251 SURFACE_PIXEL_FORMAT, 3); 252 break; 253 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 255 REG_UPDATE(DCSURF_SURFACE_CONFIG, 256 SURFACE_PIXEL_FORMAT, 8); 257 break; 258 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 259 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 260 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 261 REG_UPDATE(DCSURF_SURFACE_CONFIG, 262 SURFACE_PIXEL_FORMAT, 10); 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 265 REG_UPDATE(DCSURF_SURFACE_CONFIG, 266 SURFACE_PIXEL_FORMAT, 22); 267 break; 268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 270 REG_UPDATE(DCSURF_SURFACE_CONFIG, 271 SURFACE_PIXEL_FORMAT, 24); 272 break; 273 274 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 275 REG_UPDATE(DCSURF_SURFACE_CONFIG, 276 SURFACE_PIXEL_FORMAT, 65); 277 break; 278 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 279 REG_UPDATE(DCSURF_SURFACE_CONFIG, 280 SURFACE_PIXEL_FORMAT, 64); 281 break; 282 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 283 REG_UPDATE(DCSURF_SURFACE_CONFIG, 284 SURFACE_PIXEL_FORMAT, 67); 285 break; 286 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 287 REG_UPDATE(DCSURF_SURFACE_CONFIG, 288 SURFACE_PIXEL_FORMAT, 66); 289 break; 290 default: 291 BREAK_TO_DEBUGGER(); 292 break; 293 } 294 295 /* don't see the need of program the xbar in DCN 1.0 */ 296 } 297 298 bool hubp1_program_surface_flip_and_addr( 299 struct hubp *hubp, 300 const struct dc_plane_address *address, 301 bool flip_immediate) 302 { 303 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 304 305 /* program flip type */ 306 REG_SET(DCSURF_FLIP_CONTROL, 0, 307 SURFACE_FLIP_TYPE, flip_immediate); 308 309 /* HW automatically latch rest of address register on write to 310 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 311 * 312 * program high first and then the low addr, order matters! 313 */ 314 switch (address->type) { 315 case PLN_ADDR_TYPE_GRAPHICS: 316 /* DCN1.0 does not support const color 317 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 318 * base on address->grph.dcc_const_color 319 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 320 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 321 */ 322 323 if (address->grph.addr.quad_part == 0) 324 break; 325 326 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 327 PRIMARY_SURFACE_TMZ, address->tmz_surface, 328 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 329 330 if (address->grph.meta_addr.quad_part != 0) { 331 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 332 PRIMARY_META_SURFACE_ADDRESS_HIGH, 333 address->grph.meta_addr.high_part); 334 335 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 336 PRIMARY_META_SURFACE_ADDRESS, 337 address->grph.meta_addr.low_part); 338 } 339 340 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 341 PRIMARY_SURFACE_ADDRESS_HIGH, 342 address->grph.addr.high_part); 343 344 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 345 PRIMARY_SURFACE_ADDRESS, 346 address->grph.addr.low_part); 347 break; 348 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 349 if (address->video_progressive.luma_addr.quad_part == 0 350 || address->video_progressive.chroma_addr.quad_part == 0) 351 break; 352 353 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 354 PRIMARY_SURFACE_TMZ, address->tmz_surface, 355 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 356 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 357 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 358 359 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 360 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 361 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 362 address->video_progressive.chroma_meta_addr.high_part); 363 364 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 365 PRIMARY_META_SURFACE_ADDRESS_C, 366 address->video_progressive.chroma_meta_addr.low_part); 367 368 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 369 PRIMARY_META_SURFACE_ADDRESS_HIGH, 370 address->video_progressive.luma_meta_addr.high_part); 371 372 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 373 PRIMARY_META_SURFACE_ADDRESS, 374 address->video_progressive.luma_meta_addr.low_part); 375 } 376 377 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 378 PRIMARY_SURFACE_ADDRESS_HIGH_C, 379 address->video_progressive.chroma_addr.high_part); 380 381 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 382 PRIMARY_SURFACE_ADDRESS_C, 383 address->video_progressive.chroma_addr.low_part); 384 385 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 386 PRIMARY_SURFACE_ADDRESS_HIGH, 387 address->video_progressive.luma_addr.high_part); 388 389 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 390 PRIMARY_SURFACE_ADDRESS, 391 address->video_progressive.luma_addr.low_part); 392 break; 393 case PLN_ADDR_TYPE_GRPH_STEREO: 394 if (address->grph_stereo.left_addr.quad_part == 0) 395 break; 396 if (address->grph_stereo.right_addr.quad_part == 0) 397 break; 398 399 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 400 PRIMARY_SURFACE_TMZ, address->tmz_surface, 401 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 402 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 403 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 404 405 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 406 407 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 408 SECONDARY_META_SURFACE_ADDRESS_HIGH, 409 address->grph_stereo.right_meta_addr.high_part); 410 411 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 412 SECONDARY_META_SURFACE_ADDRESS, 413 address->grph_stereo.right_meta_addr.low_part); 414 } 415 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 416 417 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 418 PRIMARY_META_SURFACE_ADDRESS_HIGH, 419 address->grph_stereo.left_meta_addr.high_part); 420 421 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 422 PRIMARY_META_SURFACE_ADDRESS, 423 address->grph_stereo.left_meta_addr.low_part); 424 } 425 426 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 427 SECONDARY_SURFACE_ADDRESS_HIGH, 428 address->grph_stereo.right_addr.high_part); 429 430 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 431 SECONDARY_SURFACE_ADDRESS, 432 address->grph_stereo.right_addr.low_part); 433 434 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 435 PRIMARY_SURFACE_ADDRESS_HIGH, 436 address->grph_stereo.left_addr.high_part); 437 438 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 439 PRIMARY_SURFACE_ADDRESS, 440 address->grph_stereo.left_addr.low_part); 441 break; 442 default: 443 BREAK_TO_DEBUGGER(); 444 break; 445 } 446 447 hubp->request_address = *address; 448 449 if (flip_immediate) 450 hubp->current_address = *address; 451 452 return true; 453 } 454 455 void hubp1_dcc_control(struct hubp *hubp, bool enable, 456 bool independent_64b_blks) 457 { 458 uint32_t dcc_en = enable ? 1 : 0; 459 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 460 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 461 462 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 463 PRIMARY_SURFACE_DCC_EN, dcc_en, 464 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 465 } 466 467 void hubp1_program_surface_config( 468 struct hubp *hubp, 469 enum surface_pixel_format format, 470 union dc_tiling_info *tiling_info, 471 union plane_size *plane_size, 472 enum dc_rotation_angle rotation, 473 struct dc_plane_dcc_param *dcc, 474 bool horizontal_mirror) 475 { 476 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 477 hubp1_program_tiling(hubp, tiling_info, format); 478 hubp1_program_size_and_rotation( 479 hubp, rotation, format, plane_size, dcc, horizontal_mirror); 480 hubp1_program_pixel_format(hubp, format); 481 } 482 483 void hubp1_program_requestor( 484 struct hubp *hubp, 485 struct _vcs_dpi_display_rq_regs_st *rq_regs) 486 { 487 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 488 489 REG_UPDATE(HUBPRET_CONTROL, 490 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 491 REG_SET_4(DCN_EXPANSION_MODE, 0, 492 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 493 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 494 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 495 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 496 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 497 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 498 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 499 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 500 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 501 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 502 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 503 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 504 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 505 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 506 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 507 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 508 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 509 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 510 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 511 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 512 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 513 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 514 } 515 516 517 void hubp1_program_deadline( 518 struct hubp *hubp, 519 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 520 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 521 { 522 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 523 524 /* DLG - Per hubp */ 525 REG_SET_2(BLANK_OFFSET_0, 0, 526 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 527 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 528 529 REG_SET(BLANK_OFFSET_1, 0, 530 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 531 532 REG_SET(DST_DIMENSIONS, 0, 533 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 534 535 REG_SET_2(DST_AFTER_SCALER, 0, 536 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 537 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 538 539 if (REG(PREFETCH_SETTINS)) 540 REG_SET_2(PREFETCH_SETTINS, 0, 541 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 542 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 543 else 544 REG_SET_2(PREFETCH_SETTINGS, 0, 545 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 546 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 547 548 REG_SET_2(VBLANK_PARAMETERS_0, 0, 549 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 550 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 551 552 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 553 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 554 555 /* DLG - Per luma/chroma */ 556 REG_SET(VBLANK_PARAMETERS_1, 0, 557 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 558 559 REG_SET(VBLANK_PARAMETERS_3, 0, 560 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 561 562 if (REG(NOM_PARAMETERS_0)) 563 REG_SET(NOM_PARAMETERS_0, 0, 564 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 565 566 if (REG(NOM_PARAMETERS_1)) 567 REG_SET(NOM_PARAMETERS_1, 0, 568 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 569 570 REG_SET(NOM_PARAMETERS_4, 0, 571 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 572 573 REG_SET(NOM_PARAMETERS_5, 0, 574 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 575 576 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 577 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 578 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 579 580 REG_SET_2(PER_LINE_DELIVERY, 0, 581 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 582 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 583 584 if (REG(PREFETCH_SETTINS_C)) 585 REG_SET(PREFETCH_SETTINS_C, 0, 586 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 587 else 588 REG_SET(PREFETCH_SETTINGS_C, 0, 589 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 590 591 REG_SET(VBLANK_PARAMETERS_2, 0, 592 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 593 594 REG_SET(VBLANK_PARAMETERS_4, 0, 595 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 596 597 if (REG(NOM_PARAMETERS_2)) 598 REG_SET(NOM_PARAMETERS_2, 0, 599 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 600 601 if (REG(NOM_PARAMETERS_3)) 602 REG_SET(NOM_PARAMETERS_3, 0, 603 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 604 605 REG_SET(NOM_PARAMETERS_6, 0, 606 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 607 608 REG_SET(NOM_PARAMETERS_7, 0, 609 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 610 611 /* TTU - per hubp */ 612 REG_SET_2(DCN_TTU_QOS_WM, 0, 613 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 614 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 615 616 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 617 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 618 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 619 620 /* TTU - per luma/chroma */ 621 /* Assumed surf0 is luma and 1 is chroma */ 622 623 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 624 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 625 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 626 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 627 628 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 629 REFCYC_PER_REQ_DELIVERY_PRE, 630 ttu_attr->refcyc_per_req_delivery_pre_l); 631 632 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 633 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 634 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 635 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 636 637 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 638 REFCYC_PER_REQ_DELIVERY_PRE, 639 ttu_attr->refcyc_per_req_delivery_pre_c); 640 641 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 642 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 643 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 644 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 645 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 646 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 647 } 648 649 static void hubp1_setup( 650 struct hubp *hubp, 651 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 652 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 653 struct _vcs_dpi_display_rq_regs_st *rq_regs, 654 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 655 { 656 /* otg is locked when this func is called. Register are double buffered. 657 * disable the requestors is not needed 658 */ 659 hubp1_program_requestor(hubp, rq_regs); 660 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 661 hubp1_vready_workaround(hubp, pipe_dest); 662 } 663 664 bool hubp1_is_flip_pending(struct hubp *hubp) 665 { 666 uint32_t flip_pending = 0; 667 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 668 struct dc_plane_address earliest_inuse_address; 669 670 REG_GET(DCSURF_FLIP_CONTROL, 671 SURFACE_FLIP_PENDING, &flip_pending); 672 673 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 674 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 675 676 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 677 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 678 679 if (flip_pending) 680 return true; 681 682 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 683 return true; 684 685 hubp->current_address = hubp->request_address; 686 return false; 687 } 688 689 uint32_t aperture_default_system = 1; 690 uint32_t context0_default_system; /* = 0;*/ 691 692 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 693 struct vm_system_aperture_param *apt) 694 { 695 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 696 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 697 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 698 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 699 700 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 701 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 702 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 703 704 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 705 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 706 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 707 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 708 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 709 710 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 711 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 712 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 713 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 714 715 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 716 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 717 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 718 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 719 } 720 721 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 722 const struct vm_context0_param *vm0) 723 { 724 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 725 /* pte base */ 726 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 727 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 728 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 729 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 730 731 /* pte start */ 732 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 733 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 734 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 735 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 736 737 /* pte end */ 738 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 739 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 740 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 741 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 742 743 /* fault handling */ 744 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 745 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 746 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 747 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 748 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 749 750 /* control: enable VM PTE*/ 751 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 752 ENABLE_L1_TLB, 1, 753 SYSTEM_ACCESS_MODE, 3); 754 } 755 756 void min_set_viewport( 757 struct hubp *hubp, 758 const struct rect *viewport, 759 const struct rect *viewport_c) 760 { 761 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 762 763 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 764 PRI_VIEWPORT_WIDTH, viewport->width, 765 PRI_VIEWPORT_HEIGHT, viewport->height); 766 767 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 768 PRI_VIEWPORT_X_START, viewport->x, 769 PRI_VIEWPORT_Y_START, viewport->y); 770 771 /*for stereo*/ 772 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 773 SEC_VIEWPORT_WIDTH, viewport->width, 774 SEC_VIEWPORT_HEIGHT, viewport->height); 775 776 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 777 SEC_VIEWPORT_X_START, viewport->x, 778 SEC_VIEWPORT_Y_START, viewport->y); 779 780 /* DC supports NV12 only at the moment */ 781 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 782 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 783 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 784 785 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 786 PRI_VIEWPORT_X_START_C, viewport_c->x, 787 PRI_VIEWPORT_Y_START_C, viewport_c->y); 788 } 789 790 void hubp1_read_state(struct hubp *hubp) 791 { 792 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 793 struct dcn_hubp_state *s = &hubp1->state; 794 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 795 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 796 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 797 798 /* Requester */ 799 REG_GET(HUBPRET_CONTROL, 800 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 801 REG_GET_4(DCN_EXPANSION_MODE, 802 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 803 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 804 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 805 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 806 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 807 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 808 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 809 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 810 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 811 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 812 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 813 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 814 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 815 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 816 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 817 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 818 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 819 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 820 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 821 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 822 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 823 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 824 825 /* DLG - Per hubp */ 826 REG_GET_2(BLANK_OFFSET_0, 827 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 828 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 829 830 REG_GET(BLANK_OFFSET_1, 831 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 832 833 REG_GET(DST_DIMENSIONS, 834 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 835 836 REG_GET_2(DST_AFTER_SCALER, 837 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 838 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 839 840 if (REG(PREFETCH_SETTINS)) 841 REG_GET_2(PREFETCH_SETTINS, 842 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 843 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 844 else 845 REG_GET_2(PREFETCH_SETTINGS, 846 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 847 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 848 849 REG_GET_2(VBLANK_PARAMETERS_0, 850 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 851 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 852 853 REG_GET(REF_FREQ_TO_PIX_FREQ, 854 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 855 856 /* DLG - Per luma/chroma */ 857 REG_GET(VBLANK_PARAMETERS_1, 858 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 859 860 REG_GET(VBLANK_PARAMETERS_3, 861 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 862 863 if (REG(NOM_PARAMETERS_0)) 864 REG_GET(NOM_PARAMETERS_0, 865 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 866 867 if (REG(NOM_PARAMETERS_1)) 868 REG_GET(NOM_PARAMETERS_1, 869 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 870 871 REG_GET(NOM_PARAMETERS_4, 872 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 873 874 REG_GET(NOM_PARAMETERS_5, 875 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 876 877 REG_GET_2(PER_LINE_DELIVERY_PRE, 878 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 879 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 880 881 REG_GET_2(PER_LINE_DELIVERY, 882 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 883 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 884 885 if (REG(PREFETCH_SETTINS_C)) 886 REG_GET(PREFETCH_SETTINS_C, 887 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 888 else 889 REG_GET(PREFETCH_SETTINGS_C, 890 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 891 892 REG_GET(VBLANK_PARAMETERS_2, 893 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 894 895 REG_GET(VBLANK_PARAMETERS_4, 896 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 897 898 if (REG(NOM_PARAMETERS_2)) 899 REG_GET(NOM_PARAMETERS_2, 900 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 901 902 if (REG(NOM_PARAMETERS_3)) 903 REG_GET(NOM_PARAMETERS_3, 904 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 905 906 REG_GET(NOM_PARAMETERS_6, 907 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 908 909 REG_GET(NOM_PARAMETERS_7, 910 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 911 912 /* TTU - per hubp */ 913 REG_GET_2(DCN_TTU_QOS_WM, 914 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 915 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 916 917 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 918 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 919 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 920 921 /* TTU - per luma/chroma */ 922 /* Assumed surf0 is luma and 1 is chroma */ 923 924 REG_GET_3(DCN_SURF0_TTU_CNTL0, 925 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 926 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 927 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 928 929 REG_GET(DCN_SURF0_TTU_CNTL1, 930 REFCYC_PER_REQ_DELIVERY_PRE, 931 &ttu_attr->refcyc_per_req_delivery_pre_l); 932 933 REG_GET_3(DCN_SURF1_TTU_CNTL0, 934 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 935 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 936 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 937 938 REG_GET(DCN_SURF1_TTU_CNTL1, 939 REFCYC_PER_REQ_DELIVERY_PRE, 940 &ttu_attr->refcyc_per_req_delivery_pre_c); 941 942 /* Rest of hubp */ 943 REG_GET(DCSURF_SURFACE_CONFIG, 944 SURFACE_PIXEL_FORMAT, &s->pixel_format); 945 946 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 947 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 948 949 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 950 PRI_VIEWPORT_WIDTH, &s->viewport_width, 951 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 952 953 REG_GET_2(DCSURF_SURFACE_CONFIG, 954 ROTATION_ANGLE, &s->rotation_angle, 955 H_MIRROR_EN, &s->h_mirror_en); 956 957 REG_GET(DCSURF_TILING_CONFIG, 958 SW_MODE, &s->sw_mode); 959 960 REG_GET(DCSURF_SURFACE_CONTROL, 961 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 962 963 REG_GET_3(DCHUBP_CNTL, 964 HUBP_BLANK_EN, &s->blank_en, 965 HUBP_TTU_DISABLE, &s->ttu_disable, 966 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 967 968 REG_GET(DCN_GLOBAL_TTU_CNTL, 969 MIN_TTU_VBLANK, &s->min_ttu_vblank); 970 971 REG_GET_2(DCN_TTU_QOS_WM, 972 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 973 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 974 } 975 976 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 977 { 978 enum cursor_pitch hw_pitch; 979 980 switch (pitch) { 981 case 64: 982 hw_pitch = CURSOR_PITCH_64_PIXELS; 983 break; 984 case 128: 985 hw_pitch = CURSOR_PITCH_128_PIXELS; 986 break; 987 case 256: 988 hw_pitch = CURSOR_PITCH_256_PIXELS; 989 break; 990 default: 991 DC_ERR("Invalid cursor pitch of %d. " 992 "Only 64/128/256 is supported on DCN.\n", pitch); 993 hw_pitch = CURSOR_PITCH_64_PIXELS; 994 break; 995 } 996 return hw_pitch; 997 } 998 999 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1000 unsigned int cur_width, 1001 enum dc_cursor_color_format format) 1002 { 1003 enum cursor_lines_per_chunk line_per_chunk; 1004 1005 if (format == CURSOR_MODE_MONO) 1006 /* impl B. expansion in CUR Buffer reader */ 1007 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1008 else if (cur_width <= 32) 1009 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1010 else if (cur_width <= 64) 1011 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1012 else if (cur_width <= 128) 1013 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1014 else 1015 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1016 1017 return line_per_chunk; 1018 } 1019 1020 void hubp1_cursor_set_attributes( 1021 struct hubp *hubp, 1022 const struct dc_cursor_attributes *attr) 1023 { 1024 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1025 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1026 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1027 attr->width, attr->color_format); 1028 1029 hubp->curs_attr = *attr; 1030 1031 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1032 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1033 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1034 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1035 1036 REG_UPDATE_2(CURSOR_SIZE, 1037 CURSOR_WIDTH, attr->width, 1038 CURSOR_HEIGHT, attr->height); 1039 1040 REG_UPDATE_3(CURSOR_CONTROL, 1041 CURSOR_MODE, attr->color_format, 1042 CURSOR_PITCH, hw_pitch, 1043 CURSOR_LINES_PER_CHUNK, lpc); 1044 1045 REG_SET_2(CURSOR_SETTINS, 0, 1046 /* no shift of the cursor HDL schedule */ 1047 CURSOR0_DST_Y_OFFSET, 0, 1048 /* used to shift the cursor chunk request deadline */ 1049 CURSOR0_CHUNK_HDL_ADJUST, 3); 1050 } 1051 1052 void hubp1_cursor_set_position( 1053 struct hubp *hubp, 1054 const struct dc_cursor_position *pos, 1055 const struct dc_cursor_mi_param *param) 1056 { 1057 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1058 int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start; 1059 uint32_t cur_en = pos->enable ? 1 : 0; 1060 uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1061 1062 /* 1063 * Guard aganst cursor_set_position() from being called with invalid 1064 * attributes 1065 * 1066 * TODO: Look at combining cursor_set_position() and 1067 * cursor_set_attributes() into cursor_update() 1068 */ 1069 if (hubp->curs_attr.address.quad_part == 0) 1070 return; 1071 1072 dst_x_offset *= param->ref_clk_khz; 1073 dst_x_offset /= param->pixel_clk_khz; 1074 1075 ASSERT(param->h_scale_ratio.value); 1076 1077 if (param->h_scale_ratio.value) 1078 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1079 dc_fixpt_from_int(dst_x_offset), 1080 param->h_scale_ratio)); 1081 1082 if (src_x_offset >= (int)param->viewport_width) 1083 cur_en = 0; /* not visible beyond right edge*/ 1084 1085 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1086 cur_en = 0; /* not visible beyond left edge*/ 1087 1088 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1089 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1090 1091 REG_UPDATE(CURSOR_CONTROL, 1092 CURSOR_ENABLE, cur_en); 1093 1094 REG_SET_2(CURSOR_POSITION, 0, 1095 CURSOR_X_POSITION, pos->x, 1096 CURSOR_Y_POSITION, pos->y); 1097 1098 REG_SET_2(CURSOR_HOT_SPOT, 0, 1099 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1100 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1101 1102 REG_SET(CURSOR_DST_OFFSET, 0, 1103 CURSOR_DST_X_OFFSET, dst_x_offset); 1104 /* TODO Handle surface pixel formats other than 4:4:4 */ 1105 } 1106 1107 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1108 { 1109 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1110 uint32_t clk_enable = enable ? 1 : 0; 1111 1112 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1113 } 1114 1115 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1116 { 1117 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1118 1119 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1120 } 1121 1122 static struct hubp_funcs dcn10_hubp_funcs = { 1123 .hubp_program_surface_flip_and_addr = 1124 hubp1_program_surface_flip_and_addr, 1125 .hubp_program_surface_config = 1126 hubp1_program_surface_config, 1127 .hubp_is_flip_pending = hubp1_is_flip_pending, 1128 .hubp_setup = hubp1_setup, 1129 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1130 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1131 .set_blank = hubp1_set_blank, 1132 .dcc_control = hubp1_dcc_control, 1133 .mem_program_viewport = min_set_viewport, 1134 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1135 .set_cursor_attributes = hubp1_cursor_set_attributes, 1136 .set_cursor_position = hubp1_cursor_set_position, 1137 .hubp_disconnect = hubp1_disconnect, 1138 .hubp_clk_cntl = hubp1_clk_cntl, 1139 .hubp_vtg_sel = hubp1_vtg_sel, 1140 .hubp_read_state = hubp1_read_state, 1141 .hubp_disable_control = hubp1_disable_control, 1142 .hubp_get_underflow_status = hubp1_get_underflow_status, 1143 1144 }; 1145 1146 /*****************************************/ 1147 /* Constructor, Destructor */ 1148 /*****************************************/ 1149 1150 void dcn10_hubp_construct( 1151 struct dcn10_hubp *hubp1, 1152 struct dc_context *ctx, 1153 uint32_t inst, 1154 const struct dcn_mi_registers *hubp_regs, 1155 const struct dcn_mi_shift *hubp_shift, 1156 const struct dcn_mi_mask *hubp_mask) 1157 { 1158 hubp1->base.funcs = &dcn10_hubp_funcs; 1159 hubp1->base.ctx = ctx; 1160 hubp1->hubp_regs = hubp_regs; 1161 hubp1->hubp_shift = hubp_shift; 1162 hubp1->hubp_mask = hubp_mask; 1163 hubp1->base.inst = inst; 1164 hubp1->base.opp_id = 0xf; 1165 hubp1->base.mpcc_id = 0xf; 1166 } 1167 1168 1169