1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = OPP_ID_INVALID; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 103 void hubp1_clear_underflow(struct hubp *hubp) 104 { 105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108 } 109 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 111 { 112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113 uint32_t blank_en = blank ? 1 : 0; 114 115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 116 } 117 118 void hubp1_vready_workaround(struct hubp *hubp, 119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 120 { 121 uint32_t value = 0; 122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 123 124 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 125 value = REG_READ(HUBPREQ_DEBUG_DB); 126 127 /* hack mode disable */ 128 value |= 0x100; 129 value &= ~0x1000; 130 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 133 /* if (eco_fix_needed(otg_global_sync_timing) 134 * set HBUBREQ_DEBUG_DB[12] = 1 */ 135 value |= 0x1000; 136 } 137 138 REG_WRITE(HUBPREQ_DEBUG_DB, value); 139 } 140 141 void hubp1_program_tiling( 142 struct hubp *hubp, 143 const union dc_tiling_info *info, 144 const enum surface_pixel_format pixel_format) 145 { 146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 148 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 149 NUM_PIPES, log_2(info->gfx9.num_pipes), 150 NUM_BANKS, log_2(info->gfx9.num_banks), 151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 152 NUM_SE, log_2(info->gfx9.num_shader_engines), 153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 155 156 REG_UPDATE_4(DCSURF_TILING_CONFIG, 157 SW_MODE, info->gfx9.swizzle, 158 META_LINEAR, info->gfx9.meta_linear, 159 RB_ALIGNED, info->gfx9.rb_aligned, 160 PIPE_ALIGNED, info->gfx9.pipe_aligned); 161 } 162 163 void hubp1_program_size( 164 struct hubp *hubp, 165 enum surface_pixel_format format, 166 const struct plane_size *plane_size, 167 struct dc_plane_dcc_param *dcc) 168 { 169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 170 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 171 172 /* Program data and meta surface pitch (calculation from addrlib) 173 * 444 or 420 luma 174 */ 175 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 176 ASSERT(plane_size->chroma_pitch != 0); 177 /* Chroma pitch zero can cause system hang! */ 178 179 pitch = plane_size->surface_pitch - 1; 180 meta_pitch = dcc->meta_pitch - 1; 181 pitch_c = plane_size->chroma_pitch - 1; 182 meta_pitch_c = dcc->meta_pitch_c - 1; 183 } else { 184 pitch = plane_size->surface_pitch - 1; 185 meta_pitch = dcc->meta_pitch - 1; 186 pitch_c = 0; 187 meta_pitch_c = 0; 188 } 189 190 if (!dcc->enable) { 191 meta_pitch = 0; 192 meta_pitch_c = 0; 193 } 194 195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 196 PITCH, pitch, META_PITCH, meta_pitch); 197 198 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 200 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 201 } 202 203 void hubp1_program_rotation( 204 struct hubp *hubp, 205 enum dc_rotation_angle rotation, 206 bool horizontal_mirror) 207 { 208 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 209 uint32_t mirror; 210 211 212 if (horizontal_mirror) 213 mirror = 1; 214 else 215 mirror = 0; 216 217 /* Program rotation angle and horz mirror - no mirror */ 218 if (rotation == ROTATION_ANGLE_0) 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 220 ROTATION_ANGLE, 0, 221 H_MIRROR_EN, mirror); 222 else if (rotation == ROTATION_ANGLE_90) 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 224 ROTATION_ANGLE, 1, 225 H_MIRROR_EN, mirror); 226 else if (rotation == ROTATION_ANGLE_180) 227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 228 ROTATION_ANGLE, 2, 229 H_MIRROR_EN, mirror); 230 else if (rotation == ROTATION_ANGLE_270) 231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 232 ROTATION_ANGLE, 3, 233 H_MIRROR_EN, mirror); 234 } 235 236 void hubp1_program_pixel_format( 237 struct hubp *hubp, 238 enum surface_pixel_format format) 239 { 240 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 241 uint32_t red_bar = 3; 242 uint32_t blue_bar = 2; 243 244 /* swap for ABGR format */ 245 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 246 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 249 red_bar = 2; 250 blue_bar = 3; 251 } 252 253 REG_UPDATE_2(HUBPRET_CONTROL, 254 CROSSBAR_SRC_CB_B, blue_bar, 255 CROSSBAR_SRC_CR_R, red_bar); 256 257 /* Mapping is same as ipp programming (cnvc) */ 258 259 switch (format) { 260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 261 REG_UPDATE(DCSURF_SURFACE_CONFIG, 262 SURFACE_PIXEL_FORMAT, 1); 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 265 REG_UPDATE(DCSURF_SURFACE_CONFIG, 266 SURFACE_PIXEL_FORMAT, 3); 267 break; 268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 270 REG_UPDATE(DCSURF_SURFACE_CONFIG, 271 SURFACE_PIXEL_FORMAT, 8); 272 break; 273 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 274 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 276 REG_UPDATE(DCSURF_SURFACE_CONFIG, 277 SURFACE_PIXEL_FORMAT, 10); 278 break; 279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 280 REG_UPDATE(DCSURF_SURFACE_CONFIG, 281 SURFACE_PIXEL_FORMAT, 22); 282 break; 283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 284 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 285 REG_UPDATE(DCSURF_SURFACE_CONFIG, 286 SURFACE_PIXEL_FORMAT, 24); 287 break; 288 289 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 290 REG_UPDATE(DCSURF_SURFACE_CONFIG, 291 SURFACE_PIXEL_FORMAT, 65); 292 break; 293 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 294 REG_UPDATE(DCSURF_SURFACE_CONFIG, 295 SURFACE_PIXEL_FORMAT, 64); 296 break; 297 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 298 REG_UPDATE(DCSURF_SURFACE_CONFIG, 299 SURFACE_PIXEL_FORMAT, 67); 300 break; 301 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 302 REG_UPDATE(DCSURF_SURFACE_CONFIG, 303 SURFACE_PIXEL_FORMAT, 66); 304 break; 305 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 306 REG_UPDATE(DCSURF_SURFACE_CONFIG, 307 SURFACE_PIXEL_FORMAT, 12); 308 break; 309 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 310 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 311 REG_UPDATE(DCSURF_SURFACE_CONFIG, 312 SURFACE_PIXEL_FORMAT, 112); 313 break; 314 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 315 REG_UPDATE(DCSURF_SURFACE_CONFIG, 316 SURFACE_PIXEL_FORMAT, 113); 317 break; 318 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 319 REG_UPDATE(DCSURF_SURFACE_CONFIG, 320 SURFACE_PIXEL_FORMAT, 114); 321 break; 322 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 323 REG_UPDATE(DCSURF_SURFACE_CONFIG, 324 SURFACE_PIXEL_FORMAT, 118); 325 break; 326 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 327 REG_UPDATE(DCSURF_SURFACE_CONFIG, 328 SURFACE_PIXEL_FORMAT, 119); 329 break; 330 #endif 331 default: 332 BREAK_TO_DEBUGGER(); 333 break; 334 } 335 336 /* don't see the need of program the xbar in DCN 1.0 */ 337 } 338 339 bool hubp1_program_surface_flip_and_addr( 340 struct hubp *hubp, 341 const struct dc_plane_address *address, 342 bool flip_immediate) 343 { 344 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 345 346 347 //program flip type 348 REG_UPDATE(DCSURF_FLIP_CONTROL, 349 SURFACE_FLIP_TYPE, flip_immediate); 350 351 352 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 353 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 354 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 355 356 } else { 357 // turn off stereo if not in stereo 358 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 359 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 360 } 361 362 363 364 /* HW automatically latch rest of address register on write to 365 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 366 * 367 * program high first and then the low addr, order matters! 368 */ 369 switch (address->type) { 370 case PLN_ADDR_TYPE_GRAPHICS: 371 /* DCN1.0 does not support const color 372 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 373 * base on address->grph.dcc_const_color 374 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 375 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 376 */ 377 378 if (address->grph.addr.quad_part == 0) 379 break; 380 381 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 382 PRIMARY_SURFACE_TMZ, address->tmz_surface, 383 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 384 385 if (address->grph.meta_addr.quad_part != 0) { 386 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 387 PRIMARY_META_SURFACE_ADDRESS_HIGH, 388 address->grph.meta_addr.high_part); 389 390 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 391 PRIMARY_META_SURFACE_ADDRESS, 392 address->grph.meta_addr.low_part); 393 } 394 395 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 396 PRIMARY_SURFACE_ADDRESS_HIGH, 397 address->grph.addr.high_part); 398 399 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 400 PRIMARY_SURFACE_ADDRESS, 401 address->grph.addr.low_part); 402 break; 403 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 404 if (address->video_progressive.luma_addr.quad_part == 0 405 || address->video_progressive.chroma_addr.quad_part == 0) 406 break; 407 408 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 409 PRIMARY_SURFACE_TMZ, address->tmz_surface, 410 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 411 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 412 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 413 414 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 415 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 416 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 417 address->video_progressive.chroma_meta_addr.high_part); 418 419 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 420 PRIMARY_META_SURFACE_ADDRESS_C, 421 address->video_progressive.chroma_meta_addr.low_part); 422 423 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 424 PRIMARY_META_SURFACE_ADDRESS_HIGH, 425 address->video_progressive.luma_meta_addr.high_part); 426 427 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 428 PRIMARY_META_SURFACE_ADDRESS, 429 address->video_progressive.luma_meta_addr.low_part); 430 } 431 432 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 433 PRIMARY_SURFACE_ADDRESS_HIGH_C, 434 address->video_progressive.chroma_addr.high_part); 435 436 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 437 PRIMARY_SURFACE_ADDRESS_C, 438 address->video_progressive.chroma_addr.low_part); 439 440 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 441 PRIMARY_SURFACE_ADDRESS_HIGH, 442 address->video_progressive.luma_addr.high_part); 443 444 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 445 PRIMARY_SURFACE_ADDRESS, 446 address->video_progressive.luma_addr.low_part); 447 break; 448 case PLN_ADDR_TYPE_GRPH_STEREO: 449 if (address->grph_stereo.left_addr.quad_part == 0) 450 break; 451 if (address->grph_stereo.right_addr.quad_part == 0) 452 break; 453 454 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 455 PRIMARY_SURFACE_TMZ, address->tmz_surface, 456 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 457 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 458 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 459 SECONDARY_SURFACE_TMZ, address->tmz_surface, 460 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 461 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 462 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 463 464 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 465 466 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 467 SECONDARY_META_SURFACE_ADDRESS_HIGH, 468 address->grph_stereo.right_meta_addr.high_part); 469 470 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 471 SECONDARY_META_SURFACE_ADDRESS, 472 address->grph_stereo.right_meta_addr.low_part); 473 } 474 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 475 476 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 477 PRIMARY_META_SURFACE_ADDRESS_HIGH, 478 address->grph_stereo.left_meta_addr.high_part); 479 480 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 481 PRIMARY_META_SURFACE_ADDRESS, 482 address->grph_stereo.left_meta_addr.low_part); 483 } 484 485 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 486 SECONDARY_SURFACE_ADDRESS_HIGH, 487 address->grph_stereo.right_addr.high_part); 488 489 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 490 SECONDARY_SURFACE_ADDRESS, 491 address->grph_stereo.right_addr.low_part); 492 493 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 494 PRIMARY_SURFACE_ADDRESS_HIGH, 495 address->grph_stereo.left_addr.high_part); 496 497 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 498 PRIMARY_SURFACE_ADDRESS, 499 address->grph_stereo.left_addr.low_part); 500 break; 501 default: 502 BREAK_TO_DEBUGGER(); 503 break; 504 } 505 506 hubp->request_address = *address; 507 508 return true; 509 } 510 511 void hubp1_dcc_control(struct hubp *hubp, bool enable, 512 enum hubp_ind_block_size independent_64b_blks) 513 { 514 uint32_t dcc_en = enable ? 1 : 0; 515 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 516 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 517 518 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 519 PRIMARY_SURFACE_DCC_EN, dcc_en, 520 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 521 SECONDARY_SURFACE_DCC_EN, dcc_en, 522 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 523 } 524 525 void hubp1_program_surface_config( 526 struct hubp *hubp, 527 enum surface_pixel_format format, 528 union dc_tiling_info *tiling_info, 529 struct plane_size *plane_size, 530 enum dc_rotation_angle rotation, 531 struct dc_plane_dcc_param *dcc, 532 bool horizontal_mirror, 533 unsigned int compat_level) 534 { 535 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 536 hubp1_program_tiling(hubp, tiling_info, format); 537 hubp1_program_size(hubp, format, plane_size, dcc); 538 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 539 hubp1_program_pixel_format(hubp, format); 540 } 541 542 void hubp1_program_requestor( 543 struct hubp *hubp, 544 struct _vcs_dpi_display_rq_regs_st *rq_regs) 545 { 546 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 547 548 REG_UPDATE(HUBPRET_CONTROL, 549 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 550 REG_SET_4(DCN_EXPANSION_MODE, 0, 551 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 552 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 553 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 554 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 555 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 556 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 557 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 558 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 559 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 560 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 561 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 562 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 563 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 564 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 565 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 566 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 567 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 568 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 569 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 570 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 571 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 572 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 573 } 574 575 576 void hubp1_program_deadline( 577 struct hubp *hubp, 578 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 579 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 580 { 581 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 582 583 /* DLG - Per hubp */ 584 REG_SET_2(BLANK_OFFSET_0, 0, 585 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 586 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 587 588 REG_SET(BLANK_OFFSET_1, 0, 589 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 590 591 REG_SET(DST_DIMENSIONS, 0, 592 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 593 594 REG_SET_2(DST_AFTER_SCALER, 0, 595 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 596 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 597 598 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 599 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 600 601 /* DLG - Per luma/chroma */ 602 REG_SET(VBLANK_PARAMETERS_1, 0, 603 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 604 605 if (REG(NOM_PARAMETERS_0)) 606 REG_SET(NOM_PARAMETERS_0, 0, 607 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 608 609 if (REG(NOM_PARAMETERS_1)) 610 REG_SET(NOM_PARAMETERS_1, 0, 611 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 612 613 REG_SET(NOM_PARAMETERS_4, 0, 614 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 615 616 REG_SET(NOM_PARAMETERS_5, 0, 617 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 618 619 REG_SET_2(PER_LINE_DELIVERY, 0, 620 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 621 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 622 623 REG_SET(VBLANK_PARAMETERS_2, 0, 624 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 625 626 if (REG(NOM_PARAMETERS_2)) 627 REG_SET(NOM_PARAMETERS_2, 0, 628 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 629 630 if (REG(NOM_PARAMETERS_3)) 631 REG_SET(NOM_PARAMETERS_3, 0, 632 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 633 634 REG_SET(NOM_PARAMETERS_6, 0, 635 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 636 637 REG_SET(NOM_PARAMETERS_7, 0, 638 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 639 640 /* TTU - per hubp */ 641 REG_SET_2(DCN_TTU_QOS_WM, 0, 642 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 643 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 644 645 /* TTU - per luma/chroma */ 646 /* Assumed surf0 is luma and 1 is chroma */ 647 648 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 649 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 650 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 651 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 652 653 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 654 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 655 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 656 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 657 658 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 659 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 660 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 661 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 662 } 663 664 static void hubp1_setup( 665 struct hubp *hubp, 666 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 667 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 668 struct _vcs_dpi_display_rq_regs_st *rq_regs, 669 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 670 { 671 /* otg is locked when this func is called. Register are double buffered. 672 * disable the requestors is not needed 673 */ 674 hubp1_program_requestor(hubp, rq_regs); 675 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 676 hubp1_vready_workaround(hubp, pipe_dest); 677 } 678 679 static void hubp1_setup_interdependent( 680 struct hubp *hubp, 681 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 682 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 683 { 684 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 685 686 REG_SET_2(PREFETCH_SETTINS, 0, 687 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 688 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 689 690 REG_SET(PREFETCH_SETTINS_C, 0, 691 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 692 693 REG_SET_2(VBLANK_PARAMETERS_0, 0, 694 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 695 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 696 697 REG_SET(VBLANK_PARAMETERS_3, 0, 698 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 699 700 REG_SET(VBLANK_PARAMETERS_4, 0, 701 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 702 703 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 704 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 705 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 706 707 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 708 REFCYC_PER_REQ_DELIVERY_PRE, 709 ttu_attr->refcyc_per_req_delivery_pre_l); 710 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 711 REFCYC_PER_REQ_DELIVERY_PRE, 712 ttu_attr->refcyc_per_req_delivery_pre_c); 713 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 714 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 715 716 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 717 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 718 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 719 } 720 721 bool hubp1_is_flip_pending(struct hubp *hubp) 722 { 723 uint32_t flip_pending = 0; 724 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 725 struct dc_plane_address earliest_inuse_address; 726 727 REG_GET(DCSURF_FLIP_CONTROL, 728 SURFACE_FLIP_PENDING, &flip_pending); 729 730 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 731 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 732 733 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 734 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 735 736 if (flip_pending) 737 return true; 738 739 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 740 return true; 741 742 return false; 743 } 744 745 uint32_t aperture_default_system = 1; 746 uint32_t context0_default_system; /* = 0;*/ 747 748 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 749 struct vm_system_aperture_param *apt) 750 { 751 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 752 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 753 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 754 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 755 756 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 757 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 758 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 759 760 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 761 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 762 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 763 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 764 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 765 766 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 767 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 768 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 769 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 770 771 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 772 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 773 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 774 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 775 } 776 777 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 778 const struct vm_context0_param *vm0) 779 { 780 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 781 /* pte base */ 782 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 783 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 784 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 785 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 786 787 /* pte start */ 788 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 789 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 790 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 791 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 792 793 /* pte end */ 794 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 795 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 796 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 797 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 798 799 /* fault handling */ 800 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 801 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 802 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 803 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 804 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 805 806 /* control: enable VM PTE*/ 807 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 808 ENABLE_L1_TLB, 1, 809 SYSTEM_ACCESS_MODE, 3); 810 } 811 812 void min_set_viewport( 813 struct hubp *hubp, 814 const struct rect *viewport, 815 const struct rect *viewport_c) 816 { 817 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 818 819 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 820 PRI_VIEWPORT_WIDTH, viewport->width, 821 PRI_VIEWPORT_HEIGHT, viewport->height); 822 823 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 824 PRI_VIEWPORT_X_START, viewport->x, 825 PRI_VIEWPORT_Y_START, viewport->y); 826 827 /*for stereo*/ 828 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 829 SEC_VIEWPORT_WIDTH, viewport->width, 830 SEC_VIEWPORT_HEIGHT, viewport->height); 831 832 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 833 SEC_VIEWPORT_X_START, viewport->x, 834 SEC_VIEWPORT_Y_START, viewport->y); 835 836 /* DC supports NV12 only at the moment */ 837 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 838 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 839 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 840 841 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 842 PRI_VIEWPORT_X_START_C, viewport_c->x, 843 PRI_VIEWPORT_Y_START_C, viewport_c->y); 844 } 845 846 void hubp1_read_state_common(struct hubp *hubp) 847 { 848 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 849 struct dcn_hubp_state *s = &hubp1->state; 850 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 851 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 852 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 853 854 /* Requester */ 855 REG_GET(HUBPRET_CONTROL, 856 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 857 REG_GET_4(DCN_EXPANSION_MODE, 858 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 859 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 860 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 861 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 862 863 /* DLG - Per hubp */ 864 REG_GET_2(BLANK_OFFSET_0, 865 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 866 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 867 868 REG_GET(BLANK_OFFSET_1, 869 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 870 871 REG_GET(DST_DIMENSIONS, 872 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 873 874 REG_GET_2(DST_AFTER_SCALER, 875 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 876 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 877 878 if (REG(PREFETCH_SETTINS)) 879 REG_GET_2(PREFETCH_SETTINS, 880 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 881 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 882 else 883 REG_GET_2(PREFETCH_SETTINGS, 884 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 885 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 886 887 REG_GET_2(VBLANK_PARAMETERS_0, 888 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 889 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 890 891 REG_GET(REF_FREQ_TO_PIX_FREQ, 892 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 893 894 /* DLG - Per luma/chroma */ 895 REG_GET(VBLANK_PARAMETERS_1, 896 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 897 898 REG_GET(VBLANK_PARAMETERS_3, 899 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 900 901 if (REG(NOM_PARAMETERS_0)) 902 REG_GET(NOM_PARAMETERS_0, 903 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 904 905 if (REG(NOM_PARAMETERS_1)) 906 REG_GET(NOM_PARAMETERS_1, 907 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 908 909 REG_GET(NOM_PARAMETERS_4, 910 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 911 912 REG_GET(NOM_PARAMETERS_5, 913 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 914 915 REG_GET_2(PER_LINE_DELIVERY_PRE, 916 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 917 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 918 919 REG_GET_2(PER_LINE_DELIVERY, 920 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 921 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 922 923 if (REG(PREFETCH_SETTINS_C)) 924 REG_GET(PREFETCH_SETTINS_C, 925 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 926 else 927 REG_GET(PREFETCH_SETTINGS_C, 928 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 929 930 REG_GET(VBLANK_PARAMETERS_2, 931 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 932 933 REG_GET(VBLANK_PARAMETERS_4, 934 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 935 936 if (REG(NOM_PARAMETERS_2)) 937 REG_GET(NOM_PARAMETERS_2, 938 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 939 940 if (REG(NOM_PARAMETERS_3)) 941 REG_GET(NOM_PARAMETERS_3, 942 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 943 944 REG_GET(NOM_PARAMETERS_6, 945 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 946 947 REG_GET(NOM_PARAMETERS_7, 948 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 949 950 /* TTU - per hubp */ 951 REG_GET_2(DCN_TTU_QOS_WM, 952 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 953 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 954 955 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 956 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 957 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 958 959 /* TTU - per luma/chroma */ 960 /* Assumed surf0 is luma and 1 is chroma */ 961 962 REG_GET_3(DCN_SURF0_TTU_CNTL0, 963 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 964 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 965 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 966 967 REG_GET(DCN_SURF0_TTU_CNTL1, 968 REFCYC_PER_REQ_DELIVERY_PRE, 969 &ttu_attr->refcyc_per_req_delivery_pre_l); 970 971 REG_GET_3(DCN_SURF1_TTU_CNTL0, 972 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 973 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 974 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 975 976 REG_GET(DCN_SURF1_TTU_CNTL1, 977 REFCYC_PER_REQ_DELIVERY_PRE, 978 &ttu_attr->refcyc_per_req_delivery_pre_c); 979 980 /* Rest of hubp */ 981 REG_GET(DCSURF_SURFACE_CONFIG, 982 SURFACE_PIXEL_FORMAT, &s->pixel_format); 983 984 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 985 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 986 987 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 988 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 989 990 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 991 PRI_VIEWPORT_WIDTH, &s->viewport_width, 992 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 993 994 REG_GET_2(DCSURF_SURFACE_CONFIG, 995 ROTATION_ANGLE, &s->rotation_angle, 996 H_MIRROR_EN, &s->h_mirror_en); 997 998 REG_GET(DCSURF_TILING_CONFIG, 999 SW_MODE, &s->sw_mode); 1000 1001 REG_GET(DCSURF_SURFACE_CONTROL, 1002 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1003 1004 REG_GET_3(DCHUBP_CNTL, 1005 HUBP_BLANK_EN, &s->blank_en, 1006 HUBP_TTU_DISABLE, &s->ttu_disable, 1007 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1008 1009 REG_GET(DCN_GLOBAL_TTU_CNTL, 1010 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1011 1012 REG_GET_2(DCN_TTU_QOS_WM, 1013 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1014 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1015 1016 } 1017 1018 void hubp1_read_state(struct hubp *hubp) 1019 { 1020 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1021 struct dcn_hubp_state *s = &hubp1->state; 1022 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1023 1024 hubp1_read_state_common(hubp); 1025 1026 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1027 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1028 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1029 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1030 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1031 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1032 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1033 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1034 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1035 1036 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1037 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1038 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1039 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1040 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1041 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1042 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1043 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1044 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1045 1046 } 1047 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1048 { 1049 enum cursor_pitch hw_pitch; 1050 1051 switch (pitch) { 1052 case 64: 1053 hw_pitch = CURSOR_PITCH_64_PIXELS; 1054 break; 1055 case 128: 1056 hw_pitch = CURSOR_PITCH_128_PIXELS; 1057 break; 1058 case 256: 1059 hw_pitch = CURSOR_PITCH_256_PIXELS; 1060 break; 1061 default: 1062 DC_ERR("Invalid cursor pitch of %d. " 1063 "Only 64/128/256 is supported on DCN.\n", pitch); 1064 hw_pitch = CURSOR_PITCH_64_PIXELS; 1065 break; 1066 } 1067 return hw_pitch; 1068 } 1069 1070 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1071 unsigned int cur_width, 1072 enum dc_cursor_color_format format) 1073 { 1074 enum cursor_lines_per_chunk line_per_chunk; 1075 1076 if (format == CURSOR_MODE_MONO) 1077 /* impl B. expansion in CUR Buffer reader */ 1078 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1079 else if (cur_width <= 32) 1080 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1081 else if (cur_width <= 64) 1082 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1083 else if (cur_width <= 128) 1084 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1085 else 1086 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1087 1088 return line_per_chunk; 1089 } 1090 1091 void hubp1_cursor_set_attributes( 1092 struct hubp *hubp, 1093 const struct dc_cursor_attributes *attr) 1094 { 1095 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1096 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1097 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1098 attr->width, attr->color_format); 1099 1100 hubp->curs_attr = *attr; 1101 1102 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1103 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1104 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1105 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1106 1107 REG_UPDATE_2(CURSOR_SIZE, 1108 CURSOR_WIDTH, attr->width, 1109 CURSOR_HEIGHT, attr->height); 1110 1111 REG_UPDATE_3(CURSOR_CONTROL, 1112 CURSOR_MODE, attr->color_format, 1113 CURSOR_PITCH, hw_pitch, 1114 CURSOR_LINES_PER_CHUNK, lpc); 1115 1116 REG_SET_2(CURSOR_SETTINS, 0, 1117 /* no shift of the cursor HDL schedule */ 1118 CURSOR0_DST_Y_OFFSET, 0, 1119 /* used to shift the cursor chunk request deadline */ 1120 CURSOR0_CHUNK_HDL_ADJUST, 3); 1121 } 1122 1123 void hubp1_cursor_set_position( 1124 struct hubp *hubp, 1125 const struct dc_cursor_position *pos, 1126 const struct dc_cursor_mi_param *param) 1127 { 1128 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1129 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 1130 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 1131 int x_hotspot = pos->x_hotspot; 1132 int y_hotspot = pos->y_hotspot; 1133 uint32_t dst_x_offset; 1134 uint32_t cur_en = pos->enable ? 1 : 0; 1135 1136 /* 1137 * Guard aganst cursor_set_position() from being called with invalid 1138 * attributes 1139 * 1140 * TODO: Look at combining cursor_set_position() and 1141 * cursor_set_attributes() into cursor_update() 1142 */ 1143 if (hubp->curs_attr.address.quad_part == 0) 1144 return; 1145 1146 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1147 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 1148 y_hotspot = pos->x_hotspot; 1149 x_hotspot = pos->y_hotspot; 1150 } 1151 1152 if (param->mirror) { 1153 x_hotspot = param->viewport.width - x_hotspot; 1154 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1155 } 1156 1157 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1158 dst_x_offset *= param->ref_clk_khz; 1159 dst_x_offset /= param->pixel_clk_khz; 1160 1161 ASSERT(param->h_scale_ratio.value); 1162 1163 if (param->h_scale_ratio.value) 1164 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1165 dc_fixpt_from_int(dst_x_offset), 1166 param->h_scale_ratio)); 1167 1168 if (src_x_offset >= (int)param->viewport.width) 1169 cur_en = 0; /* not visible beyond right edge*/ 1170 1171 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1172 cur_en = 0; /* not visible beyond left edge*/ 1173 1174 if (src_y_offset >= (int)param->viewport.height) 1175 cur_en = 0; /* not visible beyond bottom edge*/ 1176 1177 if (src_y_offset + (int)hubp->curs_attr.height <= 0) 1178 cur_en = 0; /* not visible beyond top edge*/ 1179 1180 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1181 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1182 1183 REG_UPDATE(CURSOR_CONTROL, 1184 CURSOR_ENABLE, cur_en); 1185 1186 REG_SET_2(CURSOR_POSITION, 0, 1187 CURSOR_X_POSITION, pos->x, 1188 CURSOR_Y_POSITION, pos->y); 1189 1190 REG_SET_2(CURSOR_HOT_SPOT, 0, 1191 CURSOR_HOT_SPOT_X, x_hotspot, 1192 CURSOR_HOT_SPOT_Y, y_hotspot); 1193 1194 REG_SET(CURSOR_DST_OFFSET, 0, 1195 CURSOR_DST_X_OFFSET, dst_x_offset); 1196 /* TODO Handle surface pixel formats other than 4:4:4 */ 1197 } 1198 1199 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1200 { 1201 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1202 uint32_t clk_enable = enable ? 1 : 0; 1203 1204 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1205 } 1206 1207 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1208 { 1209 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1210 1211 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1212 } 1213 1214 void hubp1_init(struct hubp *hubp) 1215 { 1216 //do nothing 1217 } 1218 static const struct hubp_funcs dcn10_hubp_funcs = { 1219 .hubp_program_surface_flip_and_addr = 1220 hubp1_program_surface_flip_and_addr, 1221 .hubp_program_surface_config = 1222 hubp1_program_surface_config, 1223 .hubp_is_flip_pending = hubp1_is_flip_pending, 1224 .hubp_setup = hubp1_setup, 1225 .hubp_setup_interdependent = hubp1_setup_interdependent, 1226 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1227 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1228 .set_blank = hubp1_set_blank, 1229 .dcc_control = hubp1_dcc_control, 1230 .mem_program_viewport = min_set_viewport, 1231 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1232 .set_cursor_attributes = hubp1_cursor_set_attributes, 1233 .set_cursor_position = hubp1_cursor_set_position, 1234 .hubp_disconnect = hubp1_disconnect, 1235 .hubp_clk_cntl = hubp1_clk_cntl, 1236 .hubp_vtg_sel = hubp1_vtg_sel, 1237 .hubp_read_state = hubp1_read_state, 1238 .hubp_clear_underflow = hubp1_clear_underflow, 1239 .hubp_disable_control = hubp1_disable_control, 1240 .hubp_get_underflow_status = hubp1_get_underflow_status, 1241 .hubp_init = hubp1_init, 1242 1243 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 1244 .dmdata_set_attributes = NULL, 1245 .dmdata_load = NULL, 1246 #endif 1247 }; 1248 1249 /*****************************************/ 1250 /* Constructor, Destructor */ 1251 /*****************************************/ 1252 1253 void dcn10_hubp_construct( 1254 struct dcn10_hubp *hubp1, 1255 struct dc_context *ctx, 1256 uint32_t inst, 1257 const struct dcn_mi_registers *hubp_regs, 1258 const struct dcn_mi_shift *hubp_shift, 1259 const struct dcn_mi_mask *hubp_mask) 1260 { 1261 hubp1->base.funcs = &dcn10_hubp_funcs; 1262 hubp1->base.ctx = ctx; 1263 hubp1->hubp_regs = hubp_regs; 1264 hubp1->hubp_shift = hubp_shift; 1265 hubp1->hubp_mask = hubp_mask; 1266 hubp1->base.inst = inst; 1267 hubp1->base.opp_id = OPP_ID_INVALID; 1268 hubp1->base.mpcc_id = 0xf; 1269 } 1270 1271 1272