1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = OPP_ID_INVALID; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 103 void hubp1_clear_underflow(struct hubp *hubp) 104 { 105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108 } 109 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 111 { 112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113 uint32_t blank_en = blank ? 1 : 0; 114 115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 116 } 117 118 void hubp1_vready_workaround(struct hubp *hubp, 119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 120 { 121 uint32_t value = 0; 122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 123 124 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 125 value = REG_READ(HUBPREQ_DEBUG_DB); 126 127 /* hack mode disable */ 128 value |= 0x100; 129 value &= ~0x1000; 130 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 133 /* if (eco_fix_needed(otg_global_sync_timing) 134 * set HBUBREQ_DEBUG_DB[12] = 1 */ 135 value |= 0x1000; 136 } 137 138 REG_WRITE(HUBPREQ_DEBUG_DB, value); 139 } 140 141 void hubp1_program_tiling( 142 struct hubp *hubp, 143 const union dc_tiling_info *info, 144 const enum surface_pixel_format pixel_format) 145 { 146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 148 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 149 NUM_PIPES, log_2(info->gfx9.num_pipes), 150 NUM_BANKS, log_2(info->gfx9.num_banks), 151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 152 NUM_SE, log_2(info->gfx9.num_shader_engines), 153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 155 156 REG_UPDATE_4(DCSURF_TILING_CONFIG, 157 SW_MODE, info->gfx9.swizzle, 158 META_LINEAR, info->gfx9.meta_linear, 159 RB_ALIGNED, info->gfx9.rb_aligned, 160 PIPE_ALIGNED, info->gfx9.pipe_aligned); 161 } 162 163 void hubp1_program_size( 164 struct hubp *hubp, 165 enum surface_pixel_format format, 166 const struct plane_size *plane_size, 167 struct dc_plane_dcc_param *dcc) 168 { 169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 170 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 171 172 /* Program data and meta surface pitch (calculation from addrlib) 173 * 444 or 420 luma 174 */ 175 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 176 ASSERT(plane_size->chroma_pitch != 0); 177 /* Chroma pitch zero can cause system hang! */ 178 179 pitch = plane_size->surface_pitch - 1; 180 meta_pitch = dcc->meta_pitch - 1; 181 pitch_c = plane_size->chroma_pitch - 1; 182 meta_pitch_c = dcc->meta_pitch_c - 1; 183 } else { 184 pitch = plane_size->surface_pitch - 1; 185 meta_pitch = dcc->meta_pitch - 1; 186 pitch_c = 0; 187 meta_pitch_c = 0; 188 } 189 190 if (!dcc->enable) { 191 meta_pitch = 0; 192 meta_pitch_c = 0; 193 } 194 195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 196 PITCH, pitch, META_PITCH, meta_pitch); 197 198 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 200 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 201 } 202 203 void hubp1_program_rotation( 204 struct hubp *hubp, 205 enum dc_rotation_angle rotation, 206 bool horizontal_mirror) 207 { 208 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 209 uint32_t mirror; 210 211 212 if (horizontal_mirror) 213 mirror = 1; 214 else 215 mirror = 0; 216 217 /* Program rotation angle and horz mirror - no mirror */ 218 if (rotation == ROTATION_ANGLE_0) 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 220 ROTATION_ANGLE, 0, 221 H_MIRROR_EN, mirror); 222 else if (rotation == ROTATION_ANGLE_90) 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 224 ROTATION_ANGLE, 1, 225 H_MIRROR_EN, mirror); 226 else if (rotation == ROTATION_ANGLE_180) 227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 228 ROTATION_ANGLE, 2, 229 H_MIRROR_EN, mirror); 230 else if (rotation == ROTATION_ANGLE_270) 231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 232 ROTATION_ANGLE, 3, 233 H_MIRROR_EN, mirror); 234 } 235 236 void hubp1_program_pixel_format( 237 struct hubp *hubp, 238 enum surface_pixel_format format) 239 { 240 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 241 uint32_t red_bar = 3; 242 uint32_t blue_bar = 2; 243 244 /* swap for ABGR format */ 245 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 246 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 249 red_bar = 2; 250 blue_bar = 3; 251 } 252 253 REG_UPDATE_2(HUBPRET_CONTROL, 254 CROSSBAR_SRC_CB_B, blue_bar, 255 CROSSBAR_SRC_CR_R, red_bar); 256 257 /* Mapping is same as ipp programming (cnvc) */ 258 259 switch (format) { 260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 261 REG_UPDATE(DCSURF_SURFACE_CONFIG, 262 SURFACE_PIXEL_FORMAT, 1); 263 break; 264 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 265 REG_UPDATE(DCSURF_SURFACE_CONFIG, 266 SURFACE_PIXEL_FORMAT, 3); 267 break; 268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 270 REG_UPDATE(DCSURF_SURFACE_CONFIG, 271 SURFACE_PIXEL_FORMAT, 8); 272 break; 273 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 274 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 276 REG_UPDATE(DCSURF_SURFACE_CONFIG, 277 SURFACE_PIXEL_FORMAT, 10); 278 break; 279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 280 REG_UPDATE(DCSURF_SURFACE_CONFIG, 281 SURFACE_PIXEL_FORMAT, 22); 282 break; 283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 284 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 285 REG_UPDATE(DCSURF_SURFACE_CONFIG, 286 SURFACE_PIXEL_FORMAT, 24); 287 break; 288 289 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 290 REG_UPDATE(DCSURF_SURFACE_CONFIG, 291 SURFACE_PIXEL_FORMAT, 65); 292 break; 293 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 294 REG_UPDATE(DCSURF_SURFACE_CONFIG, 295 SURFACE_PIXEL_FORMAT, 64); 296 break; 297 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 298 REG_UPDATE(DCSURF_SURFACE_CONFIG, 299 SURFACE_PIXEL_FORMAT, 67); 300 break; 301 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 302 REG_UPDATE(DCSURF_SURFACE_CONFIG, 303 SURFACE_PIXEL_FORMAT, 66); 304 break; 305 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 306 REG_UPDATE(DCSURF_SURFACE_CONFIG, 307 SURFACE_PIXEL_FORMAT, 12); 308 break; 309 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 310 REG_UPDATE(DCSURF_SURFACE_CONFIG, 311 SURFACE_PIXEL_FORMAT, 112); 312 break; 313 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 314 REG_UPDATE(DCSURF_SURFACE_CONFIG, 315 SURFACE_PIXEL_FORMAT, 113); 316 break; 317 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 318 REG_UPDATE(DCSURF_SURFACE_CONFIG, 319 SURFACE_PIXEL_FORMAT, 114); 320 break; 321 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 322 REG_UPDATE(DCSURF_SURFACE_CONFIG, 323 SURFACE_PIXEL_FORMAT, 118); 324 break; 325 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 326 REG_UPDATE(DCSURF_SURFACE_CONFIG, 327 SURFACE_PIXEL_FORMAT, 119); 328 break; 329 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 330 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 331 SURFACE_PIXEL_FORMAT, 116, 332 ALPHA_PLANE_EN, 0); 333 break; 334 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 335 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 336 SURFACE_PIXEL_FORMAT, 116, 337 ALPHA_PLANE_EN, 1); 338 break; 339 default: 340 BREAK_TO_DEBUGGER(); 341 break; 342 } 343 344 /* don't see the need of program the xbar in DCN 1.0 */ 345 } 346 347 bool hubp1_program_surface_flip_and_addr( 348 struct hubp *hubp, 349 const struct dc_plane_address *address, 350 bool flip_immediate) 351 { 352 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 353 354 355 //program flip type 356 REG_UPDATE(DCSURF_FLIP_CONTROL, 357 SURFACE_FLIP_TYPE, flip_immediate); 358 359 360 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 361 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 362 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 363 364 } else { 365 // turn off stereo if not in stereo 366 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 367 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 368 } 369 370 371 372 /* HW automatically latch rest of address register on write to 373 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 374 * 375 * program high first and then the low addr, order matters! 376 */ 377 switch (address->type) { 378 case PLN_ADDR_TYPE_GRAPHICS: 379 /* DCN1.0 does not support const color 380 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 381 * base on address->grph.dcc_const_color 382 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 383 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 384 */ 385 386 if (address->grph.addr.quad_part == 0) 387 break; 388 389 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 390 PRIMARY_SURFACE_TMZ, address->tmz_surface, 391 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 392 393 if (address->grph.meta_addr.quad_part != 0) { 394 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 395 PRIMARY_META_SURFACE_ADDRESS_HIGH, 396 address->grph.meta_addr.high_part); 397 398 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 399 PRIMARY_META_SURFACE_ADDRESS, 400 address->grph.meta_addr.low_part); 401 } 402 403 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 404 PRIMARY_SURFACE_ADDRESS_HIGH, 405 address->grph.addr.high_part); 406 407 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 408 PRIMARY_SURFACE_ADDRESS, 409 address->grph.addr.low_part); 410 break; 411 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 412 if (address->video_progressive.luma_addr.quad_part == 0 413 || address->video_progressive.chroma_addr.quad_part == 0) 414 break; 415 416 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 417 PRIMARY_SURFACE_TMZ, address->tmz_surface, 418 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 419 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 420 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 421 422 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 423 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 424 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 425 address->video_progressive.chroma_meta_addr.high_part); 426 427 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 428 PRIMARY_META_SURFACE_ADDRESS_C, 429 address->video_progressive.chroma_meta_addr.low_part); 430 431 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 432 PRIMARY_META_SURFACE_ADDRESS_HIGH, 433 address->video_progressive.luma_meta_addr.high_part); 434 435 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 436 PRIMARY_META_SURFACE_ADDRESS, 437 address->video_progressive.luma_meta_addr.low_part); 438 } 439 440 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 441 PRIMARY_SURFACE_ADDRESS_HIGH_C, 442 address->video_progressive.chroma_addr.high_part); 443 444 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 445 PRIMARY_SURFACE_ADDRESS_C, 446 address->video_progressive.chroma_addr.low_part); 447 448 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 449 PRIMARY_SURFACE_ADDRESS_HIGH, 450 address->video_progressive.luma_addr.high_part); 451 452 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 453 PRIMARY_SURFACE_ADDRESS, 454 address->video_progressive.luma_addr.low_part); 455 break; 456 case PLN_ADDR_TYPE_GRPH_STEREO: 457 if (address->grph_stereo.left_addr.quad_part == 0) 458 break; 459 if (address->grph_stereo.right_addr.quad_part == 0) 460 break; 461 462 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 463 PRIMARY_SURFACE_TMZ, address->tmz_surface, 464 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 465 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 466 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 467 SECONDARY_SURFACE_TMZ, address->tmz_surface, 468 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 469 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 470 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 471 472 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 473 474 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 475 SECONDARY_META_SURFACE_ADDRESS_HIGH, 476 address->grph_stereo.right_meta_addr.high_part); 477 478 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 479 SECONDARY_META_SURFACE_ADDRESS, 480 address->grph_stereo.right_meta_addr.low_part); 481 } 482 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 483 484 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 485 PRIMARY_META_SURFACE_ADDRESS_HIGH, 486 address->grph_stereo.left_meta_addr.high_part); 487 488 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 489 PRIMARY_META_SURFACE_ADDRESS, 490 address->grph_stereo.left_meta_addr.low_part); 491 } 492 493 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 494 SECONDARY_SURFACE_ADDRESS_HIGH, 495 address->grph_stereo.right_addr.high_part); 496 497 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 498 SECONDARY_SURFACE_ADDRESS, 499 address->grph_stereo.right_addr.low_part); 500 501 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 502 PRIMARY_SURFACE_ADDRESS_HIGH, 503 address->grph_stereo.left_addr.high_part); 504 505 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 506 PRIMARY_SURFACE_ADDRESS, 507 address->grph_stereo.left_addr.low_part); 508 break; 509 default: 510 BREAK_TO_DEBUGGER(); 511 break; 512 } 513 514 hubp->request_address = *address; 515 516 return true; 517 } 518 519 void hubp1_dcc_control(struct hubp *hubp, bool enable, 520 enum hubp_ind_block_size independent_64b_blks) 521 { 522 uint32_t dcc_en = enable ? 1 : 0; 523 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 524 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 525 526 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 527 PRIMARY_SURFACE_DCC_EN, dcc_en, 528 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 529 SECONDARY_SURFACE_DCC_EN, dcc_en, 530 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 531 } 532 533 void hubp1_program_surface_config( 534 struct hubp *hubp, 535 enum surface_pixel_format format, 536 union dc_tiling_info *tiling_info, 537 struct plane_size *plane_size, 538 enum dc_rotation_angle rotation, 539 struct dc_plane_dcc_param *dcc, 540 bool horizontal_mirror, 541 unsigned int compat_level) 542 { 543 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 544 hubp1_program_tiling(hubp, tiling_info, format); 545 hubp1_program_size(hubp, format, plane_size, dcc); 546 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 547 hubp1_program_pixel_format(hubp, format); 548 } 549 550 void hubp1_program_requestor( 551 struct hubp *hubp, 552 struct _vcs_dpi_display_rq_regs_st *rq_regs) 553 { 554 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 555 556 REG_UPDATE(HUBPRET_CONTROL, 557 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 558 REG_SET_4(DCN_EXPANSION_MODE, 0, 559 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 560 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 561 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 562 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 563 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 564 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 565 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 566 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 567 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 568 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 569 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 570 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 571 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 572 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 573 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 574 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 575 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 576 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 577 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 578 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 579 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 580 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 581 } 582 583 584 void hubp1_program_deadline( 585 struct hubp *hubp, 586 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 587 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 588 { 589 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 590 591 /* DLG - Per hubp */ 592 REG_SET_2(BLANK_OFFSET_0, 0, 593 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 594 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 595 596 REG_SET(BLANK_OFFSET_1, 0, 597 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 598 599 REG_SET(DST_DIMENSIONS, 0, 600 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 601 602 REG_SET_2(DST_AFTER_SCALER, 0, 603 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 604 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 605 606 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 607 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 608 609 /* DLG - Per luma/chroma */ 610 REG_SET(VBLANK_PARAMETERS_1, 0, 611 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 612 613 if (REG(NOM_PARAMETERS_0)) 614 REG_SET(NOM_PARAMETERS_0, 0, 615 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 616 617 if (REG(NOM_PARAMETERS_1)) 618 REG_SET(NOM_PARAMETERS_1, 0, 619 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 620 621 REG_SET(NOM_PARAMETERS_4, 0, 622 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 623 624 REG_SET(NOM_PARAMETERS_5, 0, 625 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 626 627 REG_SET_2(PER_LINE_DELIVERY, 0, 628 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 629 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 630 631 REG_SET(VBLANK_PARAMETERS_2, 0, 632 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 633 634 if (REG(NOM_PARAMETERS_2)) 635 REG_SET(NOM_PARAMETERS_2, 0, 636 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 637 638 if (REG(NOM_PARAMETERS_3)) 639 REG_SET(NOM_PARAMETERS_3, 0, 640 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 641 642 REG_SET(NOM_PARAMETERS_6, 0, 643 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 644 645 REG_SET(NOM_PARAMETERS_7, 0, 646 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 647 648 /* TTU - per hubp */ 649 REG_SET_2(DCN_TTU_QOS_WM, 0, 650 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 651 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 652 653 /* TTU - per luma/chroma */ 654 /* Assumed surf0 is luma and 1 is chroma */ 655 656 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 657 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 658 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 659 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 660 661 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 662 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 663 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 664 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 665 666 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 667 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 668 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 669 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 670 } 671 672 static void hubp1_setup( 673 struct hubp *hubp, 674 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 675 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 676 struct _vcs_dpi_display_rq_regs_st *rq_regs, 677 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 678 { 679 /* otg is locked when this func is called. Register are double buffered. 680 * disable the requestors is not needed 681 */ 682 hubp1_program_requestor(hubp, rq_regs); 683 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 684 hubp1_vready_workaround(hubp, pipe_dest); 685 } 686 687 static void hubp1_setup_interdependent( 688 struct hubp *hubp, 689 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 690 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 691 { 692 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 693 694 REG_SET_2(PREFETCH_SETTINS, 0, 695 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 696 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 697 698 REG_SET(PREFETCH_SETTINS_C, 0, 699 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 700 701 REG_SET_2(VBLANK_PARAMETERS_0, 0, 702 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 703 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 704 705 REG_SET(VBLANK_PARAMETERS_3, 0, 706 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 707 708 REG_SET(VBLANK_PARAMETERS_4, 0, 709 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 710 711 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 712 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 713 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 714 715 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 716 REFCYC_PER_REQ_DELIVERY_PRE, 717 ttu_attr->refcyc_per_req_delivery_pre_l); 718 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 719 REFCYC_PER_REQ_DELIVERY_PRE, 720 ttu_attr->refcyc_per_req_delivery_pre_c); 721 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 722 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 723 724 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 725 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 726 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 727 } 728 729 bool hubp1_is_flip_pending(struct hubp *hubp) 730 { 731 uint32_t flip_pending = 0; 732 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 733 struct dc_plane_address earliest_inuse_address; 734 735 if (hubp && hubp->power_gated) 736 return false; 737 738 REG_GET(DCSURF_FLIP_CONTROL, 739 SURFACE_FLIP_PENDING, &flip_pending); 740 741 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 742 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 743 744 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 745 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 746 747 if (flip_pending) 748 return true; 749 750 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 751 return true; 752 753 return false; 754 } 755 756 uint32_t aperture_default_system = 1; 757 uint32_t context0_default_system; /* = 0;*/ 758 759 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 760 struct vm_system_aperture_param *apt) 761 { 762 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 763 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 764 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 765 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 766 767 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 768 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 769 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 770 771 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 772 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 773 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 774 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 775 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 776 777 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 778 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 779 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 780 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 781 782 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 783 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 784 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 785 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 786 } 787 788 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 789 const struct vm_context0_param *vm0) 790 { 791 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 792 /* pte base */ 793 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 794 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 795 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 796 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 797 798 /* pte start */ 799 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 800 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 801 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 802 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 803 804 /* pte end */ 805 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 806 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 807 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 808 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 809 810 /* fault handling */ 811 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 812 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 813 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 814 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 815 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 816 817 /* control: enable VM PTE*/ 818 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 819 ENABLE_L1_TLB, 1, 820 SYSTEM_ACCESS_MODE, 3); 821 } 822 823 void min_set_viewport( 824 struct hubp *hubp, 825 const struct rect *viewport, 826 const struct rect *viewport_c) 827 { 828 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 829 830 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 831 PRI_VIEWPORT_WIDTH, viewport->width, 832 PRI_VIEWPORT_HEIGHT, viewport->height); 833 834 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 835 PRI_VIEWPORT_X_START, viewport->x, 836 PRI_VIEWPORT_Y_START, viewport->y); 837 838 /*for stereo*/ 839 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 840 SEC_VIEWPORT_WIDTH, viewport->width, 841 SEC_VIEWPORT_HEIGHT, viewport->height); 842 843 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 844 SEC_VIEWPORT_X_START, viewport->x, 845 SEC_VIEWPORT_Y_START, viewport->y); 846 847 /* DC supports NV12 only at the moment */ 848 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 849 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 850 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 851 852 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 853 PRI_VIEWPORT_X_START_C, viewport_c->x, 854 PRI_VIEWPORT_Y_START_C, viewport_c->y); 855 856 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 857 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 858 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 859 860 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 861 SEC_VIEWPORT_X_START_C, viewport_c->x, 862 SEC_VIEWPORT_Y_START_C, viewport_c->y); 863 } 864 865 void hubp1_read_state_common(struct hubp *hubp) 866 { 867 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 868 struct dcn_hubp_state *s = &hubp1->state; 869 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 870 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 871 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 872 873 /* Requester */ 874 REG_GET(HUBPRET_CONTROL, 875 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 876 REG_GET_4(DCN_EXPANSION_MODE, 877 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 878 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 879 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 880 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 881 882 /* DLG - Per hubp */ 883 REG_GET_2(BLANK_OFFSET_0, 884 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 885 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 886 887 REG_GET(BLANK_OFFSET_1, 888 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 889 890 REG_GET(DST_DIMENSIONS, 891 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 892 893 REG_GET_2(DST_AFTER_SCALER, 894 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 895 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 896 897 if (REG(PREFETCH_SETTINS)) 898 REG_GET_2(PREFETCH_SETTINS, 899 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 900 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 901 else 902 REG_GET_2(PREFETCH_SETTINGS, 903 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 904 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 905 906 REG_GET_2(VBLANK_PARAMETERS_0, 907 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 908 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 909 910 REG_GET(REF_FREQ_TO_PIX_FREQ, 911 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 912 913 /* DLG - Per luma/chroma */ 914 REG_GET(VBLANK_PARAMETERS_1, 915 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 916 917 REG_GET(VBLANK_PARAMETERS_3, 918 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 919 920 if (REG(NOM_PARAMETERS_0)) 921 REG_GET(NOM_PARAMETERS_0, 922 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 923 924 if (REG(NOM_PARAMETERS_1)) 925 REG_GET(NOM_PARAMETERS_1, 926 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 927 928 REG_GET(NOM_PARAMETERS_4, 929 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 930 931 REG_GET(NOM_PARAMETERS_5, 932 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 933 934 REG_GET_2(PER_LINE_DELIVERY_PRE, 935 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 936 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 937 938 REG_GET_2(PER_LINE_DELIVERY, 939 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 940 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 941 942 if (REG(PREFETCH_SETTINS_C)) 943 REG_GET(PREFETCH_SETTINS_C, 944 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 945 else 946 REG_GET(PREFETCH_SETTINGS_C, 947 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 948 949 REG_GET(VBLANK_PARAMETERS_2, 950 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 951 952 REG_GET(VBLANK_PARAMETERS_4, 953 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 954 955 if (REG(NOM_PARAMETERS_2)) 956 REG_GET(NOM_PARAMETERS_2, 957 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 958 959 if (REG(NOM_PARAMETERS_3)) 960 REG_GET(NOM_PARAMETERS_3, 961 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 962 963 REG_GET(NOM_PARAMETERS_6, 964 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 965 966 REG_GET(NOM_PARAMETERS_7, 967 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 968 969 /* TTU - per hubp */ 970 REG_GET_2(DCN_TTU_QOS_WM, 971 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 972 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 973 974 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 975 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 976 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 977 978 /* TTU - per luma/chroma */ 979 /* Assumed surf0 is luma and 1 is chroma */ 980 981 REG_GET_3(DCN_SURF0_TTU_CNTL0, 982 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 983 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 984 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 985 986 REG_GET(DCN_SURF0_TTU_CNTL1, 987 REFCYC_PER_REQ_DELIVERY_PRE, 988 &ttu_attr->refcyc_per_req_delivery_pre_l); 989 990 REG_GET_3(DCN_SURF1_TTU_CNTL0, 991 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 992 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 993 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 994 995 REG_GET(DCN_SURF1_TTU_CNTL1, 996 REFCYC_PER_REQ_DELIVERY_PRE, 997 &ttu_attr->refcyc_per_req_delivery_pre_c); 998 999 /* Rest of hubp */ 1000 REG_GET(DCSURF_SURFACE_CONFIG, 1001 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1002 1003 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1004 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1005 1006 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1007 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1008 1009 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1010 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1011 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1012 1013 REG_GET_2(DCSURF_SURFACE_CONFIG, 1014 ROTATION_ANGLE, &s->rotation_angle, 1015 H_MIRROR_EN, &s->h_mirror_en); 1016 1017 REG_GET(DCSURF_TILING_CONFIG, 1018 SW_MODE, &s->sw_mode); 1019 1020 REG_GET(DCSURF_SURFACE_CONTROL, 1021 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1022 1023 REG_GET_3(DCHUBP_CNTL, 1024 HUBP_BLANK_EN, &s->blank_en, 1025 HUBP_TTU_DISABLE, &s->ttu_disable, 1026 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1027 1028 REG_GET(HUBP_CLK_CNTL, 1029 HUBP_CLOCK_ENABLE, &s->clock_en); 1030 1031 REG_GET(DCN_GLOBAL_TTU_CNTL, 1032 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1033 1034 REG_GET_2(DCN_TTU_QOS_WM, 1035 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1036 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1037 1038 } 1039 1040 void hubp1_read_state(struct hubp *hubp) 1041 { 1042 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1043 struct dcn_hubp_state *s = &hubp1->state; 1044 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1045 1046 hubp1_read_state_common(hubp); 1047 1048 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1049 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1050 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1051 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1052 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1053 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1054 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1055 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1056 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1057 1058 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1059 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1060 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1061 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1062 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1063 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1064 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1065 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1066 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1067 1068 } 1069 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1070 { 1071 enum cursor_pitch hw_pitch; 1072 1073 switch (pitch) { 1074 case 64: 1075 hw_pitch = CURSOR_PITCH_64_PIXELS; 1076 break; 1077 case 128: 1078 hw_pitch = CURSOR_PITCH_128_PIXELS; 1079 break; 1080 case 256: 1081 hw_pitch = CURSOR_PITCH_256_PIXELS; 1082 break; 1083 default: 1084 DC_ERR("Invalid cursor pitch of %d. " 1085 "Only 64/128/256 is supported on DCN.\n", pitch); 1086 hw_pitch = CURSOR_PITCH_64_PIXELS; 1087 break; 1088 } 1089 return hw_pitch; 1090 } 1091 1092 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1093 unsigned int cur_width, 1094 enum dc_cursor_color_format format) 1095 { 1096 enum cursor_lines_per_chunk line_per_chunk; 1097 1098 if (format == CURSOR_MODE_MONO) 1099 /* impl B. expansion in CUR Buffer reader */ 1100 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1101 else if (cur_width <= 32) 1102 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1103 else if (cur_width <= 64) 1104 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1105 else if (cur_width <= 128) 1106 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1107 else 1108 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1109 1110 return line_per_chunk; 1111 } 1112 1113 void hubp1_cursor_set_attributes( 1114 struct hubp *hubp, 1115 const struct dc_cursor_attributes *attr) 1116 { 1117 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1118 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1119 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1120 attr->width, attr->color_format); 1121 1122 hubp->curs_attr = *attr; 1123 1124 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1125 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1126 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1127 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1128 1129 REG_UPDATE_2(CURSOR_SIZE, 1130 CURSOR_WIDTH, attr->width, 1131 CURSOR_HEIGHT, attr->height); 1132 1133 REG_UPDATE_3(CURSOR_CONTROL, 1134 CURSOR_MODE, attr->color_format, 1135 CURSOR_PITCH, hw_pitch, 1136 CURSOR_LINES_PER_CHUNK, lpc); 1137 1138 REG_SET_2(CURSOR_SETTINS, 0, 1139 /* no shift of the cursor HDL schedule */ 1140 CURSOR0_DST_Y_OFFSET, 0, 1141 /* used to shift the cursor chunk request deadline */ 1142 CURSOR0_CHUNK_HDL_ADJUST, 3); 1143 } 1144 1145 void hubp1_cursor_set_position( 1146 struct hubp *hubp, 1147 const struct dc_cursor_position *pos, 1148 const struct dc_cursor_mi_param *param) 1149 { 1150 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1151 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 1152 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 1153 int x_hotspot = pos->x_hotspot; 1154 int y_hotspot = pos->y_hotspot; 1155 int cursor_height = (int)hubp->curs_attr.height; 1156 int cursor_width = (int)hubp->curs_attr.width; 1157 uint32_t dst_x_offset; 1158 uint32_t cur_en = pos->enable ? 1 : 0; 1159 1160 /* 1161 * Guard aganst cursor_set_position() from being called with invalid 1162 * attributes 1163 * 1164 * TODO: Look at combining cursor_set_position() and 1165 * cursor_set_attributes() into cursor_update() 1166 */ 1167 if (hubp->curs_attr.address.quad_part == 0) 1168 return; 1169 1170 // Rotated cursor width/height and hotspots tweaks for offset calculation 1171 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1172 swap(cursor_height, cursor_width); 1173 if (param->rotation == ROTATION_ANGLE_90) { 1174 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 1175 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 1176 } 1177 } else if (param->rotation == ROTATION_ANGLE_180) { 1178 src_x_offset = pos->x - param->viewport.x; 1179 src_y_offset = pos->y - param->viewport.y; 1180 } 1181 1182 if (param->mirror) { 1183 x_hotspot = param->viewport.width - x_hotspot; 1184 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1185 } 1186 1187 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1188 dst_x_offset *= param->ref_clk_khz; 1189 dst_x_offset /= param->pixel_clk_khz; 1190 1191 ASSERT(param->h_scale_ratio.value); 1192 1193 if (param->h_scale_ratio.value) 1194 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1195 dc_fixpt_from_int(dst_x_offset), 1196 param->h_scale_ratio)); 1197 1198 if (src_x_offset >= (int)param->viewport.width) 1199 cur_en = 0; /* not visible beyond right edge*/ 1200 1201 if (src_x_offset + cursor_width <= 0) 1202 cur_en = 0; /* not visible beyond left edge*/ 1203 1204 if (src_y_offset >= (int)param->viewport.height) 1205 cur_en = 0; /* not visible beyond bottom edge*/ 1206 1207 if (src_y_offset + cursor_height <= 0) 1208 cur_en = 0; /* not visible beyond top edge*/ 1209 1210 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1211 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1212 1213 REG_UPDATE(CURSOR_CONTROL, 1214 CURSOR_ENABLE, cur_en); 1215 1216 REG_SET_2(CURSOR_POSITION, 0, 1217 CURSOR_X_POSITION, pos->x, 1218 CURSOR_Y_POSITION, pos->y); 1219 1220 REG_SET_2(CURSOR_HOT_SPOT, 0, 1221 CURSOR_HOT_SPOT_X, x_hotspot, 1222 CURSOR_HOT_SPOT_Y, y_hotspot); 1223 1224 REG_SET(CURSOR_DST_OFFSET, 0, 1225 CURSOR_DST_X_OFFSET, dst_x_offset); 1226 /* TODO Handle surface pixel formats other than 4:4:4 */ 1227 } 1228 1229 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1230 { 1231 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1232 uint32_t clk_enable = enable ? 1 : 0; 1233 1234 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1235 } 1236 1237 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1238 { 1239 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1240 1241 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1242 } 1243 1244 bool hubp1_in_blank(struct hubp *hubp) 1245 { 1246 uint32_t in_blank; 1247 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1248 1249 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); 1250 return in_blank ? true : false; 1251 } 1252 1253 void hubp1_soft_reset(struct hubp *hubp, bool reset) 1254 { 1255 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1256 1257 REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); 1258 } 1259 1260 void hubp1_init(struct hubp *hubp) 1261 { 1262 //do nothing 1263 } 1264 static const struct hubp_funcs dcn10_hubp_funcs = { 1265 .hubp_program_surface_flip_and_addr = 1266 hubp1_program_surface_flip_and_addr, 1267 .hubp_program_surface_config = 1268 hubp1_program_surface_config, 1269 .hubp_is_flip_pending = hubp1_is_flip_pending, 1270 .hubp_setup = hubp1_setup, 1271 .hubp_setup_interdependent = hubp1_setup_interdependent, 1272 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1273 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1274 .set_blank = hubp1_set_blank, 1275 .dcc_control = hubp1_dcc_control, 1276 .mem_program_viewport = min_set_viewport, 1277 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1278 .set_cursor_attributes = hubp1_cursor_set_attributes, 1279 .set_cursor_position = hubp1_cursor_set_position, 1280 .hubp_disconnect = hubp1_disconnect, 1281 .hubp_clk_cntl = hubp1_clk_cntl, 1282 .hubp_vtg_sel = hubp1_vtg_sel, 1283 .hubp_read_state = hubp1_read_state, 1284 .hubp_clear_underflow = hubp1_clear_underflow, 1285 .hubp_disable_control = hubp1_disable_control, 1286 .hubp_get_underflow_status = hubp1_get_underflow_status, 1287 .hubp_init = hubp1_init, 1288 1289 .dmdata_set_attributes = NULL, 1290 .dmdata_load = NULL, 1291 .hubp_soft_reset = hubp1_soft_reset, 1292 .hubp_in_blank = hubp1_in_blank, 1293 }; 1294 1295 /*****************************************/ 1296 /* Constructor, Destructor */ 1297 /*****************************************/ 1298 1299 void dcn10_hubp_construct( 1300 struct dcn10_hubp *hubp1, 1301 struct dc_context *ctx, 1302 uint32_t inst, 1303 const struct dcn_mi_registers *hubp_regs, 1304 const struct dcn_mi_shift *hubp_shift, 1305 const struct dcn_mi_mask *hubp_mask) 1306 { 1307 hubp1->base.funcs = &dcn10_hubp_funcs; 1308 hubp1->base.ctx = ctx; 1309 hubp1->hubp_regs = hubp_regs; 1310 hubp1->hubp_shift = hubp_shift; 1311 hubp1->hubp_mask = hubp_mask; 1312 hubp1->base.inst = inst; 1313 hubp1->base.opp_id = OPP_ID_INVALID; 1314 hubp1->base.mpcc_id = 0xf; 1315 } 1316 1317 1318