1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = 0xf; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 103 { 104 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 105 uint32_t blank_en = blank ? 1 : 0; 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 108 } 109 110 static void hubp1_vready_workaround(struct hubp *hubp, 111 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 112 { 113 uint32_t value = 0; 114 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 115 116 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 117 value = REG_READ(HUBPREQ_DEBUG_DB); 118 119 /* hack mode disable */ 120 value |= 0x100; 121 value &= ~0x1000; 122 123 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 124 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 125 /* if (eco_fix_needed(otg_global_sync_timing) 126 * set HBUBREQ_DEBUG_DB[12] = 1 */ 127 value |= 0x1000; 128 } 129 130 REG_WRITE(HUBPREQ_DEBUG_DB, value); 131 } 132 133 void hubp1_program_tiling( 134 struct hubp *hubp, 135 const union dc_tiling_info *info, 136 const enum surface_pixel_format pixel_format) 137 { 138 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 139 140 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 141 NUM_PIPES, log_2(info->gfx9.num_pipes), 142 NUM_BANKS, log_2(info->gfx9.num_banks), 143 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 144 NUM_SE, log_2(info->gfx9.num_shader_engines), 145 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 146 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 147 148 REG_UPDATE_4(DCSURF_TILING_CONFIG, 149 SW_MODE, info->gfx9.swizzle, 150 META_LINEAR, info->gfx9.meta_linear, 151 RB_ALIGNED, info->gfx9.rb_aligned, 152 PIPE_ALIGNED, info->gfx9.pipe_aligned); 153 } 154 155 void hubp1_program_size( 156 struct hubp *hubp, 157 enum surface_pixel_format format, 158 const union plane_size *plane_size, 159 struct dc_plane_dcc_param *dcc) 160 { 161 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 162 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 163 164 /* Program data and meta surface pitch (calculation from addrlib) 165 * 444 or 420 luma 166 */ 167 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 168 ASSERT(plane_size->video.chroma_pitch != 0); 169 /* Chroma pitch zero can cause system hang! */ 170 171 pitch = plane_size->video.luma_pitch - 1; 172 meta_pitch = dcc->video.meta_pitch_l - 1; 173 pitch_c = plane_size->video.chroma_pitch - 1; 174 meta_pitch_c = dcc->video.meta_pitch_c - 1; 175 } else { 176 pitch = plane_size->grph.surface_pitch - 1; 177 meta_pitch = dcc->grph.meta_pitch - 1; 178 pitch_c = 0; 179 meta_pitch_c = 0; 180 } 181 182 if (!dcc->enable) { 183 meta_pitch = 0; 184 meta_pitch_c = 0; 185 } 186 187 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 188 PITCH, pitch, META_PITCH, meta_pitch); 189 190 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 191 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 192 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 193 } 194 195 void hubp1_program_rotation( 196 struct hubp *hubp, 197 enum dc_rotation_angle rotation, 198 bool horizontal_mirror) 199 { 200 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 201 uint32_t mirror; 202 203 204 if (horizontal_mirror) 205 mirror = 1; 206 else 207 mirror = 0; 208 209 /* Program rotation angle and horz mirror - no mirror */ 210 if (rotation == ROTATION_ANGLE_0) 211 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 212 ROTATION_ANGLE, 0, 213 H_MIRROR_EN, mirror); 214 else if (rotation == ROTATION_ANGLE_90) 215 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 216 ROTATION_ANGLE, 1, 217 H_MIRROR_EN, mirror); 218 else if (rotation == ROTATION_ANGLE_180) 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 220 ROTATION_ANGLE, 2, 221 H_MIRROR_EN, mirror); 222 else if (rotation == ROTATION_ANGLE_270) 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 224 ROTATION_ANGLE, 3, 225 H_MIRROR_EN, mirror); 226 } 227 228 void hubp1_program_pixel_format( 229 struct hubp *hubp, 230 enum surface_pixel_format format) 231 { 232 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 233 uint32_t red_bar = 3; 234 uint32_t blue_bar = 2; 235 236 /* swap for ABGR format */ 237 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 238 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 239 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 240 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 241 red_bar = 2; 242 blue_bar = 3; 243 } 244 245 REG_UPDATE_2(HUBPRET_CONTROL, 246 CROSSBAR_SRC_CB_B, blue_bar, 247 CROSSBAR_SRC_CR_R, red_bar); 248 249 /* Mapping is same as ipp programming (cnvc) */ 250 251 switch (format) { 252 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 253 REG_UPDATE(DCSURF_SURFACE_CONFIG, 254 SURFACE_PIXEL_FORMAT, 1); 255 break; 256 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 257 REG_UPDATE(DCSURF_SURFACE_CONFIG, 258 SURFACE_PIXEL_FORMAT, 3); 259 break; 260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 261 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 262 REG_UPDATE(DCSURF_SURFACE_CONFIG, 263 SURFACE_PIXEL_FORMAT, 8); 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 268 REG_UPDATE(DCSURF_SURFACE_CONFIG, 269 SURFACE_PIXEL_FORMAT, 10); 270 break; 271 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 272 REG_UPDATE(DCSURF_SURFACE_CONFIG, 273 SURFACE_PIXEL_FORMAT, 22); 274 break; 275 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 277 REG_UPDATE(DCSURF_SURFACE_CONFIG, 278 SURFACE_PIXEL_FORMAT, 24); 279 break; 280 281 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 282 REG_UPDATE(DCSURF_SURFACE_CONFIG, 283 SURFACE_PIXEL_FORMAT, 65); 284 break; 285 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 286 REG_UPDATE(DCSURF_SURFACE_CONFIG, 287 SURFACE_PIXEL_FORMAT, 64); 288 break; 289 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 290 REG_UPDATE(DCSURF_SURFACE_CONFIG, 291 SURFACE_PIXEL_FORMAT, 67); 292 break; 293 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 294 REG_UPDATE(DCSURF_SURFACE_CONFIG, 295 SURFACE_PIXEL_FORMAT, 66); 296 break; 297 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 298 REG_UPDATE(DCSURF_SURFACE_CONFIG, 299 SURFACE_PIXEL_FORMAT, 12); 300 break; 301 default: 302 BREAK_TO_DEBUGGER(); 303 break; 304 } 305 306 /* don't see the need of program the xbar in DCN 1.0 */ 307 } 308 309 bool hubp1_program_surface_flip_and_addr( 310 struct hubp *hubp, 311 const struct dc_plane_address *address, 312 bool flip_immediate) 313 { 314 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 315 316 317 //program flip type 318 REG_UPDATE(DCSURF_FLIP_CONTROL, 319 SURFACE_FLIP_TYPE, flip_immediate); 320 321 322 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 323 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 324 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 325 326 } else { 327 // turn off stereo if not in stereo 328 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 329 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 330 } 331 332 333 334 /* HW automatically latch rest of address register on write to 335 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 336 * 337 * program high first and then the low addr, order matters! 338 */ 339 switch (address->type) { 340 case PLN_ADDR_TYPE_GRAPHICS: 341 /* DCN1.0 does not support const color 342 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 343 * base on address->grph.dcc_const_color 344 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 345 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 346 */ 347 348 if (address->grph.addr.quad_part == 0) 349 break; 350 351 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 352 PRIMARY_SURFACE_TMZ, address->tmz_surface, 353 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 354 355 if (address->grph.meta_addr.quad_part != 0) { 356 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 357 PRIMARY_META_SURFACE_ADDRESS_HIGH, 358 address->grph.meta_addr.high_part); 359 360 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 361 PRIMARY_META_SURFACE_ADDRESS, 362 address->grph.meta_addr.low_part); 363 } 364 365 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 366 PRIMARY_SURFACE_ADDRESS_HIGH, 367 address->grph.addr.high_part); 368 369 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 370 PRIMARY_SURFACE_ADDRESS, 371 address->grph.addr.low_part); 372 break; 373 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 374 if (address->video_progressive.luma_addr.quad_part == 0 375 || address->video_progressive.chroma_addr.quad_part == 0) 376 break; 377 378 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 379 PRIMARY_SURFACE_TMZ, address->tmz_surface, 380 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 381 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 382 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 383 384 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 385 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 386 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 387 address->video_progressive.chroma_meta_addr.high_part); 388 389 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 390 PRIMARY_META_SURFACE_ADDRESS_C, 391 address->video_progressive.chroma_meta_addr.low_part); 392 393 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 394 PRIMARY_META_SURFACE_ADDRESS_HIGH, 395 address->video_progressive.luma_meta_addr.high_part); 396 397 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 398 PRIMARY_META_SURFACE_ADDRESS, 399 address->video_progressive.luma_meta_addr.low_part); 400 } 401 402 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 403 PRIMARY_SURFACE_ADDRESS_HIGH_C, 404 address->video_progressive.chroma_addr.high_part); 405 406 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 407 PRIMARY_SURFACE_ADDRESS_C, 408 address->video_progressive.chroma_addr.low_part); 409 410 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 411 PRIMARY_SURFACE_ADDRESS_HIGH, 412 address->video_progressive.luma_addr.high_part); 413 414 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 415 PRIMARY_SURFACE_ADDRESS, 416 address->video_progressive.luma_addr.low_part); 417 break; 418 case PLN_ADDR_TYPE_GRPH_STEREO: 419 if (address->grph_stereo.left_addr.quad_part == 0) 420 break; 421 if (address->grph_stereo.right_addr.quad_part == 0) 422 break; 423 424 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 425 PRIMARY_SURFACE_TMZ, address->tmz_surface, 426 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 427 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 428 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 429 SECONDARY_SURFACE_TMZ, address->tmz_surface, 430 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 431 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 432 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 433 434 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 435 436 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 437 SECONDARY_META_SURFACE_ADDRESS_HIGH, 438 address->grph_stereo.right_meta_addr.high_part); 439 440 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 441 SECONDARY_META_SURFACE_ADDRESS, 442 address->grph_stereo.right_meta_addr.low_part); 443 } 444 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 445 446 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 447 PRIMARY_META_SURFACE_ADDRESS_HIGH, 448 address->grph_stereo.left_meta_addr.high_part); 449 450 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 451 PRIMARY_META_SURFACE_ADDRESS, 452 address->grph_stereo.left_meta_addr.low_part); 453 } 454 455 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 456 SECONDARY_SURFACE_ADDRESS_HIGH, 457 address->grph_stereo.right_addr.high_part); 458 459 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 460 SECONDARY_SURFACE_ADDRESS, 461 address->grph_stereo.right_addr.low_part); 462 463 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 464 PRIMARY_SURFACE_ADDRESS_HIGH, 465 address->grph_stereo.left_addr.high_part); 466 467 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 468 PRIMARY_SURFACE_ADDRESS, 469 address->grph_stereo.left_addr.low_part); 470 break; 471 default: 472 BREAK_TO_DEBUGGER(); 473 break; 474 } 475 476 hubp->request_address = *address; 477 478 return true; 479 } 480 481 void hubp1_dcc_control(struct hubp *hubp, bool enable, 482 bool independent_64b_blks) 483 { 484 uint32_t dcc_en = enable ? 1 : 0; 485 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 486 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 487 488 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 489 PRIMARY_SURFACE_DCC_EN, dcc_en, 490 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 491 SECONDARY_SURFACE_DCC_EN, dcc_en, 492 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 493 } 494 495 void hubp1_program_surface_config( 496 struct hubp *hubp, 497 enum surface_pixel_format format, 498 union dc_tiling_info *tiling_info, 499 union plane_size *plane_size, 500 enum dc_rotation_angle rotation, 501 struct dc_plane_dcc_param *dcc, 502 bool horizontal_mirror, 503 unsigned int compat_level) 504 { 505 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 506 hubp1_program_tiling(hubp, tiling_info, format); 507 hubp1_program_size(hubp, format, plane_size, dcc); 508 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 509 hubp1_program_pixel_format(hubp, format); 510 } 511 512 void hubp1_program_requestor( 513 struct hubp *hubp, 514 struct _vcs_dpi_display_rq_regs_st *rq_regs) 515 { 516 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 517 518 REG_UPDATE(HUBPRET_CONTROL, 519 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 520 REG_SET_4(DCN_EXPANSION_MODE, 0, 521 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 522 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 523 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 524 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 525 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 526 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 527 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 528 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 529 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 530 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 531 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 532 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 533 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 534 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 535 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 536 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 537 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 538 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 539 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 540 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 541 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 542 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 543 } 544 545 546 void hubp1_program_deadline( 547 struct hubp *hubp, 548 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 549 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 550 { 551 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 552 553 /* DLG - Per hubp */ 554 REG_SET_2(BLANK_OFFSET_0, 0, 555 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 556 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 557 558 REG_SET(BLANK_OFFSET_1, 0, 559 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 560 561 REG_SET(DST_DIMENSIONS, 0, 562 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 563 564 REG_SET_2(DST_AFTER_SCALER, 0, 565 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 566 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 567 568 if (REG(PREFETCH_SETTINS)) 569 REG_SET_2(PREFETCH_SETTINS, 0, 570 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 571 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 572 else 573 REG_SET_2(PREFETCH_SETTINGS, 0, 574 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 575 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 576 577 REG_SET_2(VBLANK_PARAMETERS_0, 0, 578 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 579 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 580 581 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 582 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 583 584 /* DLG - Per luma/chroma */ 585 REG_SET(VBLANK_PARAMETERS_1, 0, 586 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 587 588 REG_SET(VBLANK_PARAMETERS_3, 0, 589 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 590 591 if (REG(NOM_PARAMETERS_0)) 592 REG_SET(NOM_PARAMETERS_0, 0, 593 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 594 595 if (REG(NOM_PARAMETERS_1)) 596 REG_SET(NOM_PARAMETERS_1, 0, 597 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 598 599 REG_SET(NOM_PARAMETERS_4, 0, 600 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 601 602 REG_SET(NOM_PARAMETERS_5, 0, 603 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 604 605 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 606 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 607 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 608 609 REG_SET_2(PER_LINE_DELIVERY, 0, 610 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 611 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 612 613 if (REG(PREFETCH_SETTINS_C)) 614 REG_SET(PREFETCH_SETTINS_C, 0, 615 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 616 else 617 REG_SET(PREFETCH_SETTINGS_C, 0, 618 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 619 620 REG_SET(VBLANK_PARAMETERS_2, 0, 621 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 622 623 REG_SET(VBLANK_PARAMETERS_4, 0, 624 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 625 626 if (REG(NOM_PARAMETERS_2)) 627 REG_SET(NOM_PARAMETERS_2, 0, 628 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 629 630 if (REG(NOM_PARAMETERS_3)) 631 REG_SET(NOM_PARAMETERS_3, 0, 632 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 633 634 REG_SET(NOM_PARAMETERS_6, 0, 635 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 636 637 REG_SET(NOM_PARAMETERS_7, 0, 638 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 639 640 /* TTU - per hubp */ 641 REG_SET_2(DCN_TTU_QOS_WM, 0, 642 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 643 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 644 645 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 646 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 647 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 648 649 /* TTU - per luma/chroma */ 650 /* Assumed surf0 is luma and 1 is chroma */ 651 652 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 653 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 654 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 655 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 656 657 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 658 REFCYC_PER_REQ_DELIVERY_PRE, 659 ttu_attr->refcyc_per_req_delivery_pre_l); 660 661 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 662 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 663 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 664 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 665 666 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 667 REFCYC_PER_REQ_DELIVERY_PRE, 668 ttu_attr->refcyc_per_req_delivery_pre_c); 669 670 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 671 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 672 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 673 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 674 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 675 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 676 } 677 678 static void hubp1_setup( 679 struct hubp *hubp, 680 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 681 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 682 struct _vcs_dpi_display_rq_regs_st *rq_regs, 683 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 684 { 685 /* otg is locked when this func is called. Register are double buffered. 686 * disable the requestors is not needed 687 */ 688 hubp1_program_requestor(hubp, rq_regs); 689 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 690 hubp1_vready_workaround(hubp, pipe_dest); 691 } 692 693 bool hubp1_is_flip_pending(struct hubp *hubp) 694 { 695 uint32_t flip_pending = 0; 696 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 697 struct dc_plane_address earliest_inuse_address; 698 699 REG_GET(DCSURF_FLIP_CONTROL, 700 SURFACE_FLIP_PENDING, &flip_pending); 701 702 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 703 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 704 705 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 706 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 707 708 if (flip_pending) 709 return true; 710 711 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 712 return true; 713 714 return false; 715 } 716 717 uint32_t aperture_default_system = 1; 718 uint32_t context0_default_system; /* = 0;*/ 719 720 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 721 struct vm_system_aperture_param *apt) 722 { 723 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 724 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 725 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 726 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 727 728 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 729 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 730 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 731 732 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 733 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 734 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 735 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 736 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 737 738 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 739 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 740 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 741 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 742 743 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 744 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 745 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 746 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 747 } 748 749 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 750 const struct vm_context0_param *vm0) 751 { 752 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 753 /* pte base */ 754 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 755 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 756 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 757 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 758 759 /* pte start */ 760 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 761 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 762 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 763 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 764 765 /* pte end */ 766 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 767 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 768 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 769 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 770 771 /* fault handling */ 772 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 773 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 774 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 775 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 776 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 777 778 /* control: enable VM PTE*/ 779 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 780 ENABLE_L1_TLB, 1, 781 SYSTEM_ACCESS_MODE, 3); 782 } 783 784 void min_set_viewport( 785 struct hubp *hubp, 786 const struct rect *viewport, 787 const struct rect *viewport_c) 788 { 789 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 790 791 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 792 PRI_VIEWPORT_WIDTH, viewport->width, 793 PRI_VIEWPORT_HEIGHT, viewport->height); 794 795 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 796 PRI_VIEWPORT_X_START, viewport->x, 797 PRI_VIEWPORT_Y_START, viewport->y); 798 799 /*for stereo*/ 800 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 801 SEC_VIEWPORT_WIDTH, viewport->width, 802 SEC_VIEWPORT_HEIGHT, viewport->height); 803 804 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 805 SEC_VIEWPORT_X_START, viewport->x, 806 SEC_VIEWPORT_Y_START, viewport->y); 807 808 /* DC supports NV12 only at the moment */ 809 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 810 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 811 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 812 813 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 814 PRI_VIEWPORT_X_START_C, viewport_c->x, 815 PRI_VIEWPORT_Y_START_C, viewport_c->y); 816 } 817 818 void hubp1_read_state(struct hubp *hubp) 819 { 820 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 821 struct dcn_hubp_state *s = &hubp1->state; 822 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 823 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 824 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 825 826 /* Requester */ 827 REG_GET(HUBPRET_CONTROL, 828 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 829 REG_GET_4(DCN_EXPANSION_MODE, 830 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 831 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 832 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 833 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 834 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 835 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 836 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 837 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 838 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 839 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 840 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 841 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 842 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 843 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 844 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 845 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 846 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 847 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 848 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 849 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 850 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 851 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 852 853 /* DLG - Per hubp */ 854 REG_GET_2(BLANK_OFFSET_0, 855 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 856 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 857 858 REG_GET(BLANK_OFFSET_1, 859 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 860 861 REG_GET(DST_DIMENSIONS, 862 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 863 864 REG_GET_2(DST_AFTER_SCALER, 865 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 866 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 867 868 if (REG(PREFETCH_SETTINS)) 869 REG_GET_2(PREFETCH_SETTINS, 870 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 871 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 872 else 873 REG_GET_2(PREFETCH_SETTINGS, 874 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 875 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 876 877 REG_GET_2(VBLANK_PARAMETERS_0, 878 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 879 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 880 881 REG_GET(REF_FREQ_TO_PIX_FREQ, 882 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 883 884 /* DLG - Per luma/chroma */ 885 REG_GET(VBLANK_PARAMETERS_1, 886 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 887 888 REG_GET(VBLANK_PARAMETERS_3, 889 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 890 891 if (REG(NOM_PARAMETERS_0)) 892 REG_GET(NOM_PARAMETERS_0, 893 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 894 895 if (REG(NOM_PARAMETERS_1)) 896 REG_GET(NOM_PARAMETERS_1, 897 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 898 899 REG_GET(NOM_PARAMETERS_4, 900 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 901 902 REG_GET(NOM_PARAMETERS_5, 903 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 904 905 REG_GET_2(PER_LINE_DELIVERY_PRE, 906 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 907 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 908 909 REG_GET_2(PER_LINE_DELIVERY, 910 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 911 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 912 913 if (REG(PREFETCH_SETTINS_C)) 914 REG_GET(PREFETCH_SETTINS_C, 915 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 916 else 917 REG_GET(PREFETCH_SETTINGS_C, 918 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 919 920 REG_GET(VBLANK_PARAMETERS_2, 921 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 922 923 REG_GET(VBLANK_PARAMETERS_4, 924 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 925 926 if (REG(NOM_PARAMETERS_2)) 927 REG_GET(NOM_PARAMETERS_2, 928 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 929 930 if (REG(NOM_PARAMETERS_3)) 931 REG_GET(NOM_PARAMETERS_3, 932 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 933 934 REG_GET(NOM_PARAMETERS_6, 935 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 936 937 REG_GET(NOM_PARAMETERS_7, 938 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 939 940 /* TTU - per hubp */ 941 REG_GET_2(DCN_TTU_QOS_WM, 942 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 943 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 944 945 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 946 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 947 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 948 949 /* TTU - per luma/chroma */ 950 /* Assumed surf0 is luma and 1 is chroma */ 951 952 REG_GET_3(DCN_SURF0_TTU_CNTL0, 953 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 954 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 955 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 956 957 REG_GET(DCN_SURF0_TTU_CNTL1, 958 REFCYC_PER_REQ_DELIVERY_PRE, 959 &ttu_attr->refcyc_per_req_delivery_pre_l); 960 961 REG_GET_3(DCN_SURF1_TTU_CNTL0, 962 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 963 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 964 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 965 966 REG_GET(DCN_SURF1_TTU_CNTL1, 967 REFCYC_PER_REQ_DELIVERY_PRE, 968 &ttu_attr->refcyc_per_req_delivery_pre_c); 969 970 /* Rest of hubp */ 971 REG_GET(DCSURF_SURFACE_CONFIG, 972 SURFACE_PIXEL_FORMAT, &s->pixel_format); 973 974 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 975 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 976 977 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 978 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 979 980 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 981 PRI_VIEWPORT_WIDTH, &s->viewport_width, 982 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 983 984 REG_GET_2(DCSURF_SURFACE_CONFIG, 985 ROTATION_ANGLE, &s->rotation_angle, 986 H_MIRROR_EN, &s->h_mirror_en); 987 988 REG_GET(DCSURF_TILING_CONFIG, 989 SW_MODE, &s->sw_mode); 990 991 REG_GET(DCSURF_SURFACE_CONTROL, 992 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 993 994 REG_GET_3(DCHUBP_CNTL, 995 HUBP_BLANK_EN, &s->blank_en, 996 HUBP_TTU_DISABLE, &s->ttu_disable, 997 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 998 999 REG_GET(DCN_GLOBAL_TTU_CNTL, 1000 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1001 1002 REG_GET_2(DCN_TTU_QOS_WM, 1003 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1004 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1005 } 1006 1007 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1008 { 1009 enum cursor_pitch hw_pitch; 1010 1011 switch (pitch) { 1012 case 64: 1013 hw_pitch = CURSOR_PITCH_64_PIXELS; 1014 break; 1015 case 128: 1016 hw_pitch = CURSOR_PITCH_128_PIXELS; 1017 break; 1018 case 256: 1019 hw_pitch = CURSOR_PITCH_256_PIXELS; 1020 break; 1021 default: 1022 DC_ERR("Invalid cursor pitch of %d. " 1023 "Only 64/128/256 is supported on DCN.\n", pitch); 1024 hw_pitch = CURSOR_PITCH_64_PIXELS; 1025 break; 1026 } 1027 return hw_pitch; 1028 } 1029 1030 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1031 unsigned int cur_width, 1032 enum dc_cursor_color_format format) 1033 { 1034 enum cursor_lines_per_chunk line_per_chunk; 1035 1036 if (format == CURSOR_MODE_MONO) 1037 /* impl B. expansion in CUR Buffer reader */ 1038 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1039 else if (cur_width <= 32) 1040 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1041 else if (cur_width <= 64) 1042 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1043 else if (cur_width <= 128) 1044 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1045 else 1046 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1047 1048 return line_per_chunk; 1049 } 1050 1051 void hubp1_cursor_set_attributes( 1052 struct hubp *hubp, 1053 const struct dc_cursor_attributes *attr) 1054 { 1055 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1056 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1057 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1058 attr->width, attr->color_format); 1059 1060 hubp->curs_attr = *attr; 1061 1062 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1063 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1064 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1065 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1066 1067 REG_UPDATE_2(CURSOR_SIZE, 1068 CURSOR_WIDTH, attr->width, 1069 CURSOR_HEIGHT, attr->height); 1070 1071 REG_UPDATE_3(CURSOR_CONTROL, 1072 CURSOR_MODE, attr->color_format, 1073 CURSOR_PITCH, hw_pitch, 1074 CURSOR_LINES_PER_CHUNK, lpc); 1075 1076 REG_SET_2(CURSOR_SETTINS, 0, 1077 /* no shift of the cursor HDL schedule */ 1078 CURSOR0_DST_Y_OFFSET, 0, 1079 /* used to shift the cursor chunk request deadline */ 1080 CURSOR0_CHUNK_HDL_ADJUST, 3); 1081 } 1082 1083 void hubp1_cursor_set_position( 1084 struct hubp *hubp, 1085 const struct dc_cursor_position *pos, 1086 const struct dc_cursor_mi_param *param) 1087 { 1088 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1089 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 1090 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 1091 int x_hotspot = pos->x_hotspot; 1092 int y_hotspot = pos->y_hotspot; 1093 uint32_t dst_x_offset; 1094 uint32_t cur_en = pos->enable ? 1 : 0; 1095 1096 /* 1097 * Guard aganst cursor_set_position() from being called with invalid 1098 * attributes 1099 * 1100 * TODO: Look at combining cursor_set_position() and 1101 * cursor_set_attributes() into cursor_update() 1102 */ 1103 if (hubp->curs_attr.address.quad_part == 0) 1104 return; 1105 1106 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1107 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 1108 y_hotspot = pos->x_hotspot; 1109 x_hotspot = pos->y_hotspot; 1110 } 1111 1112 if (param->mirror) { 1113 x_hotspot = param->viewport.width - x_hotspot; 1114 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1115 } 1116 1117 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1118 dst_x_offset *= param->ref_clk_khz; 1119 dst_x_offset /= param->pixel_clk_khz; 1120 1121 ASSERT(param->h_scale_ratio.value); 1122 1123 if (param->h_scale_ratio.value) 1124 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1125 dc_fixpt_from_int(dst_x_offset), 1126 param->h_scale_ratio)); 1127 1128 if (src_x_offset >= (int)param->viewport.width) 1129 cur_en = 0; /* not visible beyond right edge*/ 1130 1131 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1132 cur_en = 0; /* not visible beyond left edge*/ 1133 1134 if (src_y_offset >= (int)param->viewport.height) 1135 cur_en = 0; /* not visible beyond bottom edge*/ 1136 1137 if (src_y_offset < 0) //+ (int)hubp->curs_attr.height 1138 cur_en = 0; /* not visible beyond top edge*/ 1139 1140 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1141 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1142 1143 REG_UPDATE(CURSOR_CONTROL, 1144 CURSOR_ENABLE, cur_en); 1145 1146 REG_SET_2(CURSOR_POSITION, 0, 1147 CURSOR_X_POSITION, pos->x, 1148 CURSOR_Y_POSITION, pos->y); 1149 1150 REG_SET_2(CURSOR_HOT_SPOT, 0, 1151 CURSOR_HOT_SPOT_X, x_hotspot, 1152 CURSOR_HOT_SPOT_Y, y_hotspot); 1153 1154 REG_SET(CURSOR_DST_OFFSET, 0, 1155 CURSOR_DST_X_OFFSET, dst_x_offset); 1156 /* TODO Handle surface pixel formats other than 4:4:4 */ 1157 } 1158 1159 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1160 { 1161 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1162 uint32_t clk_enable = enable ? 1 : 0; 1163 1164 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1165 } 1166 1167 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1168 { 1169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1170 1171 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1172 } 1173 1174 static const struct hubp_funcs dcn10_hubp_funcs = { 1175 .hubp_program_surface_flip_and_addr = 1176 hubp1_program_surface_flip_and_addr, 1177 .hubp_program_surface_config = 1178 hubp1_program_surface_config, 1179 .hubp_is_flip_pending = hubp1_is_flip_pending, 1180 .hubp_setup = hubp1_setup, 1181 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1182 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1183 .set_blank = hubp1_set_blank, 1184 .dcc_control = hubp1_dcc_control, 1185 .mem_program_viewport = min_set_viewport, 1186 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1187 .set_cursor_attributes = hubp1_cursor_set_attributes, 1188 .set_cursor_position = hubp1_cursor_set_position, 1189 .hubp_disconnect = hubp1_disconnect, 1190 .hubp_clk_cntl = hubp1_clk_cntl, 1191 .hubp_vtg_sel = hubp1_vtg_sel, 1192 .hubp_read_state = hubp1_read_state, 1193 .hubp_disable_control = hubp1_disable_control, 1194 .hubp_get_underflow_status = hubp1_get_underflow_status, 1195 1196 }; 1197 1198 /*****************************************/ 1199 /* Constructor, Destructor */ 1200 /*****************************************/ 1201 1202 void dcn10_hubp_construct( 1203 struct dcn10_hubp *hubp1, 1204 struct dc_context *ctx, 1205 uint32_t inst, 1206 const struct dcn_mi_registers *hubp_regs, 1207 const struct dcn_mi_shift *hubp_shift, 1208 const struct dcn_mi_mask *hubp_mask) 1209 { 1210 hubp1->base.funcs = &dcn10_hubp_funcs; 1211 hubp1->base.ctx = ctx; 1212 hubp1->hubp_regs = hubp_regs; 1213 hubp1->hubp_shift = hubp_shift; 1214 hubp1->hubp_mask = hubp_mask; 1215 hubp1->base.inst = inst; 1216 hubp1->base.opp_id = 0xf; 1217 hubp1->base.mpcc_id = 0xf; 1218 } 1219 1220 1221