186be9a04SYue Hin Lau /* 286be9a04SYue Hin Lau * Copyright 2012-15 Advanced Micro Devices, Inc. 386be9a04SYue Hin Lau * 486be9a04SYue Hin Lau * Permission is hereby granted, free of charge, to any person obtaining a 586be9a04SYue Hin Lau * copy of this software and associated documentation files (the "Software"), 686be9a04SYue Hin Lau * to deal in the Software without restriction, including without limitation 786be9a04SYue Hin Lau * the rights to use, copy, modify, merge, publish, distribute, sublicense, 886be9a04SYue Hin Lau * and/or sell copies of the Software, and to permit persons to whom the 986be9a04SYue Hin Lau * Software is furnished to do so, subject to the following conditions: 1086be9a04SYue Hin Lau * 1186be9a04SYue Hin Lau * The above copyright notice and this permission notice shall be included in 1286be9a04SYue Hin Lau * all copies or substantial portions of the Software. 1386be9a04SYue Hin Lau * 1486be9a04SYue Hin Lau * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1586be9a04SYue Hin Lau * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1686be9a04SYue Hin Lau * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1786be9a04SYue Hin Lau * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1886be9a04SYue Hin Lau * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1986be9a04SYue Hin Lau * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2086be9a04SYue Hin Lau * OTHER DEALINGS IN THE SOFTWARE. 2186be9a04SYue Hin Lau * 2286be9a04SYue Hin Lau * Authors: AMD 2386be9a04SYue Hin Lau * 2486be9a04SYue Hin Lau */ 2586be9a04SYue Hin Lau #include "dm_services.h" 2686be9a04SYue Hin Lau #include "dce_calcs.h" 2786be9a04SYue Hin Lau #include "reg_helper.h" 2886be9a04SYue Hin Lau #include "basics/conversion.h" 2986be9a04SYue Hin Lau #include "dcn10_hubp.h" 3086be9a04SYue Hin Lau 3186be9a04SYue Hin Lau #define REG(reg)\ 32c42c275cSYue Hin Lau hubp1->hubp_regs->reg 3386be9a04SYue Hin Lau 3486be9a04SYue Hin Lau #define CTX \ 3586be9a04SYue Hin Lau hubp1->base.ctx 3686be9a04SYue Hin Lau 3786be9a04SYue Hin Lau #undef FN 3886be9a04SYue Hin Lau #define FN(reg_name, field_name) \ 39c42c275cSYue Hin Lau hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 4086be9a04SYue Hin Lau 4186be9a04SYue Hin Lau void hubp1_set_blank(struct hubp *hubp, bool blank) 4286be9a04SYue Hin Lau { 4386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 4486be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 4586be9a04SYue Hin Lau 4675c2dec3STony Cheng REG_UPDATE_2(DCHUBP_CNTL, 4786be9a04SYue Hin Lau HUBP_BLANK_EN, blank_en, 4886be9a04SYue Hin Lau HUBP_TTU_DISABLE, blank_en); 4986be9a04SYue Hin Lau 5086be9a04SYue Hin Lau if (blank) { 5175c2dec3STony Cheng uint32_t reg_val = REG_READ(DCHUBP_CNTL); 5275c2dec3STony Cheng 53cc55b1f5STony Cheng if (reg_val) { 54cc55b1f5STony Cheng /* init sequence workaround: in case HUBP is 55cc55b1f5STony Cheng * power gated, this wait would timeout. 56cc55b1f5STony Cheng * 57cc55b1f5STony Cheng * we just wrote reg_val to non-0, if it stay 0 58cc55b1f5STony Cheng * it means HUBP is gated 59cc55b1f5STony Cheng */ 6086be9a04SYue Hin Lau REG_WAIT(DCHUBP_CNTL, 6186be9a04SYue Hin Lau HUBP_NO_OUTSTANDING_REQ, 1, 6286be9a04SYue Hin Lau 1, 200); 63cc55b1f5STony Cheng } 64cc55b1f5STony Cheng 6586be9a04SYue Hin Lau hubp->mpcc_id = 0xf; 6686be9a04SYue Hin Lau hubp->opp_id = 0xf; 6786be9a04SYue Hin Lau } 6886be9a04SYue Hin Lau } 6986be9a04SYue Hin Lau 701dbac201SYongqiang Sun static void hubp1_disconnect(struct hubp *hubp) 711dbac201SYongqiang Sun { 721dbac201SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 731dbac201SYongqiang Sun 741dbac201SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, 751dbac201SYongqiang Sun HUBP_TTU_DISABLE, 1); 765af9d013SEric Yang 775af9d013SEric Yang REG_UPDATE(CURSOR_CONTROL, 785af9d013SEric Yang CURSOR_ENABLE, 0); 791dbac201SYongqiang Sun } 801dbac201SYongqiang Sun 813ba43a59SCharlene Liu static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 823ba43a59SCharlene Liu { 833ba43a59SCharlene Liu struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 843ba43a59SCharlene Liu uint32_t disable = disable_hubp ? 1 : 0; 853ba43a59SCharlene Liu 863ba43a59SCharlene Liu REG_UPDATE(DCHUBP_CNTL, 873ba43a59SCharlene Liu HUBP_DISABLE, disable); 883ba43a59SCharlene Liu } 893ba43a59SCharlene Liu 903ba43a59SCharlene Liu static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 913ba43a59SCharlene Liu { 923ba43a59SCharlene Liu uint32_t hubp_underflow = 0; 933ba43a59SCharlene Liu struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 943ba43a59SCharlene Liu 953ba43a59SCharlene Liu REG_GET(DCHUBP_CNTL, 963ba43a59SCharlene Liu HUBP_UNDERFLOW_STATUS, 973ba43a59SCharlene Liu &hubp_underflow); 983ba43a59SCharlene Liu 993ba43a59SCharlene Liu return hubp_underflow; 1003ba43a59SCharlene Liu } 1013ba43a59SCharlene Liu 10286be9a04SYue Hin Lau static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 10386be9a04SYue Hin Lau { 10486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 10586be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 10686be9a04SYue Hin Lau 10786be9a04SYue Hin Lau REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 10886be9a04SYue Hin Lau } 10986be9a04SYue Hin Lau 11086be9a04SYue Hin Lau static void hubp1_vready_workaround(struct hubp *hubp, 11186be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 11286be9a04SYue Hin Lau { 11386be9a04SYue Hin Lau uint32_t value = 0; 11486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 11586be9a04SYue Hin Lau 11686be9a04SYue Hin Lau /* set HBUBREQ_DEBUG_DB[12] = 1 */ 11786be9a04SYue Hin Lau value = REG_READ(HUBPREQ_DEBUG_DB); 11886be9a04SYue Hin Lau 11986be9a04SYue Hin Lau /* hack mode disable */ 12086be9a04SYue Hin Lau value |= 0x100; 12186be9a04SYue Hin Lau value &= ~0x1000; 12286be9a04SYue Hin Lau 12386be9a04SYue Hin Lau if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 12486be9a04SYue Hin Lau + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 12586be9a04SYue Hin Lau /* if (eco_fix_needed(otg_global_sync_timing) 12686be9a04SYue Hin Lau * set HBUBREQ_DEBUG_DB[12] = 1 */ 12786be9a04SYue Hin Lau value |= 0x1000; 12886be9a04SYue Hin Lau } 12986be9a04SYue Hin Lau 13086be9a04SYue Hin Lau REG_WRITE(HUBPREQ_DEBUG_DB, value); 13186be9a04SYue Hin Lau } 13286be9a04SYue Hin Lau 13386be9a04SYue Hin Lau void hubp1_program_tiling( 1344b8240bfSYue Hin Lau struct hubp *hubp, 13586be9a04SYue Hin Lau const union dc_tiling_info *info, 13686be9a04SYue Hin Lau const enum surface_pixel_format pixel_format) 13786be9a04SYue Hin Lau { 1384b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1394b8240bfSYue Hin Lau 14086be9a04SYue Hin Lau REG_UPDATE_6(DCSURF_ADDR_CONFIG, 14186be9a04SYue Hin Lau NUM_PIPES, log_2(info->gfx9.num_pipes), 14286be9a04SYue Hin Lau NUM_BANKS, log_2(info->gfx9.num_banks), 14386be9a04SYue Hin Lau PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 14486be9a04SYue Hin Lau NUM_SE, log_2(info->gfx9.num_shader_engines), 14586be9a04SYue Hin Lau NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 14686be9a04SYue Hin Lau MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 14786be9a04SYue Hin Lau 14886be9a04SYue Hin Lau REG_UPDATE_4(DCSURF_TILING_CONFIG, 14986be9a04SYue Hin Lau SW_MODE, info->gfx9.swizzle, 15086be9a04SYue Hin Lau META_LINEAR, info->gfx9.meta_linear, 15186be9a04SYue Hin Lau RB_ALIGNED, info->gfx9.rb_aligned, 15286be9a04SYue Hin Lau PIPE_ALIGNED, info->gfx9.pipe_aligned); 15386be9a04SYue Hin Lau } 15486be9a04SYue Hin Lau 155a9962fb8SEric Bernstein void hubp1_program_size( 1564b8240bfSYue Hin Lau struct hubp *hubp, 15786be9a04SYue Hin Lau enum surface_pixel_format format, 15886be9a04SYue Hin Lau const union plane_size *plane_size, 159a9962fb8SEric Bernstein struct dc_plane_dcc_param *dcc) 16086be9a04SYue Hin Lau { 1614b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 162a9962fb8SEric Bernstein uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 16386be9a04SYue Hin Lau 16486be9a04SYue Hin Lau /* Program data and meta surface pitch (calculation from addrlib) 16586be9a04SYue Hin Lau * 444 or 420 luma 16686be9a04SYue Hin Lau */ 167836758ffSZheng, XueLai(Eric) if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 1688ec06a17SJulian Parkin ASSERT(plane_size->video.chroma_pitch != 0); 1698ec06a17SJulian Parkin /* Chroma pitch zero can cause system hang! */ 1708ec06a17SJulian Parkin 17186be9a04SYue Hin Lau pitch = plane_size->video.luma_pitch - 1; 17286be9a04SYue Hin Lau meta_pitch = dcc->video.meta_pitch_l - 1; 17386be9a04SYue Hin Lau pitch_c = plane_size->video.chroma_pitch - 1; 17486be9a04SYue Hin Lau meta_pitch_c = dcc->video.meta_pitch_c - 1; 17586be9a04SYue Hin Lau } else { 17686be9a04SYue Hin Lau pitch = plane_size->grph.surface_pitch - 1; 17786be9a04SYue Hin Lau meta_pitch = dcc->grph.meta_pitch - 1; 17886be9a04SYue Hin Lau pitch_c = 0; 17986be9a04SYue Hin Lau meta_pitch_c = 0; 18086be9a04SYue Hin Lau } 18186be9a04SYue Hin Lau 18286be9a04SYue Hin Lau if (!dcc->enable) { 18386be9a04SYue Hin Lau meta_pitch = 0; 18486be9a04SYue Hin Lau meta_pitch_c = 0; 18586be9a04SYue Hin Lau } 18686be9a04SYue Hin Lau 18786be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH, 18886be9a04SYue Hin Lau PITCH, pitch, META_PITCH, meta_pitch); 18986be9a04SYue Hin Lau 19086be9a04SYue Hin Lau if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 19186be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 19286be9a04SYue Hin Lau PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 193a9962fb8SEric Bernstein } 194a9962fb8SEric Bernstein 195a9962fb8SEric Bernstein void hubp1_program_rotation( 196a9962fb8SEric Bernstein struct hubp *hubp, 197a9962fb8SEric Bernstein enum dc_rotation_angle rotation, 198a9962fb8SEric Bernstein bool horizontal_mirror) 199a9962fb8SEric Bernstein { 200a9962fb8SEric Bernstein struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 201a9962fb8SEric Bernstein uint32_t mirror; 202a9962fb8SEric Bernstein 20386be9a04SYue Hin Lau 20486be9a04SYue Hin Lau if (horizontal_mirror) 20586be9a04SYue Hin Lau mirror = 1; 20686be9a04SYue Hin Lau else 20786be9a04SYue Hin Lau mirror = 0; 20886be9a04SYue Hin Lau 20986be9a04SYue Hin Lau /* Program rotation angle and horz mirror - no mirror */ 21086be9a04SYue Hin Lau if (rotation == ROTATION_ANGLE_0) 21186be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 21286be9a04SYue Hin Lau ROTATION_ANGLE, 0, 21386be9a04SYue Hin Lau H_MIRROR_EN, mirror); 21486be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_90) 21586be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 21686be9a04SYue Hin Lau ROTATION_ANGLE, 1, 21786be9a04SYue Hin Lau H_MIRROR_EN, mirror); 21886be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_180) 21986be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 22086be9a04SYue Hin Lau ROTATION_ANGLE, 2, 22186be9a04SYue Hin Lau H_MIRROR_EN, mirror); 22286be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_270) 22386be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 22486be9a04SYue Hin Lau ROTATION_ANGLE, 3, 22586be9a04SYue Hin Lau H_MIRROR_EN, mirror); 22686be9a04SYue Hin Lau } 22786be9a04SYue Hin Lau 22886be9a04SYue Hin Lau void hubp1_program_pixel_format( 2294b8240bfSYue Hin Lau struct hubp *hubp, 23086be9a04SYue Hin Lau enum surface_pixel_format format) 23186be9a04SYue Hin Lau { 2324b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 23386be9a04SYue Hin Lau uint32_t red_bar = 3; 23486be9a04SYue Hin Lau uint32_t blue_bar = 2; 23586be9a04SYue Hin Lau 23686be9a04SYue Hin Lau /* swap for ABGR format */ 23786be9a04SYue Hin Lau if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 23886be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 23986be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 24086be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 24186be9a04SYue Hin Lau red_bar = 2; 24286be9a04SYue Hin Lau blue_bar = 3; 24386be9a04SYue Hin Lau } 24486be9a04SYue Hin Lau 24586be9a04SYue Hin Lau REG_UPDATE_2(HUBPRET_CONTROL, 24686be9a04SYue Hin Lau CROSSBAR_SRC_CB_B, blue_bar, 24786be9a04SYue Hin Lau CROSSBAR_SRC_CR_R, red_bar); 24886be9a04SYue Hin Lau 24986be9a04SYue Hin Lau /* Mapping is same as ipp programming (cnvc) */ 25086be9a04SYue Hin Lau 25186be9a04SYue Hin Lau switch (format) { 25286be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 25386be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 25486be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 1); 25586be9a04SYue Hin Lau break; 25686be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 25786be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 25886be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 3); 25986be9a04SYue Hin Lau break; 26086be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 26186be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 26286be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 8); 26486be9a04SYue Hin Lau break; 26586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 26686be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 26786be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 26886be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26986be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 10); 27086be9a04SYue Hin Lau break; 27186be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 27286be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 27386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 22); 27486be9a04SYue Hin Lau break; 27586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 27686be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 27786be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 27886be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 24); 27986be9a04SYue Hin Lau break; 28086be9a04SYue Hin Lau 28186be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 28286be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 28386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 65); 28486be9a04SYue Hin Lau break; 28586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 28686be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 28786be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 64); 28886be9a04SYue Hin Lau break; 28986be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 29086be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 29186be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 67); 29286be9a04SYue Hin Lau break; 29386be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 29486be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 29586be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 66); 29686be9a04SYue Hin Lau break; 2973fc9fc4cSvikrant mhaske case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 2983fc9fc4cSvikrant mhaske REG_UPDATE(DCSURF_SURFACE_CONFIG, 2993fc9fc4cSvikrant mhaske SURFACE_PIXEL_FORMAT, 12); 3003fc9fc4cSvikrant mhaske break; 30186be9a04SYue Hin Lau default: 30286be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 30386be9a04SYue Hin Lau break; 30486be9a04SYue Hin Lau } 30586be9a04SYue Hin Lau 30686be9a04SYue Hin Lau /* don't see the need of program the xbar in DCN 1.0 */ 30786be9a04SYue Hin Lau } 30886be9a04SYue Hin Lau 30986be9a04SYue Hin Lau bool hubp1_program_surface_flip_and_addr( 31086be9a04SYue Hin Lau struct hubp *hubp, 31186be9a04SYue Hin Lau const struct dc_plane_address *address, 31286be9a04SYue Hin Lau bool flip_immediate) 31386be9a04SYue Hin Lau { 31486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 31586be9a04SYue Hin Lau 3161336926fSAlvin lee 3171336926fSAlvin lee //program flip type 3181336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, 31986be9a04SYue Hin Lau SURFACE_FLIP_TYPE, flip_immediate); 32086be9a04SYue Hin Lau 3211336926fSAlvin lee 3221336926fSAlvin lee if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 3231336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 3241336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 3251336926fSAlvin lee 3261336926fSAlvin lee } else { 3271336926fSAlvin lee // turn off stereo if not in stereo 3281336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 3291336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 3301336926fSAlvin lee } 3311336926fSAlvin lee 3321336926fSAlvin lee 3331336926fSAlvin lee 33486be9a04SYue Hin Lau /* HW automatically latch rest of address register on write to 33586be9a04SYue Hin Lau * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 33686be9a04SYue Hin Lau * 33786be9a04SYue Hin Lau * program high first and then the low addr, order matters! 33886be9a04SYue Hin Lau */ 33986be9a04SYue Hin Lau switch (address->type) { 34086be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRAPHICS: 34186be9a04SYue Hin Lau /* DCN1.0 does not support const color 34286be9a04SYue Hin Lau * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 34386be9a04SYue Hin Lau * base on address->grph.dcc_const_color 34486be9a04SYue Hin Lau * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 34586be9a04SYue Hin Lau * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 34686be9a04SYue Hin Lau */ 34786be9a04SYue Hin Lau 34886be9a04SYue Hin Lau if (address->grph.addr.quad_part == 0) 34986be9a04SYue Hin Lau break; 35086be9a04SYue Hin Lau 351cf8c19a3SYongqiang Sun REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 352cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 353cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 35486be9a04SYue Hin Lau 35586be9a04SYue Hin Lau if (address->grph.meta_addr.quad_part != 0) { 35686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 35786be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 35886be9a04SYue Hin Lau address->grph.meta_addr.high_part); 35986be9a04SYue Hin Lau 36086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 36186be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 36286be9a04SYue Hin Lau address->grph.meta_addr.low_part); 36386be9a04SYue Hin Lau } 36486be9a04SYue Hin Lau 36586be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 36686be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 36786be9a04SYue Hin Lau address->grph.addr.high_part); 36886be9a04SYue Hin Lau 36986be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 37086be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 37186be9a04SYue Hin Lau address->grph.addr.low_part); 37286be9a04SYue Hin Lau break; 37386be9a04SYue Hin Lau case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 37486be9a04SYue Hin Lau if (address->video_progressive.luma_addr.quad_part == 0 37586be9a04SYue Hin Lau || address->video_progressive.chroma_addr.quad_part == 0) 37686be9a04SYue Hin Lau break; 37786be9a04SYue Hin Lau 378cf8c19a3SYongqiang Sun REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 379cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 380cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 381cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 382cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 38386be9a04SYue Hin Lau 38486be9a04SYue Hin Lau if (address->video_progressive.luma_meta_addr.quad_part != 0) { 38586be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 38686be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 38786be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.high_part); 38886be9a04SYue Hin Lau 38986be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 39086be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_C, 39186be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.low_part); 39286be9a04SYue Hin Lau 39386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 39486be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 39586be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.high_part); 39686be9a04SYue Hin Lau 39786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 39886be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 39986be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.low_part); 40086be9a04SYue Hin Lau } 40186be9a04SYue Hin Lau 40286be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 40386be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH_C, 40486be9a04SYue Hin Lau address->video_progressive.chroma_addr.high_part); 40586be9a04SYue Hin Lau 40686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 40786be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_C, 40886be9a04SYue Hin Lau address->video_progressive.chroma_addr.low_part); 40986be9a04SYue Hin Lau 41086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 41186be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 41286be9a04SYue Hin Lau address->video_progressive.luma_addr.high_part); 41386be9a04SYue Hin Lau 41486be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 41586be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 41686be9a04SYue Hin Lau address->video_progressive.luma_addr.low_part); 41786be9a04SYue Hin Lau break; 41886be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRPH_STEREO: 41986be9a04SYue Hin Lau if (address->grph_stereo.left_addr.quad_part == 0) 42086be9a04SYue Hin Lau break; 42186be9a04SYue Hin Lau if (address->grph_stereo.right_addr.quad_part == 0) 42286be9a04SYue Hin Lau break; 42386be9a04SYue Hin Lau 424aa6d4a59SEric Bernstein REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 425cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 426cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 427cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 428aa6d4a59SEric Bernstein PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 429aa6d4a59SEric Bernstein SECONDARY_SURFACE_TMZ, address->tmz_surface, 430aa6d4a59SEric Bernstein SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 431aa6d4a59SEric Bernstein SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 432aa6d4a59SEric Bernstein SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 43386be9a04SYue Hin Lau 43486be9a04SYue Hin Lau if (address->grph_stereo.right_meta_addr.quad_part != 0) { 43586be9a04SYue Hin Lau 43686be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 43786be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS_HIGH, 43886be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.high_part); 43986be9a04SYue Hin Lau 44086be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 44186be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS, 44286be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.low_part); 44386be9a04SYue Hin Lau } 44486be9a04SYue Hin Lau if (address->grph_stereo.left_meta_addr.quad_part != 0) { 44586be9a04SYue Hin Lau 44686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 44786be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 44886be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.high_part); 44986be9a04SYue Hin Lau 45086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 45186be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 45286be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.low_part); 45386be9a04SYue Hin Lau } 45486be9a04SYue Hin Lau 45586be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 45686be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS_HIGH, 45786be9a04SYue Hin Lau address->grph_stereo.right_addr.high_part); 45886be9a04SYue Hin Lau 45986be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 46086be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS, 46186be9a04SYue Hin Lau address->grph_stereo.right_addr.low_part); 46286be9a04SYue Hin Lau 46386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 46486be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 46586be9a04SYue Hin Lau address->grph_stereo.left_addr.high_part); 46686be9a04SYue Hin Lau 46786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 46886be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 46986be9a04SYue Hin Lau address->grph_stereo.left_addr.low_part); 47086be9a04SYue Hin Lau break; 47186be9a04SYue Hin Lau default: 47286be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 47386be9a04SYue Hin Lau break; 47486be9a04SYue Hin Lau } 47586be9a04SYue Hin Lau 47686be9a04SYue Hin Lau hubp->request_address = *address; 47786be9a04SYue Hin Lau 47886be9a04SYue Hin Lau return true; 47986be9a04SYue Hin Lau } 48086be9a04SYue Hin Lau 48186be9a04SYue Hin Lau void hubp1_dcc_control(struct hubp *hubp, bool enable, 48286be9a04SYue Hin Lau bool independent_64b_blks) 48386be9a04SYue Hin Lau { 48486be9a04SYue Hin Lau uint32_t dcc_en = enable ? 1 : 0; 48586be9a04SYue Hin Lau uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 48686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 48786be9a04SYue Hin Lau 488aa6d4a59SEric Bernstein REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 48986be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, dcc_en, 490aa6d4a59SEric Bernstein PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 491aa6d4a59SEric Bernstein SECONDARY_SURFACE_DCC_EN, dcc_en, 492aa6d4a59SEric Bernstein SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 49386be9a04SYue Hin Lau } 49486be9a04SYue Hin Lau 49586be9a04SYue Hin Lau void hubp1_program_surface_config( 49686be9a04SYue Hin Lau struct hubp *hubp, 49786be9a04SYue Hin Lau enum surface_pixel_format format, 49886be9a04SYue Hin Lau union dc_tiling_info *tiling_info, 49986be9a04SYue Hin Lau union plane_size *plane_size, 50086be9a04SYue Hin Lau enum dc_rotation_angle rotation, 50186be9a04SYue Hin Lau struct dc_plane_dcc_param *dcc, 502a465feaeSCharlene Liu bool horizontal_mirror, 503a465feaeSCharlene Liu unsigned int compat_level) 50486be9a04SYue Hin Lau { 50586be9a04SYue Hin Lau hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 5064b8240bfSYue Hin Lau hubp1_program_tiling(hubp, tiling_info, format); 507a9962fb8SEric Bernstein hubp1_program_size(hubp, format, plane_size, dcc); 508a9962fb8SEric Bernstein hubp1_program_rotation(hubp, rotation, horizontal_mirror); 5094b8240bfSYue Hin Lau hubp1_program_pixel_format(hubp, format); 51086be9a04SYue Hin Lau } 51186be9a04SYue Hin Lau 51286be9a04SYue Hin Lau void hubp1_program_requestor( 51386be9a04SYue Hin Lau struct hubp *hubp, 51486be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs) 51586be9a04SYue Hin Lau { 51686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 51786be9a04SYue Hin Lau 51886be9a04SYue Hin Lau REG_UPDATE(HUBPRET_CONTROL, 51986be9a04SYue Hin Lau DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 52086be9a04SYue Hin Lau REG_SET_4(DCN_EXPANSION_MODE, 0, 52186be9a04SYue Hin Lau DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 52286be9a04SYue Hin Lau PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 52386be9a04SYue Hin Lau MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 52486be9a04SYue Hin Lau CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 52586be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 52686be9a04SYue Hin Lau CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 52786be9a04SYue Hin Lau MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 52886be9a04SYue Hin Lau META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 52986be9a04SYue Hin Lau MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 53086be9a04SYue Hin Lau DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 53186be9a04SYue Hin Lau MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 53286be9a04SYue Hin Lau SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 53386be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 53486be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 53586be9a04SYue Hin Lau CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 53686be9a04SYue Hin Lau MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 53786be9a04SYue Hin Lau META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 53886be9a04SYue Hin Lau MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 53986be9a04SYue Hin Lau DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 54086be9a04SYue Hin Lau MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 54186be9a04SYue Hin Lau SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 54286be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 54386be9a04SYue Hin Lau } 54486be9a04SYue Hin Lau 54586be9a04SYue Hin Lau 54686be9a04SYue Hin Lau void hubp1_program_deadline( 54786be9a04SYue Hin Lau struct hubp *hubp, 54886be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 54986be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 55086be9a04SYue Hin Lau { 55186be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 55286be9a04SYue Hin Lau 55386be9a04SYue Hin Lau /* DLG - Per hubp */ 55486be9a04SYue Hin Lau REG_SET_2(BLANK_OFFSET_0, 0, 55586be9a04SYue Hin Lau REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 55686be9a04SYue Hin Lau DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 55786be9a04SYue Hin Lau 55886be9a04SYue Hin Lau REG_SET(BLANK_OFFSET_1, 0, 55986be9a04SYue Hin Lau MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 56086be9a04SYue Hin Lau 56186be9a04SYue Hin Lau REG_SET(DST_DIMENSIONS, 0, 56286be9a04SYue Hin Lau REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 56386be9a04SYue Hin Lau 56486be9a04SYue Hin Lau REG_SET_2(DST_AFTER_SCALER, 0, 56586be9a04SYue Hin Lau REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 56686be9a04SYue Hin Lau DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 56786be9a04SYue Hin Lau 56886be9a04SYue Hin Lau if (REG(PREFETCH_SETTINS)) 56986be9a04SYue Hin Lau REG_SET_2(PREFETCH_SETTINS, 0, 57086be9a04SYue Hin Lau DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 57186be9a04SYue Hin Lau VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 57286be9a04SYue Hin Lau else 57386be9a04SYue Hin Lau REG_SET_2(PREFETCH_SETTINGS, 0, 57486be9a04SYue Hin Lau DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 57586be9a04SYue Hin Lau VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 57686be9a04SYue Hin Lau 57786be9a04SYue Hin Lau REG_SET_2(VBLANK_PARAMETERS_0, 0, 57886be9a04SYue Hin Lau DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 57986be9a04SYue Hin Lau DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 58086be9a04SYue Hin Lau 58186be9a04SYue Hin Lau REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 58286be9a04SYue Hin Lau REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 58386be9a04SYue Hin Lau 58486be9a04SYue Hin Lau /* DLG - Per luma/chroma */ 58586be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_1, 0, 58686be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 58786be9a04SYue Hin Lau 58886be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_3, 0, 58986be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 59086be9a04SYue Hin Lau 591b552204bSNikola Cornij if (REG(NOM_PARAMETERS_0)) 59286be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_0, 0, 59386be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 59486be9a04SYue Hin Lau 595b552204bSNikola Cornij if (REG(NOM_PARAMETERS_1)) 59686be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_1, 0, 59786be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 59886be9a04SYue Hin Lau 59986be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_4, 0, 60086be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 60186be9a04SYue Hin Lau 60286be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_5, 0, 60386be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 60486be9a04SYue Hin Lau 60586be9a04SYue Hin Lau REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 60686be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 60786be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 60886be9a04SYue Hin Lau 60986be9a04SYue Hin Lau REG_SET_2(PER_LINE_DELIVERY, 0, 61086be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 61186be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 61286be9a04SYue Hin Lau 61386be9a04SYue Hin Lau if (REG(PREFETCH_SETTINS_C)) 61486be9a04SYue Hin Lau REG_SET(PREFETCH_SETTINS_C, 0, 61586be9a04SYue Hin Lau VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 61686be9a04SYue Hin Lau else 61786be9a04SYue Hin Lau REG_SET(PREFETCH_SETTINGS_C, 0, 61886be9a04SYue Hin Lau VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 61986be9a04SYue Hin Lau 62086be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_2, 0, 62186be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 62286be9a04SYue Hin Lau 62386be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_4, 0, 62486be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 62586be9a04SYue Hin Lau 626b552204bSNikola Cornij if (REG(NOM_PARAMETERS_2)) 62786be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_2, 0, 62886be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 62986be9a04SYue Hin Lau 630b552204bSNikola Cornij if (REG(NOM_PARAMETERS_3)) 63186be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_3, 0, 63286be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 63386be9a04SYue Hin Lau 63486be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_6, 0, 63586be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 63686be9a04SYue Hin Lau 63786be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_7, 0, 63886be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 63986be9a04SYue Hin Lau 64086be9a04SYue Hin Lau /* TTU - per hubp */ 64186be9a04SYue Hin Lau REG_SET_2(DCN_TTU_QOS_WM, 0, 64286be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 64386be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 64486be9a04SYue Hin Lau 64586be9a04SYue Hin Lau REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 64686be9a04SYue Hin Lau MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 64786be9a04SYue Hin Lau QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 64886be9a04SYue Hin Lau 64986be9a04SYue Hin Lau /* TTU - per luma/chroma */ 65086be9a04SYue Hin Lau /* Assumed surf0 is luma and 1 is chroma */ 65186be9a04SYue Hin Lau 65286be9a04SYue Hin Lau REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 65386be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 65486be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 65586be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 65686be9a04SYue Hin Lau 65786be9a04SYue Hin Lau REG_SET(DCN_SURF0_TTU_CNTL1, 0, 65886be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY_PRE, 65986be9a04SYue Hin Lau ttu_attr->refcyc_per_req_delivery_pre_l); 66086be9a04SYue Hin Lau 66186be9a04SYue Hin Lau REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 66286be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 66386be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 66486be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 66586be9a04SYue Hin Lau 66686be9a04SYue Hin Lau REG_SET(DCN_SURF1_TTU_CNTL1, 0, 66786be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY_PRE, 66886be9a04SYue Hin Lau ttu_attr->refcyc_per_req_delivery_pre_c); 669c0aceb7dSCharlene Liu 670c0aceb7dSCharlene Liu REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 671c0aceb7dSCharlene Liu REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 672c0aceb7dSCharlene Liu QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 673c0aceb7dSCharlene Liu QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 674c0aceb7dSCharlene Liu REG_SET(DCN_CUR0_TTU_CNTL1, 0, 675c0aceb7dSCharlene Liu REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 67686be9a04SYue Hin Lau } 67786be9a04SYue Hin Lau 67886be9a04SYue Hin Lau static void hubp1_setup( 67986be9a04SYue Hin Lau struct hubp *hubp, 68086be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 68186be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 68286be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs, 68386be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 68486be9a04SYue Hin Lau { 68586be9a04SYue Hin Lau /* otg is locked when this func is called. Register are double buffered. 68686be9a04SYue Hin Lau * disable the requestors is not needed 68786be9a04SYue Hin Lau */ 68886be9a04SYue Hin Lau hubp1_program_requestor(hubp, rq_regs); 68986be9a04SYue Hin Lau hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 69086be9a04SYue Hin Lau hubp1_vready_workaround(hubp, pipe_dest); 69186be9a04SYue Hin Lau } 69286be9a04SYue Hin Lau 69386be9a04SYue Hin Lau bool hubp1_is_flip_pending(struct hubp *hubp) 69486be9a04SYue Hin Lau { 69586be9a04SYue Hin Lau uint32_t flip_pending = 0; 69686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 69786be9a04SYue Hin Lau struct dc_plane_address earliest_inuse_address; 69886be9a04SYue Hin Lau 69986be9a04SYue Hin Lau REG_GET(DCSURF_FLIP_CONTROL, 70086be9a04SYue Hin Lau SURFACE_FLIP_PENDING, &flip_pending); 70186be9a04SYue Hin Lau 70286be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 70386be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 70486be9a04SYue Hin Lau 70586be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 70686be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 70786be9a04SYue Hin Lau 70886be9a04SYue Hin Lau if (flip_pending) 70986be9a04SYue Hin Lau return true; 71086be9a04SYue Hin Lau 71186be9a04SYue Hin Lau if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 71286be9a04SYue Hin Lau return true; 71386be9a04SYue Hin Lau 71486be9a04SYue Hin Lau return false; 71586be9a04SYue Hin Lau } 71686be9a04SYue Hin Lau 71786be9a04SYue Hin Lau uint32_t aperture_default_system = 1; 71886be9a04SYue Hin Lau uint32_t context0_default_system; /* = 0;*/ 71986be9a04SYue Hin Lau 72086be9a04SYue Hin Lau static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 72186be9a04SYue Hin Lau struct vm_system_aperture_param *apt) 72286be9a04SYue Hin Lau { 72386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 72486be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 72586be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 72686be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 72786be9a04SYue Hin Lau 72886be9a04SYue Hin Lau mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 72986be9a04SYue Hin Lau mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 73086be9a04SYue Hin Lau mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 73186be9a04SYue Hin Lau 73286be9a04SYue Hin Lau REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 73386be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 73486be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 73586be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 73686be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 73786be9a04SYue Hin Lau 73886be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 73986be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 74086be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 74186be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 74286be9a04SYue Hin Lau 74386be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 74486be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 74586be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 74686be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 74786be9a04SYue Hin Lau } 74886be9a04SYue Hin Lau 74986be9a04SYue Hin Lau static void hubp1_set_vm_context0_settings(struct hubp *hubp, 75086be9a04SYue Hin Lau const struct vm_context0_param *vm0) 75186be9a04SYue Hin Lau { 75286be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 75386be9a04SYue Hin Lau /* pte base */ 75486be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 75586be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 75686be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 75786be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 75886be9a04SYue Hin Lau 75986be9a04SYue Hin Lau /* pte start */ 76086be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 76186be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 76286be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 76386be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 76486be9a04SYue Hin Lau 76586be9a04SYue Hin Lau /* pte end */ 76686be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 76786be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 76886be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 76986be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 77086be9a04SYue Hin Lau 77186be9a04SYue Hin Lau /* fault handling */ 77286be9a04SYue Hin Lau REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 77386be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 77486be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 77586be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 77686be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 77786be9a04SYue Hin Lau 77886be9a04SYue Hin Lau /* control: enable VM PTE*/ 77986be9a04SYue Hin Lau REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 78086be9a04SYue Hin Lau ENABLE_L1_TLB, 1, 78186be9a04SYue Hin Lau SYSTEM_ACCESS_MODE, 3); 78286be9a04SYue Hin Lau } 78386be9a04SYue Hin Lau 78486be9a04SYue Hin Lau void min_set_viewport( 78586be9a04SYue Hin Lau struct hubp *hubp, 78686be9a04SYue Hin Lau const struct rect *viewport, 78786be9a04SYue Hin Lau const struct rect *viewport_c) 78886be9a04SYue Hin Lau { 78986be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 79086be9a04SYue Hin Lau 79186be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 79286be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, viewport->width, 79386be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, viewport->height); 79486be9a04SYue Hin Lau 79586be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 79686be9a04SYue Hin Lau PRI_VIEWPORT_X_START, viewport->x, 79786be9a04SYue Hin Lau PRI_VIEWPORT_Y_START, viewport->y); 79886be9a04SYue Hin Lau 79986be9a04SYue Hin Lau /*for stereo*/ 80086be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 80186be9a04SYue Hin Lau SEC_VIEWPORT_WIDTH, viewport->width, 80286be9a04SYue Hin Lau SEC_VIEWPORT_HEIGHT, viewport->height); 80386be9a04SYue Hin Lau 80486be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 80586be9a04SYue Hin Lau SEC_VIEWPORT_X_START, viewport->x, 80686be9a04SYue Hin Lau SEC_VIEWPORT_Y_START, viewport->y); 80786be9a04SYue Hin Lau 80886be9a04SYue Hin Lau /* DC supports NV12 only at the moment */ 80986be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 81086be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH_C, viewport_c->width, 81186be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 81286be9a04SYue Hin Lau 81386be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 81486be9a04SYue Hin Lau PRI_VIEWPORT_X_START_C, viewport_c->x, 81586be9a04SYue Hin Lau PRI_VIEWPORT_Y_START_C, viewport_c->y); 81686be9a04SYue Hin Lau } 81786be9a04SYue Hin Lau 81834cb6b38SDmytro Laktyushkin void hubp1_read_state(struct hubp *hubp) 81986be9a04SYue Hin Lau { 8200a93dc7fSDmytro Laktyushkin struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 82134cb6b38SDmytro Laktyushkin struct dcn_hubp_state *s = &hubp1->state; 8220a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 8230a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 8240a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 8250a93dc7fSDmytro Laktyushkin 8260a93dc7fSDmytro Laktyushkin /* Requester */ 8270a93dc7fSDmytro Laktyushkin REG_GET(HUBPRET_CONTROL, 8280a93dc7fSDmytro Laktyushkin DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 8290a93dc7fSDmytro Laktyushkin REG_GET_4(DCN_EXPANSION_MODE, 8300a93dc7fSDmytro Laktyushkin DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 8310a93dc7fSDmytro Laktyushkin PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 8320a93dc7fSDmytro Laktyushkin MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 8330a93dc7fSDmytro Laktyushkin CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 8340a93dc7fSDmytro Laktyushkin REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 8350a93dc7fSDmytro Laktyushkin CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 8360a93dc7fSDmytro Laktyushkin MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 8370a93dc7fSDmytro Laktyushkin META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 8380a93dc7fSDmytro Laktyushkin MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 8390a93dc7fSDmytro Laktyushkin DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 8400a93dc7fSDmytro Laktyushkin MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 8410a93dc7fSDmytro Laktyushkin SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 8420a93dc7fSDmytro Laktyushkin PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 8430a93dc7fSDmytro Laktyushkin REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 8440a93dc7fSDmytro Laktyushkin CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 8450a93dc7fSDmytro Laktyushkin MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 8460a93dc7fSDmytro Laktyushkin META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 8470a93dc7fSDmytro Laktyushkin MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 8480a93dc7fSDmytro Laktyushkin DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 8490a93dc7fSDmytro Laktyushkin MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 8500a93dc7fSDmytro Laktyushkin SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 8510a93dc7fSDmytro Laktyushkin PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 8520a93dc7fSDmytro Laktyushkin 8530a93dc7fSDmytro Laktyushkin /* DLG - Per hubp */ 8540a93dc7fSDmytro Laktyushkin REG_GET_2(BLANK_OFFSET_0, 8550a93dc7fSDmytro Laktyushkin REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 8560a93dc7fSDmytro Laktyushkin DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 8570a93dc7fSDmytro Laktyushkin 8580a93dc7fSDmytro Laktyushkin REG_GET(BLANK_OFFSET_1, 8590a93dc7fSDmytro Laktyushkin MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 8600a93dc7fSDmytro Laktyushkin 8610a93dc7fSDmytro Laktyushkin REG_GET(DST_DIMENSIONS, 8620a93dc7fSDmytro Laktyushkin REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 8630a93dc7fSDmytro Laktyushkin 8640a93dc7fSDmytro Laktyushkin REG_GET_2(DST_AFTER_SCALER, 8650a93dc7fSDmytro Laktyushkin REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 8660a93dc7fSDmytro Laktyushkin DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 8670a93dc7fSDmytro Laktyushkin 8680a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS)) 8690a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINS, 8700a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8710a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8720a93dc7fSDmytro Laktyushkin else 8730a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINGS, 8740a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8750a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8760a93dc7fSDmytro Laktyushkin 8770a93dc7fSDmytro Laktyushkin REG_GET_2(VBLANK_PARAMETERS_0, 8780a93dc7fSDmytro Laktyushkin DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 8790a93dc7fSDmytro Laktyushkin DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 8800a93dc7fSDmytro Laktyushkin 8810a93dc7fSDmytro Laktyushkin REG_GET(REF_FREQ_TO_PIX_FREQ, 8820a93dc7fSDmytro Laktyushkin REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 8830a93dc7fSDmytro Laktyushkin 8840a93dc7fSDmytro Laktyushkin /* DLG - Per luma/chroma */ 8850a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_1, 8860a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 8870a93dc7fSDmytro Laktyushkin 8880a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_3, 8890a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 8900a93dc7fSDmytro Laktyushkin 8910a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_0)) 8920a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_0, 8930a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 8940a93dc7fSDmytro Laktyushkin 8950a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_1)) 8960a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_1, 8970a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 8980a93dc7fSDmytro Laktyushkin 8990a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_4, 9000a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 9010a93dc7fSDmytro Laktyushkin 9020a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_5, 9030a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 9040a93dc7fSDmytro Laktyushkin 9050a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY_PRE, 9060a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 9070a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 9080a93dc7fSDmytro Laktyushkin 9090a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY, 9100a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 9110a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 9120a93dc7fSDmytro Laktyushkin 9130a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS_C)) 9140a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINS_C, 9150a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 9160a93dc7fSDmytro Laktyushkin else 9170a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINGS_C, 9180a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 9190a93dc7fSDmytro Laktyushkin 9200a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_2, 9210a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 9220a93dc7fSDmytro Laktyushkin 9230a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_4, 9240a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 9250a93dc7fSDmytro Laktyushkin 9260a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_2)) 9270a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_2, 9280a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 9290a93dc7fSDmytro Laktyushkin 9300a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_3)) 9310a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_3, 9320a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 9330a93dc7fSDmytro Laktyushkin 9340a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_6, 9350a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 9360a93dc7fSDmytro Laktyushkin 9370a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_7, 9380a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 9390a93dc7fSDmytro Laktyushkin 9400a93dc7fSDmytro Laktyushkin /* TTU - per hubp */ 9410a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_TTU_QOS_WM, 9420a93dc7fSDmytro Laktyushkin QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 9430a93dc7fSDmytro Laktyushkin QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 9440a93dc7fSDmytro Laktyushkin 9450a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_GLOBAL_TTU_CNTL, 9460a93dc7fSDmytro Laktyushkin MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 9470a93dc7fSDmytro Laktyushkin QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 9480a93dc7fSDmytro Laktyushkin 9490a93dc7fSDmytro Laktyushkin /* TTU - per luma/chroma */ 9500a93dc7fSDmytro Laktyushkin /* Assumed surf0 is luma and 1 is chroma */ 9510a93dc7fSDmytro Laktyushkin 9520a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF0_TTU_CNTL0, 9530a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 9540a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 9550a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 9560a93dc7fSDmytro Laktyushkin 9570a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF0_TTU_CNTL1, 9580a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9590a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_l); 9600a93dc7fSDmytro Laktyushkin 9610a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF1_TTU_CNTL0, 9620a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 9630a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 9640a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 9650a93dc7fSDmytro Laktyushkin 9660a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF1_TTU_CNTL1, 9670a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9680a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_c); 9690a93dc7fSDmytro Laktyushkin 9700a93dc7fSDmytro Laktyushkin /* Rest of hubp */ 97186be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONFIG, 97286be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, &s->pixel_format); 97386be9a04SYue Hin Lau 97486be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 97586be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 97686be9a04SYue Hin Lau 977afd0384cSJun Lei REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 978afd0384cSJun Lei SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 979afd0384cSJun Lei 98086be9a04SYue Hin Lau REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 98186be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, &s->viewport_width, 98286be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, &s->viewport_height); 98386be9a04SYue Hin Lau 98486be9a04SYue Hin Lau REG_GET_2(DCSURF_SURFACE_CONFIG, 98586be9a04SYue Hin Lau ROTATION_ANGLE, &s->rotation_angle, 98686be9a04SYue Hin Lau H_MIRROR_EN, &s->h_mirror_en); 98786be9a04SYue Hin Lau 98886be9a04SYue Hin Lau REG_GET(DCSURF_TILING_CONFIG, 98986be9a04SYue Hin Lau SW_MODE, &s->sw_mode); 99086be9a04SYue Hin Lau 99186be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONTROL, 99286be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 99386be9a04SYue Hin Lau 99486be9a04SYue Hin Lau REG_GET_3(DCHUBP_CNTL, 99586be9a04SYue Hin Lau HUBP_BLANK_EN, &s->blank_en, 99686be9a04SYue Hin Lau HUBP_TTU_DISABLE, &s->ttu_disable, 99786be9a04SYue Hin Lau HUBP_UNDERFLOW_STATUS, &s->underflow_status); 99886be9a04SYue Hin Lau 99986be9a04SYue Hin Lau REG_GET(DCN_GLOBAL_TTU_CNTL, 100086be9a04SYue Hin Lau MIN_TTU_VBLANK, &s->min_ttu_vblank); 100186be9a04SYue Hin Lau 100286be9a04SYue Hin Lau REG_GET_2(DCN_TTU_QOS_WM, 100386be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 100486be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 100586be9a04SYue Hin Lau } 100686be9a04SYue Hin Lau 100736192e7eSEric Bernstein enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 100886be9a04SYue Hin Lau { 100986be9a04SYue Hin Lau enum cursor_pitch hw_pitch; 101086be9a04SYue Hin Lau 101186be9a04SYue Hin Lau switch (pitch) { 101286be9a04SYue Hin Lau case 64: 101386be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 101486be9a04SYue Hin Lau break; 101586be9a04SYue Hin Lau case 128: 101686be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_128_PIXELS; 101786be9a04SYue Hin Lau break; 101886be9a04SYue Hin Lau case 256: 101986be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_256_PIXELS; 102086be9a04SYue Hin Lau break; 102186be9a04SYue Hin Lau default: 102286be9a04SYue Hin Lau DC_ERR("Invalid cursor pitch of %d. " 102386be9a04SYue Hin Lau "Only 64/128/256 is supported on DCN.\n", pitch); 102486be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 102586be9a04SYue Hin Lau break; 102686be9a04SYue Hin Lau } 102786be9a04SYue Hin Lau return hw_pitch; 102886be9a04SYue Hin Lau } 102986be9a04SYue Hin Lau 103036192e7eSEric Bernstein static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 103186be9a04SYue Hin Lau unsigned int cur_width, 103286be9a04SYue Hin Lau enum dc_cursor_color_format format) 103386be9a04SYue Hin Lau { 103486be9a04SYue Hin Lau enum cursor_lines_per_chunk line_per_chunk; 103586be9a04SYue Hin Lau 103686be9a04SYue Hin Lau if (format == CURSOR_MODE_MONO) 103786be9a04SYue Hin Lau /* impl B. expansion in CUR Buffer reader */ 103886be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 103986be9a04SYue Hin Lau else if (cur_width <= 32) 104086be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 104186be9a04SYue Hin Lau else if (cur_width <= 64) 104286be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 104386be9a04SYue Hin Lau else if (cur_width <= 128) 104486be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 104586be9a04SYue Hin Lau else 104686be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 104786be9a04SYue Hin Lau 104886be9a04SYue Hin Lau return line_per_chunk; 104986be9a04SYue Hin Lau } 105086be9a04SYue Hin Lau 105186be9a04SYue Hin Lau void hubp1_cursor_set_attributes( 105286be9a04SYue Hin Lau struct hubp *hubp, 105386be9a04SYue Hin Lau const struct dc_cursor_attributes *attr) 105486be9a04SYue Hin Lau { 105586be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 105636192e7eSEric Bernstein enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 105736192e7eSEric Bernstein enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 105886be9a04SYue Hin Lau attr->width, attr->color_format); 105986be9a04SYue Hin Lau 106086be9a04SYue Hin Lau hubp->curs_attr = *attr; 106186be9a04SYue Hin Lau 106286be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 106386be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 106486be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS, 106586be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS, attr->address.low_part); 106686be9a04SYue Hin Lau 106786be9a04SYue Hin Lau REG_UPDATE_2(CURSOR_SIZE, 106886be9a04SYue Hin Lau CURSOR_WIDTH, attr->width, 106986be9a04SYue Hin Lau CURSOR_HEIGHT, attr->height); 107036192e7eSEric Bernstein 107186be9a04SYue Hin Lau REG_UPDATE_3(CURSOR_CONTROL, 107286be9a04SYue Hin Lau CURSOR_MODE, attr->color_format, 107386be9a04SYue Hin Lau CURSOR_PITCH, hw_pitch, 107486be9a04SYue Hin Lau CURSOR_LINES_PER_CHUNK, lpc); 107536192e7eSEric Bernstein 1076e9be38b4SEric Bernstein REG_SET_2(CURSOR_SETTINS, 0, 1077e9be38b4SEric Bernstein /* no shift of the cursor HDL schedule */ 1078e9be38b4SEric Bernstein CURSOR0_DST_Y_OFFSET, 0, 1079e9be38b4SEric Bernstein /* used to shift the cursor chunk request deadline */ 1080e9be38b4SEric Bernstein CURSOR0_CHUNK_HDL_ADJUST, 3); 108186be9a04SYue Hin Lau } 108286be9a04SYue Hin Lau 108386be9a04SYue Hin Lau void hubp1_cursor_set_position( 108486be9a04SYue Hin Lau struct hubp *hubp, 108586be9a04SYue Hin Lau const struct dc_cursor_position *pos, 108686be9a04SYue Hin Lau const struct dc_cursor_mi_param *param) 108786be9a04SYue Hin Lau { 108886be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 108939a9f4d8SDmytro Laktyushkin int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 109094a4ffd1SGloria Li int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 109108ed681cSDmytro Laktyushkin int x_hotspot = pos->x_hotspot; 109208ed681cSDmytro Laktyushkin int y_hotspot = pos->y_hotspot; 109308ed681cSDmytro Laktyushkin uint32_t dst_x_offset; 109486be9a04SYue Hin Lau uint32_t cur_en = pos->enable ? 1 : 0; 109586be9a04SYue Hin Lau 109686be9a04SYue Hin Lau /* 109786be9a04SYue Hin Lau * Guard aganst cursor_set_position() from being called with invalid 109886be9a04SYue Hin Lau * attributes 109986be9a04SYue Hin Lau * 110086be9a04SYue Hin Lau * TODO: Look at combining cursor_set_position() and 110186be9a04SYue Hin Lau * cursor_set_attributes() into cursor_update() 110286be9a04SYue Hin Lau */ 110386be9a04SYue Hin Lau if (hubp->curs_attr.address.quad_part == 0) 110486be9a04SYue Hin Lau return; 110586be9a04SYue Hin Lau 110608ed681cSDmytro Laktyushkin if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 110708ed681cSDmytro Laktyushkin src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 110808ed681cSDmytro Laktyushkin y_hotspot = pos->x_hotspot; 110908ed681cSDmytro Laktyushkin x_hotspot = pos->y_hotspot; 111008ed681cSDmytro Laktyushkin } 111108ed681cSDmytro Laktyushkin 111208ed681cSDmytro Laktyushkin if (param->mirror) { 111308ed681cSDmytro Laktyushkin x_hotspot = param->viewport.width - x_hotspot; 111408ed681cSDmytro Laktyushkin src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 111508ed681cSDmytro Laktyushkin } 111608ed681cSDmytro Laktyushkin 111708ed681cSDmytro Laktyushkin dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 111886be9a04SYue Hin Lau dst_x_offset *= param->ref_clk_khz; 111986be9a04SYue Hin Lau dst_x_offset /= param->pixel_clk_khz; 112086be9a04SYue Hin Lau 112186be9a04SYue Hin Lau ASSERT(param->h_scale_ratio.value); 112286be9a04SYue Hin Lau 112386be9a04SYue Hin Lau if (param->h_scale_ratio.value) 1124eb0e5154SDmytro Laktyushkin dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1125eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(dst_x_offset), 112686be9a04SYue Hin Lau param->h_scale_ratio)); 112786be9a04SYue Hin Lau 112839a9f4d8SDmytro Laktyushkin if (src_x_offset >= (int)param->viewport.width) 112986be9a04SYue Hin Lau cur_en = 0; /* not visible beyond right edge*/ 113086be9a04SYue Hin Lau 113135d13315SMartin Tsai if (src_x_offset + (int)hubp->curs_attr.width <= 0) 113286be9a04SYue Hin Lau cur_en = 0; /* not visible beyond left edge*/ 113386be9a04SYue Hin Lau 113494a4ffd1SGloria Li if (src_y_offset >= (int)param->viewport.height) 113594a4ffd1SGloria Li cur_en = 0; /* not visible beyond bottom edge*/ 113694a4ffd1SGloria Li 113794a4ffd1SGloria Li if (src_y_offset < 0) //+ (int)hubp->curs_attr.height 113894a4ffd1SGloria Li cur_en = 0; /* not visible beyond top edge*/ 113994a4ffd1SGloria Li 114086be9a04SYue Hin Lau if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 114136192e7eSEric Bernstein hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 114236192e7eSEric Bernstein 114386be9a04SYue Hin Lau REG_UPDATE(CURSOR_CONTROL, 114486be9a04SYue Hin Lau CURSOR_ENABLE, cur_en); 114586be9a04SYue Hin Lau 114686be9a04SYue Hin Lau REG_SET_2(CURSOR_POSITION, 0, 114786be9a04SYue Hin Lau CURSOR_X_POSITION, pos->x, 114886be9a04SYue Hin Lau CURSOR_Y_POSITION, pos->y); 114986be9a04SYue Hin Lau 115086be9a04SYue Hin Lau REG_SET_2(CURSOR_HOT_SPOT, 0, 115108ed681cSDmytro Laktyushkin CURSOR_HOT_SPOT_X, x_hotspot, 115208ed681cSDmytro Laktyushkin CURSOR_HOT_SPOT_Y, y_hotspot); 115386be9a04SYue Hin Lau 115486be9a04SYue Hin Lau REG_SET(CURSOR_DST_OFFSET, 0, 115586be9a04SYue Hin Lau CURSOR_DST_X_OFFSET, dst_x_offset); 115686be9a04SYue Hin Lau /* TODO Handle surface pixel formats other than 4:4:4 */ 115786be9a04SYue Hin Lau } 115886be9a04SYue Hin Lau 1159c8242b98SYongqiang Sun void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1160c8242b98SYongqiang Sun { 1161c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1162c8242b98SYongqiang Sun uint32_t clk_enable = enable ? 1 : 0; 1163c8242b98SYongqiang Sun 1164c8242b98SYongqiang Sun REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1165c8242b98SYongqiang Sun } 1166c8242b98SYongqiang Sun 1167c8242b98SYongqiang Sun void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1168c8242b98SYongqiang Sun { 1169c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1170c8242b98SYongqiang Sun 1171c8242b98SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1172c8242b98SYongqiang Sun } 1173c8242b98SYongqiang Sun 1174bd4e7250SHarry Wentland static const struct hubp_funcs dcn10_hubp_funcs = { 117586be9a04SYue Hin Lau .hubp_program_surface_flip_and_addr = 117686be9a04SYue Hin Lau hubp1_program_surface_flip_and_addr, 117786be9a04SYue Hin Lau .hubp_program_surface_config = 117886be9a04SYue Hin Lau hubp1_program_surface_config, 117986be9a04SYue Hin Lau .hubp_is_flip_pending = hubp1_is_flip_pending, 118086be9a04SYue Hin Lau .hubp_setup = hubp1_setup, 118186be9a04SYue Hin Lau .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 118286be9a04SYue Hin Lau .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 118386be9a04SYue Hin Lau .set_blank = hubp1_set_blank, 118486be9a04SYue Hin Lau .dcc_control = hubp1_dcc_control, 118586be9a04SYue Hin Lau .mem_program_viewport = min_set_viewport, 118686be9a04SYue Hin Lau .set_hubp_blank_en = hubp1_set_hubp_blank_en, 118786be9a04SYue Hin Lau .set_cursor_attributes = hubp1_cursor_set_attributes, 118886be9a04SYue Hin Lau .set_cursor_position = hubp1_cursor_set_position, 11891dbac201SYongqiang Sun .hubp_disconnect = hubp1_disconnect, 1190c8242b98SYongqiang Sun .hubp_clk_cntl = hubp1_clk_cntl, 1191c8242b98SYongqiang Sun .hubp_vtg_sel = hubp1_vtg_sel, 11920a93dc7fSDmytro Laktyushkin .hubp_read_state = hubp1_read_state, 11933ba43a59SCharlene Liu .hubp_disable_control = hubp1_disable_control, 11943ba43a59SCharlene Liu .hubp_get_underflow_status = hubp1_get_underflow_status, 11953ba43a59SCharlene Liu 119686be9a04SYue Hin Lau }; 119786be9a04SYue Hin Lau 119886be9a04SYue Hin Lau /*****************************************/ 119986be9a04SYue Hin Lau /* Constructor, Destructor */ 120086be9a04SYue Hin Lau /*****************************************/ 120186be9a04SYue Hin Lau 120286be9a04SYue Hin Lau void dcn10_hubp_construct( 120386be9a04SYue Hin Lau struct dcn10_hubp *hubp1, 120486be9a04SYue Hin Lau struct dc_context *ctx, 120586be9a04SYue Hin Lau uint32_t inst, 1206c42c275cSYue Hin Lau const struct dcn_mi_registers *hubp_regs, 1207c42c275cSYue Hin Lau const struct dcn_mi_shift *hubp_shift, 1208c42c275cSYue Hin Lau const struct dcn_mi_mask *hubp_mask) 120986be9a04SYue Hin Lau { 121086be9a04SYue Hin Lau hubp1->base.funcs = &dcn10_hubp_funcs; 121186be9a04SYue Hin Lau hubp1->base.ctx = ctx; 1212c42c275cSYue Hin Lau hubp1->hubp_regs = hubp_regs; 1213c42c275cSYue Hin Lau hubp1->hubp_shift = hubp_shift; 1214c42c275cSYue Hin Lau hubp1->hubp_mask = hubp_mask; 121586be9a04SYue Hin Lau hubp1->base.inst = inst; 121686be9a04SYue Hin Lau hubp1->base.opp_id = 0xf; 121786be9a04SYue Hin Lau hubp1->base.mpcc_id = 0xf; 121886be9a04SYue Hin Lau } 121986be9a04SYue Hin Lau 122086be9a04SYue Hin Lau 1221