186be9a04SYue Hin Lau /* 286be9a04SYue Hin Lau * Copyright 2012-15 Advanced Micro Devices, Inc. 386be9a04SYue Hin Lau * 486be9a04SYue Hin Lau * Permission is hereby granted, free of charge, to any person obtaining a 586be9a04SYue Hin Lau * copy of this software and associated documentation files (the "Software"), 686be9a04SYue Hin Lau * to deal in the Software without restriction, including without limitation 786be9a04SYue Hin Lau * the rights to use, copy, modify, merge, publish, distribute, sublicense, 886be9a04SYue Hin Lau * and/or sell copies of the Software, and to permit persons to whom the 986be9a04SYue Hin Lau * Software is furnished to do so, subject to the following conditions: 1086be9a04SYue Hin Lau * 1186be9a04SYue Hin Lau * The above copyright notice and this permission notice shall be included in 1286be9a04SYue Hin Lau * all copies or substantial portions of the Software. 1386be9a04SYue Hin Lau * 1486be9a04SYue Hin Lau * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1586be9a04SYue Hin Lau * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1686be9a04SYue Hin Lau * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1786be9a04SYue Hin Lau * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1886be9a04SYue Hin Lau * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1986be9a04SYue Hin Lau * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2086be9a04SYue Hin Lau * OTHER DEALINGS IN THE SOFTWARE. 2186be9a04SYue Hin Lau * 2286be9a04SYue Hin Lau * Authors: AMD 2386be9a04SYue Hin Lau * 2486be9a04SYue Hin Lau */ 2586be9a04SYue Hin Lau #include "dm_services.h" 2686be9a04SYue Hin Lau #include "dce_calcs.h" 2786be9a04SYue Hin Lau #include "reg_helper.h" 2886be9a04SYue Hin Lau #include "basics/conversion.h" 2986be9a04SYue Hin Lau #include "dcn10_hubp.h" 3086be9a04SYue Hin Lau 3186be9a04SYue Hin Lau #define REG(reg)\ 32c42c275cSYue Hin Lau hubp1->hubp_regs->reg 3386be9a04SYue Hin Lau 3486be9a04SYue Hin Lau #define CTX \ 3586be9a04SYue Hin Lau hubp1->base.ctx 3686be9a04SYue Hin Lau 3786be9a04SYue Hin Lau #undef FN 3886be9a04SYue Hin Lau #define FN(reg_name, field_name) \ 39c42c275cSYue Hin Lau hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 4086be9a04SYue Hin Lau 4186be9a04SYue Hin Lau void hubp1_set_blank(struct hubp *hubp, bool blank) 4286be9a04SYue Hin Lau { 4386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 4486be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 4586be9a04SYue Hin Lau 4675c2dec3STony Cheng REG_UPDATE_2(DCHUBP_CNTL, 4786be9a04SYue Hin Lau HUBP_BLANK_EN, blank_en, 4886be9a04SYue Hin Lau HUBP_TTU_DISABLE, blank_en); 4986be9a04SYue Hin Lau 5086be9a04SYue Hin Lau if (blank) { 5175c2dec3STony Cheng uint32_t reg_val = REG_READ(DCHUBP_CNTL); 5275c2dec3STony Cheng 53cc55b1f5STony Cheng if (reg_val) { 54cc55b1f5STony Cheng /* init sequence workaround: in case HUBP is 55cc55b1f5STony Cheng * power gated, this wait would timeout. 56cc55b1f5STony Cheng * 57cc55b1f5STony Cheng * we just wrote reg_val to non-0, if it stay 0 58cc55b1f5STony Cheng * it means HUBP is gated 59cc55b1f5STony Cheng */ 6086be9a04SYue Hin Lau REG_WAIT(DCHUBP_CNTL, 6186be9a04SYue Hin Lau HUBP_NO_OUTSTANDING_REQ, 1, 6286be9a04SYue Hin Lau 1, 200); 63cc55b1f5STony Cheng } 64cc55b1f5STony Cheng 6586be9a04SYue Hin Lau hubp->mpcc_id = 0xf; 66043f5bb6SWesley Chalmers hubp->opp_id = OPP_ID_INVALID; 6786be9a04SYue Hin Lau } 6886be9a04SYue Hin Lau } 6986be9a04SYue Hin Lau 701dbac201SYongqiang Sun static void hubp1_disconnect(struct hubp *hubp) 711dbac201SYongqiang Sun { 721dbac201SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 731dbac201SYongqiang Sun 741dbac201SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, 751dbac201SYongqiang Sun HUBP_TTU_DISABLE, 1); 765af9d013SEric Yang 775af9d013SEric Yang REG_UPDATE(CURSOR_CONTROL, 785af9d013SEric Yang CURSOR_ENABLE, 0); 791dbac201SYongqiang Sun } 801dbac201SYongqiang Sun 813ba43a59SCharlene Liu static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 823ba43a59SCharlene Liu { 833ba43a59SCharlene Liu struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 843ba43a59SCharlene Liu uint32_t disable = disable_hubp ? 1 : 0; 853ba43a59SCharlene Liu 863ba43a59SCharlene Liu REG_UPDATE(DCHUBP_CNTL, 873ba43a59SCharlene Liu HUBP_DISABLE, disable); 883ba43a59SCharlene Liu } 893ba43a59SCharlene Liu 903ba43a59SCharlene Liu static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 913ba43a59SCharlene Liu { 923ba43a59SCharlene Liu uint32_t hubp_underflow = 0; 933ba43a59SCharlene Liu struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 943ba43a59SCharlene Liu 953ba43a59SCharlene Liu REG_GET(DCHUBP_CNTL, 963ba43a59SCharlene Liu HUBP_UNDERFLOW_STATUS, 973ba43a59SCharlene Liu &hubp_underflow); 983ba43a59SCharlene Liu 993ba43a59SCharlene Liu return hubp_underflow; 1003ba43a59SCharlene Liu } 1013ba43a59SCharlene Liu 102eb6b29d6SJun Lei 103eb6b29d6SJun Lei void hubp1_clear_underflow(struct hubp *hubp) 104eb6b29d6SJun Lei { 105eb6b29d6SJun Lei struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106eb6b29d6SJun Lei 107eb6b29d6SJun Lei REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108eb6b29d6SJun Lei } 109eb6b29d6SJun Lei 11086be9a04SYue Hin Lau static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 11186be9a04SYue Hin Lau { 11286be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 11386be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 11486be9a04SYue Hin Lau 11586be9a04SYue Hin Lau REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 11686be9a04SYue Hin Lau } 11786be9a04SYue Hin Lau 11860a804c8SEric Bernstein void hubp1_vready_workaround(struct hubp *hubp, 11986be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 12086be9a04SYue Hin Lau { 12186be9a04SYue Hin Lau uint32_t value = 0; 12286be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 12386be9a04SYue Hin Lau 12486be9a04SYue Hin Lau /* set HBUBREQ_DEBUG_DB[12] = 1 */ 12586be9a04SYue Hin Lau value = REG_READ(HUBPREQ_DEBUG_DB); 12686be9a04SYue Hin Lau 12786be9a04SYue Hin Lau /* hack mode disable */ 12886be9a04SYue Hin Lau value |= 0x100; 12986be9a04SYue Hin Lau value &= ~0x1000; 13086be9a04SYue Hin Lau 13186be9a04SYue Hin Lau if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 13286be9a04SYue Hin Lau + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 13386be9a04SYue Hin Lau /* if (eco_fix_needed(otg_global_sync_timing) 13486be9a04SYue Hin Lau * set HBUBREQ_DEBUG_DB[12] = 1 */ 13586be9a04SYue Hin Lau value |= 0x1000; 13686be9a04SYue Hin Lau } 13786be9a04SYue Hin Lau 13886be9a04SYue Hin Lau REG_WRITE(HUBPREQ_DEBUG_DB, value); 13986be9a04SYue Hin Lau } 14086be9a04SYue Hin Lau 14186be9a04SYue Hin Lau void hubp1_program_tiling( 1424b8240bfSYue Hin Lau struct hubp *hubp, 14386be9a04SYue Hin Lau const union dc_tiling_info *info, 14486be9a04SYue Hin Lau const enum surface_pixel_format pixel_format) 14586be9a04SYue Hin Lau { 1464b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1474b8240bfSYue Hin Lau 14886be9a04SYue Hin Lau REG_UPDATE_6(DCSURF_ADDR_CONFIG, 14986be9a04SYue Hin Lau NUM_PIPES, log_2(info->gfx9.num_pipes), 15086be9a04SYue Hin Lau NUM_BANKS, log_2(info->gfx9.num_banks), 15186be9a04SYue Hin Lau PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 15286be9a04SYue Hin Lau NUM_SE, log_2(info->gfx9.num_shader_engines), 15386be9a04SYue Hin Lau NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 15486be9a04SYue Hin Lau MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 15586be9a04SYue Hin Lau 15686be9a04SYue Hin Lau REG_UPDATE_4(DCSURF_TILING_CONFIG, 15786be9a04SYue Hin Lau SW_MODE, info->gfx9.swizzle, 15886be9a04SYue Hin Lau META_LINEAR, info->gfx9.meta_linear, 15986be9a04SYue Hin Lau RB_ALIGNED, info->gfx9.rb_aligned, 16086be9a04SYue Hin Lau PIPE_ALIGNED, info->gfx9.pipe_aligned); 16186be9a04SYue Hin Lau } 16286be9a04SYue Hin Lau 163a9962fb8SEric Bernstein void hubp1_program_size( 1644b8240bfSYue Hin Lau struct hubp *hubp, 16586be9a04SYue Hin Lau enum surface_pixel_format format, 16612e2b2d4SDmytro Laktyushkin const struct plane_size *plane_size, 167a9962fb8SEric Bernstein struct dc_plane_dcc_param *dcc) 16886be9a04SYue Hin Lau { 1694b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 170a9962fb8SEric Bernstein uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 17186be9a04SYue Hin Lau 17286be9a04SYue Hin Lau /* Program data and meta surface pitch (calculation from addrlib) 17386be9a04SYue Hin Lau * 444 or 420 luma 17486be9a04SYue Hin Lau */ 175836758ffSZheng, XueLai(Eric) if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 17612e2b2d4SDmytro Laktyushkin ASSERT(plane_size->chroma_pitch != 0); 1778ec06a17SJulian Parkin /* Chroma pitch zero can cause system hang! */ 1788ec06a17SJulian Parkin 17912e2b2d4SDmytro Laktyushkin pitch = plane_size->surface_pitch - 1; 18012e2b2d4SDmytro Laktyushkin meta_pitch = dcc->meta_pitch - 1; 18112e2b2d4SDmytro Laktyushkin pitch_c = plane_size->chroma_pitch - 1; 18212e2b2d4SDmytro Laktyushkin meta_pitch_c = dcc->meta_pitch_c - 1; 18386be9a04SYue Hin Lau } else { 18412e2b2d4SDmytro Laktyushkin pitch = plane_size->surface_pitch - 1; 18512e2b2d4SDmytro Laktyushkin meta_pitch = dcc->meta_pitch - 1; 18686be9a04SYue Hin Lau pitch_c = 0; 18786be9a04SYue Hin Lau meta_pitch_c = 0; 18886be9a04SYue Hin Lau } 18986be9a04SYue Hin Lau 19086be9a04SYue Hin Lau if (!dcc->enable) { 19186be9a04SYue Hin Lau meta_pitch = 0; 19286be9a04SYue Hin Lau meta_pitch_c = 0; 19386be9a04SYue Hin Lau } 19486be9a04SYue Hin Lau 19586be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH, 19686be9a04SYue Hin Lau PITCH, pitch, META_PITCH, meta_pitch); 19786be9a04SYue Hin Lau 19886be9a04SYue Hin Lau if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 19986be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 20086be9a04SYue Hin Lau PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 201a9962fb8SEric Bernstein } 202a9962fb8SEric Bernstein 203a9962fb8SEric Bernstein void hubp1_program_rotation( 204a9962fb8SEric Bernstein struct hubp *hubp, 205a9962fb8SEric Bernstein enum dc_rotation_angle rotation, 206a9962fb8SEric Bernstein bool horizontal_mirror) 207a9962fb8SEric Bernstein { 208a9962fb8SEric Bernstein struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 209a9962fb8SEric Bernstein uint32_t mirror; 210a9962fb8SEric Bernstein 21186be9a04SYue Hin Lau 21286be9a04SYue Hin Lau if (horizontal_mirror) 21386be9a04SYue Hin Lau mirror = 1; 21486be9a04SYue Hin Lau else 21586be9a04SYue Hin Lau mirror = 0; 21686be9a04SYue Hin Lau 21786be9a04SYue Hin Lau /* Program rotation angle and horz mirror - no mirror */ 21886be9a04SYue Hin Lau if (rotation == ROTATION_ANGLE_0) 21986be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 22086be9a04SYue Hin Lau ROTATION_ANGLE, 0, 22186be9a04SYue Hin Lau H_MIRROR_EN, mirror); 22286be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_90) 22386be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 22486be9a04SYue Hin Lau ROTATION_ANGLE, 1, 22586be9a04SYue Hin Lau H_MIRROR_EN, mirror); 22686be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_180) 22786be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 22886be9a04SYue Hin Lau ROTATION_ANGLE, 2, 22986be9a04SYue Hin Lau H_MIRROR_EN, mirror); 23086be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_270) 23186be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 23286be9a04SYue Hin Lau ROTATION_ANGLE, 3, 23386be9a04SYue Hin Lau H_MIRROR_EN, mirror); 23486be9a04SYue Hin Lau } 23586be9a04SYue Hin Lau 23686be9a04SYue Hin Lau void hubp1_program_pixel_format( 2374b8240bfSYue Hin Lau struct hubp *hubp, 23886be9a04SYue Hin Lau enum surface_pixel_format format) 23986be9a04SYue Hin Lau { 2404b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 24186be9a04SYue Hin Lau uint32_t red_bar = 3; 24286be9a04SYue Hin Lau uint32_t blue_bar = 2; 24386be9a04SYue Hin Lau 24486be9a04SYue Hin Lau /* swap for ABGR format */ 24586be9a04SYue Hin Lau if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 24686be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 24786be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 24886be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 24986be9a04SYue Hin Lau red_bar = 2; 25086be9a04SYue Hin Lau blue_bar = 3; 25186be9a04SYue Hin Lau } 25286be9a04SYue Hin Lau 25386be9a04SYue Hin Lau REG_UPDATE_2(HUBPRET_CONTROL, 25486be9a04SYue Hin Lau CROSSBAR_SRC_CB_B, blue_bar, 25586be9a04SYue Hin Lau CROSSBAR_SRC_CR_R, red_bar); 25686be9a04SYue Hin Lau 25786be9a04SYue Hin Lau /* Mapping is same as ipp programming (cnvc) */ 25886be9a04SYue Hin Lau 25986be9a04SYue Hin Lau switch (format) { 26086be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 26186be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26286be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 1); 26386be9a04SYue Hin Lau break; 26486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 26586be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26686be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 3); 26786be9a04SYue Hin Lau break; 26886be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 26986be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 27086be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 27186be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 8); 27286be9a04SYue Hin Lau break; 27386be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 27486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 27586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 27686be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 27786be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 10); 27886be9a04SYue Hin Lau break; 27986be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 28086be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 28186be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 22); 28286be9a04SYue Hin Lau break; 28386be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 28486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 28586be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 28686be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 24); 28786be9a04SYue Hin Lau break; 28886be9a04SYue Hin Lau 28986be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 29086be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 29186be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 65); 29286be9a04SYue Hin Lau break; 29386be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 29486be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 29586be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 64); 29686be9a04SYue Hin Lau break; 29786be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 29886be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 29986be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 67); 30086be9a04SYue Hin Lau break; 30186be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 30286be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 30386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 66); 30486be9a04SYue Hin Lau break; 3053fc9fc4cSvikrant mhaske case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 3063fc9fc4cSvikrant mhaske REG_UPDATE(DCSURF_SURFACE_CONFIG, 3073fc9fc4cSvikrant mhaske SURFACE_PIXEL_FORMAT, 12); 3083fc9fc4cSvikrant mhaske break; 309bbeb64d0SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 310bbeb64d0SHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 311bbeb64d0SHarry Wentland REG_UPDATE(DCSURF_SURFACE_CONFIG, 312bbeb64d0SHarry Wentland SURFACE_PIXEL_FORMAT, 112); 313bbeb64d0SHarry Wentland break; 314bbeb64d0SHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 315bbeb64d0SHarry Wentland REG_UPDATE(DCSURF_SURFACE_CONFIG, 316bbeb64d0SHarry Wentland SURFACE_PIXEL_FORMAT, 113); 317bbeb64d0SHarry Wentland break; 318bbeb64d0SHarry Wentland case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 319bbeb64d0SHarry Wentland REG_UPDATE(DCSURF_SURFACE_CONFIG, 320bbeb64d0SHarry Wentland SURFACE_PIXEL_FORMAT, 114); 321bbeb64d0SHarry Wentland break; 322bbeb64d0SHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 323bbeb64d0SHarry Wentland REG_UPDATE(DCSURF_SURFACE_CONFIG, 324bbeb64d0SHarry Wentland SURFACE_PIXEL_FORMAT, 118); 325bbeb64d0SHarry Wentland break; 326bbeb64d0SHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 327bbeb64d0SHarry Wentland REG_UPDATE(DCSURF_SURFACE_CONFIG, 328bbeb64d0SHarry Wentland SURFACE_PIXEL_FORMAT, 119); 329bbeb64d0SHarry Wentland break; 330bbeb64d0SHarry Wentland #endif 33186be9a04SYue Hin Lau default: 33286be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 33386be9a04SYue Hin Lau break; 33486be9a04SYue Hin Lau } 33586be9a04SYue Hin Lau 33686be9a04SYue Hin Lau /* don't see the need of program the xbar in DCN 1.0 */ 33786be9a04SYue Hin Lau } 33886be9a04SYue Hin Lau 33986be9a04SYue Hin Lau bool hubp1_program_surface_flip_and_addr( 34086be9a04SYue Hin Lau struct hubp *hubp, 34186be9a04SYue Hin Lau const struct dc_plane_address *address, 342bda9afdaSDmytro Laktyushkin bool flip_immediate) 34386be9a04SYue Hin Lau { 34486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 34586be9a04SYue Hin Lau 3461336926fSAlvin lee 3471336926fSAlvin lee //program flip type 3481336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, 34986be9a04SYue Hin Lau SURFACE_FLIP_TYPE, flip_immediate); 35086be9a04SYue Hin Lau 3511336926fSAlvin lee 3521336926fSAlvin lee if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 3531336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 3541336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 3551336926fSAlvin lee 3561336926fSAlvin lee } else { 3571336926fSAlvin lee // turn off stereo if not in stereo 3581336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 3591336926fSAlvin lee REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 3601336926fSAlvin lee } 3611336926fSAlvin lee 3621336926fSAlvin lee 3631336926fSAlvin lee 36486be9a04SYue Hin Lau /* HW automatically latch rest of address register on write to 36586be9a04SYue Hin Lau * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 36686be9a04SYue Hin Lau * 36786be9a04SYue Hin Lau * program high first and then the low addr, order matters! 36886be9a04SYue Hin Lau */ 36986be9a04SYue Hin Lau switch (address->type) { 37086be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRAPHICS: 37186be9a04SYue Hin Lau /* DCN1.0 does not support const color 37286be9a04SYue Hin Lau * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 37386be9a04SYue Hin Lau * base on address->grph.dcc_const_color 37486be9a04SYue Hin Lau * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 37586be9a04SYue Hin Lau * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 37686be9a04SYue Hin Lau */ 37786be9a04SYue Hin Lau 37886be9a04SYue Hin Lau if (address->grph.addr.quad_part == 0) 37986be9a04SYue Hin Lau break; 38086be9a04SYue Hin Lau 381cf8c19a3SYongqiang Sun REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 382cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 383cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 38486be9a04SYue Hin Lau 38586be9a04SYue Hin Lau if (address->grph.meta_addr.quad_part != 0) { 38686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 38786be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 38886be9a04SYue Hin Lau address->grph.meta_addr.high_part); 38986be9a04SYue Hin Lau 39086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 39186be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 39286be9a04SYue Hin Lau address->grph.meta_addr.low_part); 39386be9a04SYue Hin Lau } 39486be9a04SYue Hin Lau 39586be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 39686be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 39786be9a04SYue Hin Lau address->grph.addr.high_part); 39886be9a04SYue Hin Lau 39986be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 40086be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 40186be9a04SYue Hin Lau address->grph.addr.low_part); 40286be9a04SYue Hin Lau break; 40386be9a04SYue Hin Lau case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 40486be9a04SYue Hin Lau if (address->video_progressive.luma_addr.quad_part == 0 40586be9a04SYue Hin Lau || address->video_progressive.chroma_addr.quad_part == 0) 40686be9a04SYue Hin Lau break; 40786be9a04SYue Hin Lau 408cf8c19a3SYongqiang Sun REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 409cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 410cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 411cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 412cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 41386be9a04SYue Hin Lau 41486be9a04SYue Hin Lau if (address->video_progressive.luma_meta_addr.quad_part != 0) { 41586be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 41686be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 41786be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.high_part); 41886be9a04SYue Hin Lau 41986be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 42086be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_C, 42186be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.low_part); 42286be9a04SYue Hin Lau 42386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 42486be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 42586be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.high_part); 42686be9a04SYue Hin Lau 42786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 42886be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 42986be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.low_part); 43086be9a04SYue Hin Lau } 43186be9a04SYue Hin Lau 43286be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 43386be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH_C, 43486be9a04SYue Hin Lau address->video_progressive.chroma_addr.high_part); 43586be9a04SYue Hin Lau 43686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 43786be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_C, 43886be9a04SYue Hin Lau address->video_progressive.chroma_addr.low_part); 43986be9a04SYue Hin Lau 44086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 44186be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 44286be9a04SYue Hin Lau address->video_progressive.luma_addr.high_part); 44386be9a04SYue Hin Lau 44486be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 44586be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 44686be9a04SYue Hin Lau address->video_progressive.luma_addr.low_part); 44786be9a04SYue Hin Lau break; 44886be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRPH_STEREO: 44986be9a04SYue Hin Lau if (address->grph_stereo.left_addr.quad_part == 0) 45086be9a04SYue Hin Lau break; 45186be9a04SYue Hin Lau if (address->grph_stereo.right_addr.quad_part == 0) 45286be9a04SYue Hin Lau break; 45386be9a04SYue Hin Lau 454aa6d4a59SEric Bernstein REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 455cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 456cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 457cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 458aa6d4a59SEric Bernstein PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 459aa6d4a59SEric Bernstein SECONDARY_SURFACE_TMZ, address->tmz_surface, 460aa6d4a59SEric Bernstein SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 461aa6d4a59SEric Bernstein SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 462aa6d4a59SEric Bernstein SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 46386be9a04SYue Hin Lau 46486be9a04SYue Hin Lau if (address->grph_stereo.right_meta_addr.quad_part != 0) { 46586be9a04SYue Hin Lau 46686be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 46786be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS_HIGH, 46886be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.high_part); 46986be9a04SYue Hin Lau 47086be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 47186be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS, 47286be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.low_part); 47386be9a04SYue Hin Lau } 47486be9a04SYue Hin Lau if (address->grph_stereo.left_meta_addr.quad_part != 0) { 47586be9a04SYue Hin Lau 47686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 47786be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 47886be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.high_part); 47986be9a04SYue Hin Lau 48086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 48186be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 48286be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.low_part); 48386be9a04SYue Hin Lau } 48486be9a04SYue Hin Lau 48586be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 48686be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS_HIGH, 48786be9a04SYue Hin Lau address->grph_stereo.right_addr.high_part); 48886be9a04SYue Hin Lau 48986be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 49086be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS, 49186be9a04SYue Hin Lau address->grph_stereo.right_addr.low_part); 49286be9a04SYue Hin Lau 49386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 49486be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 49586be9a04SYue Hin Lau address->grph_stereo.left_addr.high_part); 49686be9a04SYue Hin Lau 49786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 49886be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 49986be9a04SYue Hin Lau address->grph_stereo.left_addr.low_part); 50086be9a04SYue Hin Lau break; 50186be9a04SYue Hin Lau default: 50286be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 50386be9a04SYue Hin Lau break; 50486be9a04SYue Hin Lau } 50586be9a04SYue Hin Lau 50686be9a04SYue Hin Lau hubp->request_address = *address; 50786be9a04SYue Hin Lau 50886be9a04SYue Hin Lau return true; 50986be9a04SYue Hin Lau } 51086be9a04SYue Hin Lau 51186be9a04SYue Hin Lau void hubp1_dcc_control(struct hubp *hubp, bool enable, 5122c58cc6dSIlya Bakoulin enum hubp_ind_block_size independent_64b_blks) 51386be9a04SYue Hin Lau { 51486be9a04SYue Hin Lau uint32_t dcc_en = enable ? 1 : 0; 51586be9a04SYue Hin Lau uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 51686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 51786be9a04SYue Hin Lau 518aa6d4a59SEric Bernstein REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 51986be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, dcc_en, 520aa6d4a59SEric Bernstein PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 521aa6d4a59SEric Bernstein SECONDARY_SURFACE_DCC_EN, dcc_en, 522aa6d4a59SEric Bernstein SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 52386be9a04SYue Hin Lau } 52486be9a04SYue Hin Lau 52586be9a04SYue Hin Lau void hubp1_program_surface_config( 52686be9a04SYue Hin Lau struct hubp *hubp, 52786be9a04SYue Hin Lau enum surface_pixel_format format, 52886be9a04SYue Hin Lau union dc_tiling_info *tiling_info, 52912e2b2d4SDmytro Laktyushkin struct plane_size *plane_size, 53086be9a04SYue Hin Lau enum dc_rotation_angle rotation, 53186be9a04SYue Hin Lau struct dc_plane_dcc_param *dcc, 532a465feaeSCharlene Liu bool horizontal_mirror, 533a465feaeSCharlene Liu unsigned int compat_level) 53486be9a04SYue Hin Lau { 53512e2b2d4SDmytro Laktyushkin hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 5364b8240bfSYue Hin Lau hubp1_program_tiling(hubp, tiling_info, format); 537a9962fb8SEric Bernstein hubp1_program_size(hubp, format, plane_size, dcc); 538a9962fb8SEric Bernstein hubp1_program_rotation(hubp, rotation, horizontal_mirror); 5394b8240bfSYue Hin Lau hubp1_program_pixel_format(hubp, format); 54086be9a04SYue Hin Lau } 54186be9a04SYue Hin Lau 54286be9a04SYue Hin Lau void hubp1_program_requestor( 54386be9a04SYue Hin Lau struct hubp *hubp, 54486be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs) 54586be9a04SYue Hin Lau { 54686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 54786be9a04SYue Hin Lau 54886be9a04SYue Hin Lau REG_UPDATE(HUBPRET_CONTROL, 54986be9a04SYue Hin Lau DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 55086be9a04SYue Hin Lau REG_SET_4(DCN_EXPANSION_MODE, 0, 55186be9a04SYue Hin Lau DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 55286be9a04SYue Hin Lau PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 55386be9a04SYue Hin Lau MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 55486be9a04SYue Hin Lau CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 55586be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 55686be9a04SYue Hin Lau CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 55786be9a04SYue Hin Lau MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 55886be9a04SYue Hin Lau META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 55986be9a04SYue Hin Lau MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 56086be9a04SYue Hin Lau DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 56186be9a04SYue Hin Lau MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 56286be9a04SYue Hin Lau SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 56386be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 56486be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 56586be9a04SYue Hin Lau CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 56686be9a04SYue Hin Lau MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 56786be9a04SYue Hin Lau META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 56886be9a04SYue Hin Lau MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 56986be9a04SYue Hin Lau DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 57086be9a04SYue Hin Lau MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 57186be9a04SYue Hin Lau SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 57286be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 57386be9a04SYue Hin Lau } 57486be9a04SYue Hin Lau 57586be9a04SYue Hin Lau 57686be9a04SYue Hin Lau void hubp1_program_deadline( 57786be9a04SYue Hin Lau struct hubp *hubp, 57886be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 57986be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 58086be9a04SYue Hin Lau { 58186be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 58286be9a04SYue Hin Lau 58386be9a04SYue Hin Lau /* DLG - Per hubp */ 58486be9a04SYue Hin Lau REG_SET_2(BLANK_OFFSET_0, 0, 58586be9a04SYue Hin Lau REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 58686be9a04SYue Hin Lau DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 58786be9a04SYue Hin Lau 58886be9a04SYue Hin Lau REG_SET(BLANK_OFFSET_1, 0, 58986be9a04SYue Hin Lau MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 59086be9a04SYue Hin Lau 59186be9a04SYue Hin Lau REG_SET(DST_DIMENSIONS, 0, 59286be9a04SYue Hin Lau REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 59386be9a04SYue Hin Lau 59486be9a04SYue Hin Lau REG_SET_2(DST_AFTER_SCALER, 0, 59586be9a04SYue Hin Lau REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 59686be9a04SYue Hin Lau DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 59786be9a04SYue Hin Lau 59886be9a04SYue Hin Lau REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 59986be9a04SYue Hin Lau REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 60086be9a04SYue Hin Lau 60186be9a04SYue Hin Lau /* DLG - Per luma/chroma */ 60286be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_1, 0, 60386be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 60486be9a04SYue Hin Lau 605b552204bSNikola Cornij if (REG(NOM_PARAMETERS_0)) 60686be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_0, 0, 60786be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 60886be9a04SYue Hin Lau 609b552204bSNikola Cornij if (REG(NOM_PARAMETERS_1)) 61086be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_1, 0, 61186be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 61286be9a04SYue Hin Lau 61386be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_4, 0, 61486be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 61586be9a04SYue Hin Lau 61686be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_5, 0, 61786be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 61886be9a04SYue Hin Lau 61986be9a04SYue Hin Lau REG_SET_2(PER_LINE_DELIVERY, 0, 62086be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 62186be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 62286be9a04SYue Hin Lau 62386be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_2, 0, 62486be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 62586be9a04SYue Hin Lau 626b552204bSNikola Cornij if (REG(NOM_PARAMETERS_2)) 62786be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_2, 0, 62886be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 62986be9a04SYue Hin Lau 630b552204bSNikola Cornij if (REG(NOM_PARAMETERS_3)) 63186be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_3, 0, 63286be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 63386be9a04SYue Hin Lau 63486be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_6, 0, 63586be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 63686be9a04SYue Hin Lau 63786be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_7, 0, 63886be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 63986be9a04SYue Hin Lau 64086be9a04SYue Hin Lau /* TTU - per hubp */ 64186be9a04SYue Hin Lau REG_SET_2(DCN_TTU_QOS_WM, 0, 64286be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 64386be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 64486be9a04SYue Hin Lau 64586be9a04SYue Hin Lau /* TTU - per luma/chroma */ 64686be9a04SYue Hin Lau /* Assumed surf0 is luma and 1 is chroma */ 64786be9a04SYue Hin Lau 64886be9a04SYue Hin Lau REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 64986be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 65086be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 65186be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 65286be9a04SYue Hin Lau 65386be9a04SYue Hin Lau REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 65486be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 65586be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 65686be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 65786be9a04SYue Hin Lau 658c0aceb7dSCharlene Liu REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 659c0aceb7dSCharlene Liu REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 660c0aceb7dSCharlene Liu QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 661c0aceb7dSCharlene Liu QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 66286be9a04SYue Hin Lau } 66386be9a04SYue Hin Lau 66486be9a04SYue Hin Lau static void hubp1_setup( 66586be9a04SYue Hin Lau struct hubp *hubp, 66686be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 66786be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 66886be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs, 66986be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 67086be9a04SYue Hin Lau { 67186be9a04SYue Hin Lau /* otg is locked when this func is called. Register are double buffered. 67286be9a04SYue Hin Lau * disable the requestors is not needed 67386be9a04SYue Hin Lau */ 67486be9a04SYue Hin Lau hubp1_program_requestor(hubp, rq_regs); 67586be9a04SYue Hin Lau hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 67686be9a04SYue Hin Lau hubp1_vready_workaround(hubp, pipe_dest); 67786be9a04SYue Hin Lau } 67886be9a04SYue Hin Lau 6791a1adf17SDmytro Laktyushkin static void hubp1_setup_interdependent( 6801a1adf17SDmytro Laktyushkin struct hubp *hubp, 6811a1adf17SDmytro Laktyushkin struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 6821a1adf17SDmytro Laktyushkin struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 6831a1adf17SDmytro Laktyushkin { 6841a1adf17SDmytro Laktyushkin struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 6851a1adf17SDmytro Laktyushkin 6861a1adf17SDmytro Laktyushkin REG_SET_2(PREFETCH_SETTINS, 0, 6871a1adf17SDmytro Laktyushkin DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 6881a1adf17SDmytro Laktyushkin VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 6891a1adf17SDmytro Laktyushkin 6901a1adf17SDmytro Laktyushkin REG_SET(PREFETCH_SETTINS_C, 0, 6911a1adf17SDmytro Laktyushkin VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 6921a1adf17SDmytro Laktyushkin 6931a1adf17SDmytro Laktyushkin REG_SET_2(VBLANK_PARAMETERS_0, 0, 6941a1adf17SDmytro Laktyushkin DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 6951a1adf17SDmytro Laktyushkin DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 6961a1adf17SDmytro Laktyushkin 6971a1adf17SDmytro Laktyushkin REG_SET(VBLANK_PARAMETERS_3, 0, 6981a1adf17SDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 6991a1adf17SDmytro Laktyushkin 7001a1adf17SDmytro Laktyushkin REG_SET(VBLANK_PARAMETERS_4, 0, 7011a1adf17SDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 7021a1adf17SDmytro Laktyushkin 7031a1adf17SDmytro Laktyushkin REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 7041a1adf17SDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 7051a1adf17SDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 7061a1adf17SDmytro Laktyushkin 7071a1adf17SDmytro Laktyushkin REG_SET(DCN_SURF0_TTU_CNTL1, 0, 7081a1adf17SDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 7091a1adf17SDmytro Laktyushkin ttu_attr->refcyc_per_req_delivery_pre_l); 7101a1adf17SDmytro Laktyushkin REG_SET(DCN_SURF1_TTU_CNTL1, 0, 7111a1adf17SDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 7121a1adf17SDmytro Laktyushkin ttu_attr->refcyc_per_req_delivery_pre_c); 7131a1adf17SDmytro Laktyushkin REG_SET(DCN_CUR0_TTU_CNTL1, 0, 7141a1adf17SDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 7151a1adf17SDmytro Laktyushkin 7161a1adf17SDmytro Laktyushkin REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 7171a1adf17SDmytro Laktyushkin MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 7181a1adf17SDmytro Laktyushkin QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 7191a1adf17SDmytro Laktyushkin } 7201a1adf17SDmytro Laktyushkin 72186be9a04SYue Hin Lau bool hubp1_is_flip_pending(struct hubp *hubp) 72286be9a04SYue Hin Lau { 72386be9a04SYue Hin Lau uint32_t flip_pending = 0; 72486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 72586be9a04SYue Hin Lau struct dc_plane_address earliest_inuse_address; 72686be9a04SYue Hin Lau 72786be9a04SYue Hin Lau REG_GET(DCSURF_FLIP_CONTROL, 72886be9a04SYue Hin Lau SURFACE_FLIP_PENDING, &flip_pending); 72986be9a04SYue Hin Lau 73086be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 73186be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 73286be9a04SYue Hin Lau 73386be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 73486be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 73586be9a04SYue Hin Lau 73686be9a04SYue Hin Lau if (flip_pending) 73786be9a04SYue Hin Lau return true; 73886be9a04SYue Hin Lau 73986be9a04SYue Hin Lau if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 74086be9a04SYue Hin Lau return true; 74186be9a04SYue Hin Lau 74286be9a04SYue Hin Lau return false; 74386be9a04SYue Hin Lau } 74486be9a04SYue Hin Lau 74586be9a04SYue Hin Lau uint32_t aperture_default_system = 1; 74686be9a04SYue Hin Lau uint32_t context0_default_system; /* = 0;*/ 74786be9a04SYue Hin Lau 74886be9a04SYue Hin Lau static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 74986be9a04SYue Hin Lau struct vm_system_aperture_param *apt) 75086be9a04SYue Hin Lau { 75186be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 75286be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 75386be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 75486be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 75586be9a04SYue Hin Lau 75686be9a04SYue Hin Lau mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 75786be9a04SYue Hin Lau mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 75886be9a04SYue Hin Lau mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 75986be9a04SYue Hin Lau 76086be9a04SYue Hin Lau REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 76186be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 76286be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 76386be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 76486be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 76586be9a04SYue Hin Lau 76686be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 76786be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 76886be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 76986be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 77086be9a04SYue Hin Lau 77186be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 77286be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 77386be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 77486be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 77586be9a04SYue Hin Lau } 77686be9a04SYue Hin Lau 77786be9a04SYue Hin Lau static void hubp1_set_vm_context0_settings(struct hubp *hubp, 77886be9a04SYue Hin Lau const struct vm_context0_param *vm0) 77986be9a04SYue Hin Lau { 78086be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 78186be9a04SYue Hin Lau /* pte base */ 78286be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 78386be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 78486be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 78586be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 78686be9a04SYue Hin Lau 78786be9a04SYue Hin Lau /* pte start */ 78886be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 78986be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 79086be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 79186be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 79286be9a04SYue Hin Lau 79386be9a04SYue Hin Lau /* pte end */ 79486be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 79586be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 79686be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 79786be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 79886be9a04SYue Hin Lau 79986be9a04SYue Hin Lau /* fault handling */ 80086be9a04SYue Hin Lau REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 80186be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 80286be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 80386be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 80486be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 80586be9a04SYue Hin Lau 80686be9a04SYue Hin Lau /* control: enable VM PTE*/ 80786be9a04SYue Hin Lau REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 80886be9a04SYue Hin Lau ENABLE_L1_TLB, 1, 80986be9a04SYue Hin Lau SYSTEM_ACCESS_MODE, 3); 81086be9a04SYue Hin Lau } 81186be9a04SYue Hin Lau 81286be9a04SYue Hin Lau void min_set_viewport( 81386be9a04SYue Hin Lau struct hubp *hubp, 81486be9a04SYue Hin Lau const struct rect *viewport, 81586be9a04SYue Hin Lau const struct rect *viewport_c) 81686be9a04SYue Hin Lau { 81786be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 81886be9a04SYue Hin Lau 81986be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 82086be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, viewport->width, 82186be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, viewport->height); 82286be9a04SYue Hin Lau 82386be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 82486be9a04SYue Hin Lau PRI_VIEWPORT_X_START, viewport->x, 82586be9a04SYue Hin Lau PRI_VIEWPORT_Y_START, viewport->y); 82686be9a04SYue Hin Lau 82786be9a04SYue Hin Lau /*for stereo*/ 82886be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 82986be9a04SYue Hin Lau SEC_VIEWPORT_WIDTH, viewport->width, 83086be9a04SYue Hin Lau SEC_VIEWPORT_HEIGHT, viewport->height); 83186be9a04SYue Hin Lau 83286be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 83386be9a04SYue Hin Lau SEC_VIEWPORT_X_START, viewport->x, 83486be9a04SYue Hin Lau SEC_VIEWPORT_Y_START, viewport->y); 83586be9a04SYue Hin Lau 83686be9a04SYue Hin Lau /* DC supports NV12 only at the moment */ 83786be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 83886be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH_C, viewport_c->width, 83986be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 84086be9a04SYue Hin Lau 84186be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 84286be9a04SYue Hin Lau PRI_VIEWPORT_X_START_C, viewport_c->x, 84386be9a04SYue Hin Lau PRI_VIEWPORT_Y_START_C, viewport_c->y); 844132dade1SIlya Bakoulin 845132dade1SIlya Bakoulin REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 846132dade1SIlya Bakoulin SEC_VIEWPORT_WIDTH_C, viewport_c->width, 847132dade1SIlya Bakoulin SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 848132dade1SIlya Bakoulin 849132dade1SIlya Bakoulin REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 850132dade1SIlya Bakoulin SEC_VIEWPORT_X_START_C, viewport_c->x, 851132dade1SIlya Bakoulin SEC_VIEWPORT_Y_START_C, viewport_c->y); 85286be9a04SYue Hin Lau } 85386be9a04SYue Hin Lau 854c70b4016SCharlene Liu void hubp1_read_state_common(struct hubp *hubp) 85586be9a04SYue Hin Lau { 8560a93dc7fSDmytro Laktyushkin struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 85734cb6b38SDmytro Laktyushkin struct dcn_hubp_state *s = &hubp1->state; 8580a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 8590a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 8600a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 8610a93dc7fSDmytro Laktyushkin 8620a93dc7fSDmytro Laktyushkin /* Requester */ 8630a93dc7fSDmytro Laktyushkin REG_GET(HUBPRET_CONTROL, 8640a93dc7fSDmytro Laktyushkin DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 8650a93dc7fSDmytro Laktyushkin REG_GET_4(DCN_EXPANSION_MODE, 8660a93dc7fSDmytro Laktyushkin DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 8670a93dc7fSDmytro Laktyushkin PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 8680a93dc7fSDmytro Laktyushkin MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 8690a93dc7fSDmytro Laktyushkin CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 8700a93dc7fSDmytro Laktyushkin 8710a93dc7fSDmytro Laktyushkin /* DLG - Per hubp */ 8720a93dc7fSDmytro Laktyushkin REG_GET_2(BLANK_OFFSET_0, 8730a93dc7fSDmytro Laktyushkin REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 8740a93dc7fSDmytro Laktyushkin DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 8750a93dc7fSDmytro Laktyushkin 8760a93dc7fSDmytro Laktyushkin REG_GET(BLANK_OFFSET_1, 8770a93dc7fSDmytro Laktyushkin MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 8780a93dc7fSDmytro Laktyushkin 8790a93dc7fSDmytro Laktyushkin REG_GET(DST_DIMENSIONS, 8800a93dc7fSDmytro Laktyushkin REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 8810a93dc7fSDmytro Laktyushkin 8820a93dc7fSDmytro Laktyushkin REG_GET_2(DST_AFTER_SCALER, 8830a93dc7fSDmytro Laktyushkin REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 8840a93dc7fSDmytro Laktyushkin DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 8850a93dc7fSDmytro Laktyushkin 8860a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS)) 8870a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINS, 8880a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8890a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8900a93dc7fSDmytro Laktyushkin else 8910a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINGS, 8920a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8930a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8940a93dc7fSDmytro Laktyushkin 8950a93dc7fSDmytro Laktyushkin REG_GET_2(VBLANK_PARAMETERS_0, 8960a93dc7fSDmytro Laktyushkin DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 8970a93dc7fSDmytro Laktyushkin DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 8980a93dc7fSDmytro Laktyushkin 8990a93dc7fSDmytro Laktyushkin REG_GET(REF_FREQ_TO_PIX_FREQ, 9000a93dc7fSDmytro Laktyushkin REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 9010a93dc7fSDmytro Laktyushkin 9020a93dc7fSDmytro Laktyushkin /* DLG - Per luma/chroma */ 9030a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_1, 9040a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 9050a93dc7fSDmytro Laktyushkin 9060a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_3, 9070a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 9080a93dc7fSDmytro Laktyushkin 9090a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_0)) 9100a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_0, 9110a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 9120a93dc7fSDmytro Laktyushkin 9130a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_1)) 9140a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_1, 9150a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 9160a93dc7fSDmytro Laktyushkin 9170a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_4, 9180a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 9190a93dc7fSDmytro Laktyushkin 9200a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_5, 9210a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 9220a93dc7fSDmytro Laktyushkin 9230a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY_PRE, 9240a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 9250a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 9260a93dc7fSDmytro Laktyushkin 9270a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY, 9280a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 9290a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 9300a93dc7fSDmytro Laktyushkin 9310a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS_C)) 9320a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINS_C, 9330a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 9340a93dc7fSDmytro Laktyushkin else 9350a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINGS_C, 9360a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 9370a93dc7fSDmytro Laktyushkin 9380a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_2, 9390a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 9400a93dc7fSDmytro Laktyushkin 9410a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_4, 9420a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 9430a93dc7fSDmytro Laktyushkin 9440a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_2)) 9450a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_2, 9460a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 9470a93dc7fSDmytro Laktyushkin 9480a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_3)) 9490a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_3, 9500a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 9510a93dc7fSDmytro Laktyushkin 9520a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_6, 9530a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 9540a93dc7fSDmytro Laktyushkin 9550a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_7, 9560a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 9570a93dc7fSDmytro Laktyushkin 9580a93dc7fSDmytro Laktyushkin /* TTU - per hubp */ 9590a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_TTU_QOS_WM, 9600a93dc7fSDmytro Laktyushkin QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 9610a93dc7fSDmytro Laktyushkin QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 9620a93dc7fSDmytro Laktyushkin 9630a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_GLOBAL_TTU_CNTL, 9640a93dc7fSDmytro Laktyushkin MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 9650a93dc7fSDmytro Laktyushkin QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 9660a93dc7fSDmytro Laktyushkin 9670a93dc7fSDmytro Laktyushkin /* TTU - per luma/chroma */ 9680a93dc7fSDmytro Laktyushkin /* Assumed surf0 is luma and 1 is chroma */ 9690a93dc7fSDmytro Laktyushkin 9700a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF0_TTU_CNTL0, 9710a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 9720a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 9730a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 9740a93dc7fSDmytro Laktyushkin 9750a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF0_TTU_CNTL1, 9760a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9770a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_l); 9780a93dc7fSDmytro Laktyushkin 9790a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF1_TTU_CNTL0, 9800a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 9810a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 9820a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 9830a93dc7fSDmytro Laktyushkin 9840a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF1_TTU_CNTL1, 9850a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9860a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_c); 9870a93dc7fSDmytro Laktyushkin 9880a93dc7fSDmytro Laktyushkin /* Rest of hubp */ 98986be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONFIG, 99086be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, &s->pixel_format); 99186be9a04SYue Hin Lau 99286be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 99386be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 99486be9a04SYue Hin Lau 995afd0384cSJun Lei REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 996afd0384cSJun Lei SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 997afd0384cSJun Lei 99886be9a04SYue Hin Lau REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 99986be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, &s->viewport_width, 100086be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, &s->viewport_height); 100186be9a04SYue Hin Lau 100286be9a04SYue Hin Lau REG_GET_2(DCSURF_SURFACE_CONFIG, 100386be9a04SYue Hin Lau ROTATION_ANGLE, &s->rotation_angle, 100486be9a04SYue Hin Lau H_MIRROR_EN, &s->h_mirror_en); 100586be9a04SYue Hin Lau 100686be9a04SYue Hin Lau REG_GET(DCSURF_TILING_CONFIG, 100786be9a04SYue Hin Lau SW_MODE, &s->sw_mode); 100886be9a04SYue Hin Lau 100986be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONTROL, 101086be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 101186be9a04SYue Hin Lau 101286be9a04SYue Hin Lau REG_GET_3(DCHUBP_CNTL, 101386be9a04SYue Hin Lau HUBP_BLANK_EN, &s->blank_en, 101486be9a04SYue Hin Lau HUBP_TTU_DISABLE, &s->ttu_disable, 101586be9a04SYue Hin Lau HUBP_UNDERFLOW_STATUS, &s->underflow_status); 101686be9a04SYue Hin Lau 101786be9a04SYue Hin Lau REG_GET(DCN_GLOBAL_TTU_CNTL, 101886be9a04SYue Hin Lau MIN_TTU_VBLANK, &s->min_ttu_vblank); 101986be9a04SYue Hin Lau 102086be9a04SYue Hin Lau REG_GET_2(DCN_TTU_QOS_WM, 102186be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 102286be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1023c70b4016SCharlene Liu 102486be9a04SYue Hin Lau } 102586be9a04SYue Hin Lau 1026c70b4016SCharlene Liu void hubp1_read_state(struct hubp *hubp) 1027c70b4016SCharlene Liu { 1028c70b4016SCharlene Liu struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1029c70b4016SCharlene Liu struct dcn_hubp_state *s = &hubp1->state; 1030c70b4016SCharlene Liu struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1031c70b4016SCharlene Liu 1032c70b4016SCharlene Liu hubp1_read_state_common(hubp); 1033c70b4016SCharlene Liu 1034c70b4016SCharlene Liu REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1035c70b4016SCharlene Liu CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1036c70b4016SCharlene Liu MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1037c70b4016SCharlene Liu META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1038c70b4016SCharlene Liu MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1039c70b4016SCharlene Liu DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1040c70b4016SCharlene Liu MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1041c70b4016SCharlene Liu SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1042c70b4016SCharlene Liu PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1043c70b4016SCharlene Liu 1044c70b4016SCharlene Liu REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1045c70b4016SCharlene Liu CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1046c70b4016SCharlene Liu MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1047c70b4016SCharlene Liu META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1048c70b4016SCharlene Liu MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1049c70b4016SCharlene Liu DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1050c70b4016SCharlene Liu MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1051c70b4016SCharlene Liu SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1052c70b4016SCharlene Liu PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1053c70b4016SCharlene Liu 1054c70b4016SCharlene Liu } 105536192e7eSEric Bernstein enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 105686be9a04SYue Hin Lau { 105786be9a04SYue Hin Lau enum cursor_pitch hw_pitch; 105886be9a04SYue Hin Lau 105986be9a04SYue Hin Lau switch (pitch) { 106086be9a04SYue Hin Lau case 64: 106186be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 106286be9a04SYue Hin Lau break; 106386be9a04SYue Hin Lau case 128: 106486be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_128_PIXELS; 106586be9a04SYue Hin Lau break; 106686be9a04SYue Hin Lau case 256: 106786be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_256_PIXELS; 106886be9a04SYue Hin Lau break; 106986be9a04SYue Hin Lau default: 107086be9a04SYue Hin Lau DC_ERR("Invalid cursor pitch of %d. " 107186be9a04SYue Hin Lau "Only 64/128/256 is supported on DCN.\n", pitch); 107286be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 107386be9a04SYue Hin Lau break; 107486be9a04SYue Hin Lau } 107586be9a04SYue Hin Lau return hw_pitch; 107686be9a04SYue Hin Lau } 107786be9a04SYue Hin Lau 107836192e7eSEric Bernstein static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 107986be9a04SYue Hin Lau unsigned int cur_width, 108086be9a04SYue Hin Lau enum dc_cursor_color_format format) 108186be9a04SYue Hin Lau { 108286be9a04SYue Hin Lau enum cursor_lines_per_chunk line_per_chunk; 108386be9a04SYue Hin Lau 108486be9a04SYue Hin Lau if (format == CURSOR_MODE_MONO) 108586be9a04SYue Hin Lau /* impl B. expansion in CUR Buffer reader */ 108686be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 108786be9a04SYue Hin Lau else if (cur_width <= 32) 108886be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 108986be9a04SYue Hin Lau else if (cur_width <= 64) 109086be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 109186be9a04SYue Hin Lau else if (cur_width <= 128) 109286be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 109386be9a04SYue Hin Lau else 109486be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 109586be9a04SYue Hin Lau 109686be9a04SYue Hin Lau return line_per_chunk; 109786be9a04SYue Hin Lau } 109886be9a04SYue Hin Lau 109986be9a04SYue Hin Lau void hubp1_cursor_set_attributes( 110086be9a04SYue Hin Lau struct hubp *hubp, 110186be9a04SYue Hin Lau const struct dc_cursor_attributes *attr) 110286be9a04SYue Hin Lau { 110386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 110436192e7eSEric Bernstein enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 110536192e7eSEric Bernstein enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 110686be9a04SYue Hin Lau attr->width, attr->color_format); 110786be9a04SYue Hin Lau 110886be9a04SYue Hin Lau hubp->curs_attr = *attr; 110986be9a04SYue Hin Lau 111086be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 111186be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 111286be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS, 111386be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS, attr->address.low_part); 111486be9a04SYue Hin Lau 111586be9a04SYue Hin Lau REG_UPDATE_2(CURSOR_SIZE, 111686be9a04SYue Hin Lau CURSOR_WIDTH, attr->width, 111786be9a04SYue Hin Lau CURSOR_HEIGHT, attr->height); 111836192e7eSEric Bernstein 111986be9a04SYue Hin Lau REG_UPDATE_3(CURSOR_CONTROL, 112086be9a04SYue Hin Lau CURSOR_MODE, attr->color_format, 112186be9a04SYue Hin Lau CURSOR_PITCH, hw_pitch, 112286be9a04SYue Hin Lau CURSOR_LINES_PER_CHUNK, lpc); 112336192e7eSEric Bernstein 1124e9be38b4SEric Bernstein REG_SET_2(CURSOR_SETTINS, 0, 1125e9be38b4SEric Bernstein /* no shift of the cursor HDL schedule */ 1126e9be38b4SEric Bernstein CURSOR0_DST_Y_OFFSET, 0, 1127e9be38b4SEric Bernstein /* used to shift the cursor chunk request deadline */ 1128e9be38b4SEric Bernstein CURSOR0_CHUNK_HDL_ADJUST, 3); 112986be9a04SYue Hin Lau } 113086be9a04SYue Hin Lau 113186be9a04SYue Hin Lau void hubp1_cursor_set_position( 113286be9a04SYue Hin Lau struct hubp *hubp, 113386be9a04SYue Hin Lau const struct dc_cursor_position *pos, 113486be9a04SYue Hin Lau const struct dc_cursor_mi_param *param) 113586be9a04SYue Hin Lau { 113686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113739a9f4d8SDmytro Laktyushkin int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 113894a4ffd1SGloria Li int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 113908ed681cSDmytro Laktyushkin int x_hotspot = pos->x_hotspot; 114008ed681cSDmytro Laktyushkin int y_hotspot = pos->y_hotspot; 114108ed681cSDmytro Laktyushkin uint32_t dst_x_offset; 114286be9a04SYue Hin Lau uint32_t cur_en = pos->enable ? 1 : 0; 114386be9a04SYue Hin Lau 114486be9a04SYue Hin Lau /* 114586be9a04SYue Hin Lau * Guard aganst cursor_set_position() from being called with invalid 114686be9a04SYue Hin Lau * attributes 114786be9a04SYue Hin Lau * 114886be9a04SYue Hin Lau * TODO: Look at combining cursor_set_position() and 114986be9a04SYue Hin Lau * cursor_set_attributes() into cursor_update() 115086be9a04SYue Hin Lau */ 115186be9a04SYue Hin Lau if (hubp->curs_attr.address.quad_part == 0) 115286be9a04SYue Hin Lau return; 115386be9a04SYue Hin Lau 115408ed681cSDmytro Laktyushkin if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 115508ed681cSDmytro Laktyushkin src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 115608ed681cSDmytro Laktyushkin y_hotspot = pos->x_hotspot; 115708ed681cSDmytro Laktyushkin x_hotspot = pos->y_hotspot; 115808ed681cSDmytro Laktyushkin } 115908ed681cSDmytro Laktyushkin 116008ed681cSDmytro Laktyushkin if (param->mirror) { 116108ed681cSDmytro Laktyushkin x_hotspot = param->viewport.width - x_hotspot; 116208ed681cSDmytro Laktyushkin src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 116308ed681cSDmytro Laktyushkin } 116408ed681cSDmytro Laktyushkin 116508ed681cSDmytro Laktyushkin dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 116686be9a04SYue Hin Lau dst_x_offset *= param->ref_clk_khz; 116786be9a04SYue Hin Lau dst_x_offset /= param->pixel_clk_khz; 116886be9a04SYue Hin Lau 116986be9a04SYue Hin Lau ASSERT(param->h_scale_ratio.value); 117086be9a04SYue Hin Lau 117186be9a04SYue Hin Lau if (param->h_scale_ratio.value) 1172eb0e5154SDmytro Laktyushkin dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1173eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(dst_x_offset), 117486be9a04SYue Hin Lau param->h_scale_ratio)); 117586be9a04SYue Hin Lau 117639a9f4d8SDmytro Laktyushkin if (src_x_offset >= (int)param->viewport.width) 117786be9a04SYue Hin Lau cur_en = 0; /* not visible beyond right edge*/ 117886be9a04SYue Hin Lau 117935d13315SMartin Tsai if (src_x_offset + (int)hubp->curs_attr.width <= 0) 118086be9a04SYue Hin Lau cur_en = 0; /* not visible beyond left edge*/ 118186be9a04SYue Hin Lau 118294a4ffd1SGloria Li if (src_y_offset >= (int)param->viewport.height) 118394a4ffd1SGloria Li cur_en = 0; /* not visible beyond bottom edge*/ 118494a4ffd1SGloria Li 118555a806d3SNicholas Kazlauskas if (src_y_offset + (int)hubp->curs_attr.height <= 0) 118694a4ffd1SGloria Li cur_en = 0; /* not visible beyond top edge*/ 118794a4ffd1SGloria Li 118886be9a04SYue Hin Lau if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 118936192e7eSEric Bernstein hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 119036192e7eSEric Bernstein 119186be9a04SYue Hin Lau REG_UPDATE(CURSOR_CONTROL, 119286be9a04SYue Hin Lau CURSOR_ENABLE, cur_en); 119386be9a04SYue Hin Lau 119486be9a04SYue Hin Lau REG_SET_2(CURSOR_POSITION, 0, 119586be9a04SYue Hin Lau CURSOR_X_POSITION, pos->x, 119686be9a04SYue Hin Lau CURSOR_Y_POSITION, pos->y); 119786be9a04SYue Hin Lau 119886be9a04SYue Hin Lau REG_SET_2(CURSOR_HOT_SPOT, 0, 119908ed681cSDmytro Laktyushkin CURSOR_HOT_SPOT_X, x_hotspot, 120008ed681cSDmytro Laktyushkin CURSOR_HOT_SPOT_Y, y_hotspot); 120186be9a04SYue Hin Lau 120286be9a04SYue Hin Lau REG_SET(CURSOR_DST_OFFSET, 0, 120386be9a04SYue Hin Lau CURSOR_DST_X_OFFSET, dst_x_offset); 120486be9a04SYue Hin Lau /* TODO Handle surface pixel formats other than 4:4:4 */ 120586be9a04SYue Hin Lau } 120686be9a04SYue Hin Lau 1207c8242b98SYongqiang Sun void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1208c8242b98SYongqiang Sun { 1209c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1210c8242b98SYongqiang Sun uint32_t clk_enable = enable ? 1 : 0; 1211c8242b98SYongqiang Sun 1212c8242b98SYongqiang Sun REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1213c8242b98SYongqiang Sun } 1214c8242b98SYongqiang Sun 1215c8242b98SYongqiang Sun void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1216c8242b98SYongqiang Sun { 1217c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1218c8242b98SYongqiang Sun 1219c8242b98SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1220c8242b98SYongqiang Sun } 1221c8242b98SYongqiang Sun 1222cc8d8413SCharlene Liu void hubp1_init(struct hubp *hubp) 1223cc8d8413SCharlene Liu { 1224cc8d8413SCharlene Liu //do nothing 1225cc8d8413SCharlene Liu } 1226bd4e7250SHarry Wentland static const struct hubp_funcs dcn10_hubp_funcs = { 122786be9a04SYue Hin Lau .hubp_program_surface_flip_and_addr = 122886be9a04SYue Hin Lau hubp1_program_surface_flip_and_addr, 122986be9a04SYue Hin Lau .hubp_program_surface_config = 123086be9a04SYue Hin Lau hubp1_program_surface_config, 123186be9a04SYue Hin Lau .hubp_is_flip_pending = hubp1_is_flip_pending, 123286be9a04SYue Hin Lau .hubp_setup = hubp1_setup, 12331a1adf17SDmytro Laktyushkin .hubp_setup_interdependent = hubp1_setup_interdependent, 123486be9a04SYue Hin Lau .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 123586be9a04SYue Hin Lau .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 123686be9a04SYue Hin Lau .set_blank = hubp1_set_blank, 123786be9a04SYue Hin Lau .dcc_control = hubp1_dcc_control, 123886be9a04SYue Hin Lau .mem_program_viewport = min_set_viewport, 123986be9a04SYue Hin Lau .set_hubp_blank_en = hubp1_set_hubp_blank_en, 124086be9a04SYue Hin Lau .set_cursor_attributes = hubp1_cursor_set_attributes, 124186be9a04SYue Hin Lau .set_cursor_position = hubp1_cursor_set_position, 12421dbac201SYongqiang Sun .hubp_disconnect = hubp1_disconnect, 1243c8242b98SYongqiang Sun .hubp_clk_cntl = hubp1_clk_cntl, 1244c8242b98SYongqiang Sun .hubp_vtg_sel = hubp1_vtg_sel, 12450a93dc7fSDmytro Laktyushkin .hubp_read_state = hubp1_read_state, 1246eb6b29d6SJun Lei .hubp_clear_underflow = hubp1_clear_underflow, 12473ba43a59SCharlene Liu .hubp_disable_control = hubp1_disable_control, 12483ba43a59SCharlene Liu .hubp_get_underflow_status = hubp1_get_underflow_status, 1249cc8d8413SCharlene Liu .hubp_init = hubp1_init, 1250bbeb64d0SHarry Wentland 1251bbeb64d0SHarry Wentland #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 1252bbeb64d0SHarry Wentland .dmdata_set_attributes = NULL, 1253bbeb64d0SHarry Wentland .dmdata_load = NULL, 1254bbeb64d0SHarry Wentland #endif 125586be9a04SYue Hin Lau }; 125686be9a04SYue Hin Lau 125786be9a04SYue Hin Lau /*****************************************/ 125886be9a04SYue Hin Lau /* Constructor, Destructor */ 125986be9a04SYue Hin Lau /*****************************************/ 126086be9a04SYue Hin Lau 126186be9a04SYue Hin Lau void dcn10_hubp_construct( 126286be9a04SYue Hin Lau struct dcn10_hubp *hubp1, 126386be9a04SYue Hin Lau struct dc_context *ctx, 126486be9a04SYue Hin Lau uint32_t inst, 1265c42c275cSYue Hin Lau const struct dcn_mi_registers *hubp_regs, 1266c42c275cSYue Hin Lau const struct dcn_mi_shift *hubp_shift, 1267c42c275cSYue Hin Lau const struct dcn_mi_mask *hubp_mask) 126886be9a04SYue Hin Lau { 126986be9a04SYue Hin Lau hubp1->base.funcs = &dcn10_hubp_funcs; 127086be9a04SYue Hin Lau hubp1->base.ctx = ctx; 1271c42c275cSYue Hin Lau hubp1->hubp_regs = hubp_regs; 1272c42c275cSYue Hin Lau hubp1->hubp_shift = hubp_shift; 1273c42c275cSYue Hin Lau hubp1->hubp_mask = hubp_mask; 127486be9a04SYue Hin Lau hubp1->base.inst = inst; 1275043f5bb6SWesley Chalmers hubp1->base.opp_id = OPP_ID_INVALID; 127686be9a04SYue Hin Lau hubp1->base.mpcc_id = 0xf; 127786be9a04SYue Hin Lau } 127886be9a04SYue Hin Lau 127986be9a04SYue Hin Lau 1280