186be9a04SYue Hin Lau /* 286be9a04SYue Hin Lau * Copyright 2012-15 Advanced Micro Devices, Inc. 386be9a04SYue Hin Lau * 486be9a04SYue Hin Lau * Permission is hereby granted, free of charge, to any person obtaining a 586be9a04SYue Hin Lau * copy of this software and associated documentation files (the "Software"), 686be9a04SYue Hin Lau * to deal in the Software without restriction, including without limitation 786be9a04SYue Hin Lau * the rights to use, copy, modify, merge, publish, distribute, sublicense, 886be9a04SYue Hin Lau * and/or sell copies of the Software, and to permit persons to whom the 986be9a04SYue Hin Lau * Software is furnished to do so, subject to the following conditions: 1086be9a04SYue Hin Lau * 1186be9a04SYue Hin Lau * The above copyright notice and this permission notice shall be included in 1286be9a04SYue Hin Lau * all copies or substantial portions of the Software. 1386be9a04SYue Hin Lau * 1486be9a04SYue Hin Lau * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1586be9a04SYue Hin Lau * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1686be9a04SYue Hin Lau * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1786be9a04SYue Hin Lau * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1886be9a04SYue Hin Lau * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1986be9a04SYue Hin Lau * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2086be9a04SYue Hin Lau * OTHER DEALINGS IN THE SOFTWARE. 2186be9a04SYue Hin Lau * 2286be9a04SYue Hin Lau * Authors: AMD 2386be9a04SYue Hin Lau * 2486be9a04SYue Hin Lau */ 2586be9a04SYue Hin Lau #include "dm_services.h" 2686be9a04SYue Hin Lau #include "dce_calcs.h" 2786be9a04SYue Hin Lau #include "reg_helper.h" 2886be9a04SYue Hin Lau #include "basics/conversion.h" 2986be9a04SYue Hin Lau #include "dcn10_hubp.h" 3086be9a04SYue Hin Lau 3186be9a04SYue Hin Lau #define REG(reg)\ 32c42c275cSYue Hin Lau hubp1->hubp_regs->reg 3386be9a04SYue Hin Lau 3486be9a04SYue Hin Lau #define CTX \ 3586be9a04SYue Hin Lau hubp1->base.ctx 3686be9a04SYue Hin Lau 3786be9a04SYue Hin Lau #undef FN 3886be9a04SYue Hin Lau #define FN(reg_name, field_name) \ 39c42c275cSYue Hin Lau hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 4086be9a04SYue Hin Lau 4186be9a04SYue Hin Lau void hubp1_set_blank(struct hubp *hubp, bool blank) 4286be9a04SYue Hin Lau { 4386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 4486be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 4586be9a04SYue Hin Lau 4675c2dec3STony Cheng REG_UPDATE_2(DCHUBP_CNTL, 4786be9a04SYue Hin Lau HUBP_BLANK_EN, blank_en, 4886be9a04SYue Hin Lau HUBP_TTU_DISABLE, blank_en); 4986be9a04SYue Hin Lau 5086be9a04SYue Hin Lau if (blank) { 5175c2dec3STony Cheng uint32_t reg_val = REG_READ(DCHUBP_CNTL); 5275c2dec3STony Cheng 53cc55b1f5STony Cheng if (reg_val) { 54cc55b1f5STony Cheng /* init sequence workaround: in case HUBP is 55cc55b1f5STony Cheng * power gated, this wait would timeout. 56cc55b1f5STony Cheng * 57cc55b1f5STony Cheng * we just wrote reg_val to non-0, if it stay 0 58cc55b1f5STony Cheng * it means HUBP is gated 59cc55b1f5STony Cheng */ 6086be9a04SYue Hin Lau REG_WAIT(DCHUBP_CNTL, 6186be9a04SYue Hin Lau HUBP_NO_OUTSTANDING_REQ, 1, 6286be9a04SYue Hin Lau 1, 200); 63cc55b1f5STony Cheng } 64cc55b1f5STony Cheng 6586be9a04SYue Hin Lau hubp->mpcc_id = 0xf; 6686be9a04SYue Hin Lau hubp->opp_id = 0xf; 6786be9a04SYue Hin Lau } 6886be9a04SYue Hin Lau } 6986be9a04SYue Hin Lau 701dbac201SYongqiang Sun static void hubp1_disconnect(struct hubp *hubp) 711dbac201SYongqiang Sun { 721dbac201SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 731dbac201SYongqiang Sun 741dbac201SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, 751dbac201SYongqiang Sun HUBP_TTU_DISABLE, 1); 765af9d013SEric Yang 775af9d013SEric Yang REG_UPDATE(CURSOR_CONTROL, 785af9d013SEric Yang CURSOR_ENABLE, 0); 791dbac201SYongqiang Sun } 801dbac201SYongqiang Sun 8186be9a04SYue Hin Lau static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 8286be9a04SYue Hin Lau { 8386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 8486be9a04SYue Hin Lau uint32_t blank_en = blank ? 1 : 0; 8586be9a04SYue Hin Lau 8686be9a04SYue Hin Lau REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 8786be9a04SYue Hin Lau } 8886be9a04SYue Hin Lau 8986be9a04SYue Hin Lau static void hubp1_vready_workaround(struct hubp *hubp, 9086be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 9186be9a04SYue Hin Lau { 9286be9a04SYue Hin Lau uint32_t value = 0; 9386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 9486be9a04SYue Hin Lau 9586be9a04SYue Hin Lau /* set HBUBREQ_DEBUG_DB[12] = 1 */ 9686be9a04SYue Hin Lau value = REG_READ(HUBPREQ_DEBUG_DB); 9786be9a04SYue Hin Lau 9886be9a04SYue Hin Lau /* hack mode disable */ 9986be9a04SYue Hin Lau value |= 0x100; 10086be9a04SYue Hin Lau value &= ~0x1000; 10186be9a04SYue Hin Lau 10286be9a04SYue Hin Lau if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 10386be9a04SYue Hin Lau + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 10486be9a04SYue Hin Lau /* if (eco_fix_needed(otg_global_sync_timing) 10586be9a04SYue Hin Lau * set HBUBREQ_DEBUG_DB[12] = 1 */ 10686be9a04SYue Hin Lau value |= 0x1000; 10786be9a04SYue Hin Lau } 10886be9a04SYue Hin Lau 10986be9a04SYue Hin Lau REG_WRITE(HUBPREQ_DEBUG_DB, value); 11086be9a04SYue Hin Lau } 11186be9a04SYue Hin Lau 11286be9a04SYue Hin Lau void hubp1_program_tiling( 1134b8240bfSYue Hin Lau struct hubp *hubp, 11486be9a04SYue Hin Lau const union dc_tiling_info *info, 11586be9a04SYue Hin Lau const enum surface_pixel_format pixel_format) 11686be9a04SYue Hin Lau { 1174b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1184b8240bfSYue Hin Lau 11986be9a04SYue Hin Lau REG_UPDATE_6(DCSURF_ADDR_CONFIG, 12086be9a04SYue Hin Lau NUM_PIPES, log_2(info->gfx9.num_pipes), 12186be9a04SYue Hin Lau NUM_BANKS, log_2(info->gfx9.num_banks), 12286be9a04SYue Hin Lau PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 12386be9a04SYue Hin Lau NUM_SE, log_2(info->gfx9.num_shader_engines), 12486be9a04SYue Hin Lau NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 12586be9a04SYue Hin Lau MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 12686be9a04SYue Hin Lau 12786be9a04SYue Hin Lau REG_UPDATE_4(DCSURF_TILING_CONFIG, 12886be9a04SYue Hin Lau SW_MODE, info->gfx9.swizzle, 12986be9a04SYue Hin Lau META_LINEAR, info->gfx9.meta_linear, 13086be9a04SYue Hin Lau RB_ALIGNED, info->gfx9.rb_aligned, 13186be9a04SYue Hin Lau PIPE_ALIGNED, info->gfx9.pipe_aligned); 13286be9a04SYue Hin Lau } 13386be9a04SYue Hin Lau 13486be9a04SYue Hin Lau void hubp1_program_size_and_rotation( 1354b8240bfSYue Hin Lau struct hubp *hubp, 13686be9a04SYue Hin Lau enum dc_rotation_angle rotation, 13786be9a04SYue Hin Lau enum surface_pixel_format format, 13886be9a04SYue Hin Lau const union plane_size *plane_size, 13986be9a04SYue Hin Lau struct dc_plane_dcc_param *dcc, 14086be9a04SYue Hin Lau bool horizontal_mirror) 14186be9a04SYue Hin Lau { 1424b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 14386be9a04SYue Hin Lau uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror; 14486be9a04SYue Hin Lau 14586be9a04SYue Hin Lau /* Program data and meta surface pitch (calculation from addrlib) 14686be9a04SYue Hin Lau * 444 or 420 luma 14786be9a04SYue Hin Lau */ 14886be9a04SYue Hin Lau if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 14986be9a04SYue Hin Lau pitch = plane_size->video.luma_pitch - 1; 15086be9a04SYue Hin Lau meta_pitch = dcc->video.meta_pitch_l - 1; 15186be9a04SYue Hin Lau pitch_c = plane_size->video.chroma_pitch - 1; 15286be9a04SYue Hin Lau meta_pitch_c = dcc->video.meta_pitch_c - 1; 15386be9a04SYue Hin Lau } else { 15486be9a04SYue Hin Lau pitch = plane_size->grph.surface_pitch - 1; 15586be9a04SYue Hin Lau meta_pitch = dcc->grph.meta_pitch - 1; 15686be9a04SYue Hin Lau pitch_c = 0; 15786be9a04SYue Hin Lau meta_pitch_c = 0; 15886be9a04SYue Hin Lau } 15986be9a04SYue Hin Lau 16086be9a04SYue Hin Lau if (!dcc->enable) { 16186be9a04SYue Hin Lau meta_pitch = 0; 16286be9a04SYue Hin Lau meta_pitch_c = 0; 16386be9a04SYue Hin Lau } 16486be9a04SYue Hin Lau 16586be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH, 16686be9a04SYue Hin Lau PITCH, pitch, META_PITCH, meta_pitch); 16786be9a04SYue Hin Lau 16886be9a04SYue Hin Lau if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 16986be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 17086be9a04SYue Hin Lau PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 17186be9a04SYue Hin Lau 17286be9a04SYue Hin Lau if (horizontal_mirror) 17386be9a04SYue Hin Lau mirror = 1; 17486be9a04SYue Hin Lau else 17586be9a04SYue Hin Lau mirror = 0; 17686be9a04SYue Hin Lau 17786be9a04SYue Hin Lau 17886be9a04SYue Hin Lau /* Program rotation angle and horz mirror - no mirror */ 17986be9a04SYue Hin Lau if (rotation == ROTATION_ANGLE_0) 18086be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 18186be9a04SYue Hin Lau ROTATION_ANGLE, 0, 18286be9a04SYue Hin Lau H_MIRROR_EN, mirror); 18386be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_90) 18486be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 18586be9a04SYue Hin Lau ROTATION_ANGLE, 1, 18686be9a04SYue Hin Lau H_MIRROR_EN, mirror); 18786be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_180) 18886be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 18986be9a04SYue Hin Lau ROTATION_ANGLE, 2, 19086be9a04SYue Hin Lau H_MIRROR_EN, mirror); 19186be9a04SYue Hin Lau else if (rotation == ROTATION_ANGLE_270) 19286be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 19386be9a04SYue Hin Lau ROTATION_ANGLE, 3, 19486be9a04SYue Hin Lau H_MIRROR_EN, mirror); 19586be9a04SYue Hin Lau } 19686be9a04SYue Hin Lau 19786be9a04SYue Hin Lau void hubp1_program_pixel_format( 1984b8240bfSYue Hin Lau struct hubp *hubp, 19986be9a04SYue Hin Lau enum surface_pixel_format format) 20086be9a04SYue Hin Lau { 2014b8240bfSYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 20286be9a04SYue Hin Lau uint32_t red_bar = 3; 20386be9a04SYue Hin Lau uint32_t blue_bar = 2; 20486be9a04SYue Hin Lau 20586be9a04SYue Hin Lau /* swap for ABGR format */ 20686be9a04SYue Hin Lau if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 20786be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 20886be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 20986be9a04SYue Hin Lau || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 21086be9a04SYue Hin Lau red_bar = 2; 21186be9a04SYue Hin Lau blue_bar = 3; 21286be9a04SYue Hin Lau } 21386be9a04SYue Hin Lau 21486be9a04SYue Hin Lau REG_UPDATE_2(HUBPRET_CONTROL, 21586be9a04SYue Hin Lau CROSSBAR_SRC_CB_B, blue_bar, 21686be9a04SYue Hin Lau CROSSBAR_SRC_CR_R, red_bar); 21786be9a04SYue Hin Lau 21886be9a04SYue Hin Lau /* Mapping is same as ipp programming (cnvc) */ 21986be9a04SYue Hin Lau 22086be9a04SYue Hin Lau switch (format) { 22186be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 22286be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 22386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 1); 22486be9a04SYue Hin Lau break; 22586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 22686be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 22786be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 3); 22886be9a04SYue Hin Lau break; 22986be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 23086be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 23186be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 23286be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 8); 23386be9a04SYue Hin Lau break; 23486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 23586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 23686be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 23786be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 23886be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 10); 23986be9a04SYue Hin Lau break; 24086be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 24186be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 24286be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 22); 24386be9a04SYue Hin Lau break; 24486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 24586be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 24686be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 24786be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 24); 24886be9a04SYue Hin Lau break; 24986be9a04SYue Hin Lau 25086be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 25186be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 25286be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 65); 25386be9a04SYue Hin Lau break; 25486be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 25586be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 25686be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 64); 25786be9a04SYue Hin Lau break; 25886be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 25986be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26086be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 67); 26186be9a04SYue Hin Lau break; 26286be9a04SYue Hin Lau case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 26386be9a04SYue Hin Lau REG_UPDATE(DCSURF_SURFACE_CONFIG, 26486be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, 66); 26586be9a04SYue Hin Lau break; 26686be9a04SYue Hin Lau default: 26786be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 26886be9a04SYue Hin Lau break; 26986be9a04SYue Hin Lau } 27086be9a04SYue Hin Lau 27186be9a04SYue Hin Lau /* don't see the need of program the xbar in DCN 1.0 */ 27286be9a04SYue Hin Lau } 27386be9a04SYue Hin Lau 27486be9a04SYue Hin Lau bool hubp1_program_surface_flip_and_addr( 27586be9a04SYue Hin Lau struct hubp *hubp, 27686be9a04SYue Hin Lau const struct dc_plane_address *address, 27786be9a04SYue Hin Lau bool flip_immediate) 27886be9a04SYue Hin Lau { 27986be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 28086be9a04SYue Hin Lau 28186be9a04SYue Hin Lau /* program flip type */ 28286be9a04SYue Hin Lau REG_SET(DCSURF_FLIP_CONTROL, 0, 28386be9a04SYue Hin Lau SURFACE_FLIP_TYPE, flip_immediate); 28486be9a04SYue Hin Lau 28586be9a04SYue Hin Lau /* HW automatically latch rest of address register on write to 28686be9a04SYue Hin Lau * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 28786be9a04SYue Hin Lau * 28886be9a04SYue Hin Lau * program high first and then the low addr, order matters! 28986be9a04SYue Hin Lau */ 29086be9a04SYue Hin Lau switch (address->type) { 29186be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRAPHICS: 29286be9a04SYue Hin Lau /* DCN1.0 does not support const color 29386be9a04SYue Hin Lau * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 29486be9a04SYue Hin Lau * base on address->grph.dcc_const_color 29586be9a04SYue Hin Lau * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 29686be9a04SYue Hin Lau * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 29786be9a04SYue Hin Lau */ 29886be9a04SYue Hin Lau 29986be9a04SYue Hin Lau if (address->grph.addr.quad_part == 0) 30086be9a04SYue Hin Lau break; 30186be9a04SYue Hin Lau 302cf8c19a3SYongqiang Sun REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 303cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 304cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 30586be9a04SYue Hin Lau 30686be9a04SYue Hin Lau if (address->grph.meta_addr.quad_part != 0) { 30786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 30886be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 30986be9a04SYue Hin Lau address->grph.meta_addr.high_part); 31086be9a04SYue Hin Lau 31186be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 31286be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 31386be9a04SYue Hin Lau address->grph.meta_addr.low_part); 31486be9a04SYue Hin Lau } 31586be9a04SYue Hin Lau 31686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 31786be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 31886be9a04SYue Hin Lau address->grph.addr.high_part); 31986be9a04SYue Hin Lau 32086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 32186be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 32286be9a04SYue Hin Lau address->grph.addr.low_part); 32386be9a04SYue Hin Lau break; 32486be9a04SYue Hin Lau case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 32586be9a04SYue Hin Lau if (address->video_progressive.luma_addr.quad_part == 0 32686be9a04SYue Hin Lau || address->video_progressive.chroma_addr.quad_part == 0) 32786be9a04SYue Hin Lau break; 32886be9a04SYue Hin Lau 329cf8c19a3SYongqiang Sun REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 330cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 331cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 332cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 333cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 33486be9a04SYue Hin Lau 33586be9a04SYue Hin Lau if (address->video_progressive.luma_meta_addr.quad_part != 0) { 33686be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 33786be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 33886be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.high_part); 33986be9a04SYue Hin Lau 34086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 34186be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_C, 34286be9a04SYue Hin Lau address->video_progressive.chroma_meta_addr.low_part); 34386be9a04SYue Hin Lau 34486be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 34586be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 34686be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.high_part); 34786be9a04SYue Hin Lau 34886be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 34986be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 35086be9a04SYue Hin Lau address->video_progressive.luma_meta_addr.low_part); 35186be9a04SYue Hin Lau } 35286be9a04SYue Hin Lau 35386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 35486be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH_C, 35586be9a04SYue Hin Lau address->video_progressive.chroma_addr.high_part); 35686be9a04SYue Hin Lau 35786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 35886be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_C, 35986be9a04SYue Hin Lau address->video_progressive.chroma_addr.low_part); 36086be9a04SYue Hin Lau 36186be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 36286be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 36386be9a04SYue Hin Lau address->video_progressive.luma_addr.high_part); 36486be9a04SYue Hin Lau 36586be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 36686be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 36786be9a04SYue Hin Lau address->video_progressive.luma_addr.low_part); 36886be9a04SYue Hin Lau break; 36986be9a04SYue Hin Lau case PLN_ADDR_TYPE_GRPH_STEREO: 37086be9a04SYue Hin Lau if (address->grph_stereo.left_addr.quad_part == 0) 37186be9a04SYue Hin Lau break; 37286be9a04SYue Hin Lau if (address->grph_stereo.right_addr.quad_part == 0) 37386be9a04SYue Hin Lau break; 37486be9a04SYue Hin Lau 375cf8c19a3SYongqiang Sun REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 376cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ, address->tmz_surface, 377cf8c19a3SYongqiang Sun PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 378cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 379cf8c19a3SYongqiang Sun PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 38086be9a04SYue Hin Lau 38186be9a04SYue Hin Lau if (address->grph_stereo.right_meta_addr.quad_part != 0) { 38286be9a04SYue Hin Lau 38386be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 38486be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS_HIGH, 38586be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.high_part); 38686be9a04SYue Hin Lau 38786be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 38886be9a04SYue Hin Lau SECONDARY_META_SURFACE_ADDRESS, 38986be9a04SYue Hin Lau address->grph_stereo.right_meta_addr.low_part); 39086be9a04SYue Hin Lau } 39186be9a04SYue Hin Lau if (address->grph_stereo.left_meta_addr.quad_part != 0) { 39286be9a04SYue Hin Lau 39386be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 39486be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS_HIGH, 39586be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.high_part); 39686be9a04SYue Hin Lau 39786be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 39886be9a04SYue Hin Lau PRIMARY_META_SURFACE_ADDRESS, 39986be9a04SYue Hin Lau address->grph_stereo.left_meta_addr.low_part); 40086be9a04SYue Hin Lau } 40186be9a04SYue Hin Lau 40286be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 40386be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS_HIGH, 40486be9a04SYue Hin Lau address->grph_stereo.right_addr.high_part); 40586be9a04SYue Hin Lau 40686be9a04SYue Hin Lau REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 40786be9a04SYue Hin Lau SECONDARY_SURFACE_ADDRESS, 40886be9a04SYue Hin Lau address->grph_stereo.right_addr.low_part); 40986be9a04SYue Hin Lau 41086be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 41186be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS_HIGH, 41286be9a04SYue Hin Lau address->grph_stereo.left_addr.high_part); 41386be9a04SYue Hin Lau 41486be9a04SYue Hin Lau REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 41586be9a04SYue Hin Lau PRIMARY_SURFACE_ADDRESS, 41686be9a04SYue Hin Lau address->grph_stereo.left_addr.low_part); 41786be9a04SYue Hin Lau break; 41886be9a04SYue Hin Lau default: 41986be9a04SYue Hin Lau BREAK_TO_DEBUGGER(); 42086be9a04SYue Hin Lau break; 42186be9a04SYue Hin Lau } 42286be9a04SYue Hin Lau 42386be9a04SYue Hin Lau hubp->request_address = *address; 42486be9a04SYue Hin Lau 42586be9a04SYue Hin Lau if (flip_immediate) 42686be9a04SYue Hin Lau hubp->current_address = *address; 42786be9a04SYue Hin Lau 42886be9a04SYue Hin Lau return true; 42986be9a04SYue Hin Lau } 43086be9a04SYue Hin Lau 43186be9a04SYue Hin Lau void hubp1_dcc_control(struct hubp *hubp, bool enable, 43286be9a04SYue Hin Lau bool independent_64b_blks) 43386be9a04SYue Hin Lau { 43486be9a04SYue Hin Lau uint32_t dcc_en = enable ? 1 : 0; 43586be9a04SYue Hin Lau uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 43686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 43786be9a04SYue Hin Lau 43886be9a04SYue Hin Lau REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 43986be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, dcc_en, 44086be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 44186be9a04SYue Hin Lau } 44286be9a04SYue Hin Lau 44386be9a04SYue Hin Lau void hubp1_program_surface_config( 44486be9a04SYue Hin Lau struct hubp *hubp, 44586be9a04SYue Hin Lau enum surface_pixel_format format, 44686be9a04SYue Hin Lau union dc_tiling_info *tiling_info, 44786be9a04SYue Hin Lau union plane_size *plane_size, 44886be9a04SYue Hin Lau enum dc_rotation_angle rotation, 44986be9a04SYue Hin Lau struct dc_plane_dcc_param *dcc, 45086be9a04SYue Hin Lau bool horizontal_mirror) 45186be9a04SYue Hin Lau { 45286be9a04SYue Hin Lau hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 4534b8240bfSYue Hin Lau hubp1_program_tiling(hubp, tiling_info, format); 45486be9a04SYue Hin Lau hubp1_program_size_and_rotation( 4554b8240bfSYue Hin Lau hubp, rotation, format, plane_size, dcc, horizontal_mirror); 4564b8240bfSYue Hin Lau hubp1_program_pixel_format(hubp, format); 45786be9a04SYue Hin Lau } 45886be9a04SYue Hin Lau 45986be9a04SYue Hin Lau void hubp1_program_requestor( 46086be9a04SYue Hin Lau struct hubp *hubp, 46186be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs) 46286be9a04SYue Hin Lau { 46386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 46486be9a04SYue Hin Lau 46586be9a04SYue Hin Lau REG_UPDATE(HUBPRET_CONTROL, 46686be9a04SYue Hin Lau DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 46786be9a04SYue Hin Lau REG_SET_4(DCN_EXPANSION_MODE, 0, 46886be9a04SYue Hin Lau DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 46986be9a04SYue Hin Lau PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 47086be9a04SYue Hin Lau MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 47186be9a04SYue Hin Lau CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 47286be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 47386be9a04SYue Hin Lau CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 47486be9a04SYue Hin Lau MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 47586be9a04SYue Hin Lau META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 47686be9a04SYue Hin Lau MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 47786be9a04SYue Hin Lau DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 47886be9a04SYue Hin Lau MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 47986be9a04SYue Hin Lau SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 48086be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 48186be9a04SYue Hin Lau REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 48286be9a04SYue Hin Lau CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 48386be9a04SYue Hin Lau MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 48486be9a04SYue Hin Lau META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 48586be9a04SYue Hin Lau MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 48686be9a04SYue Hin Lau DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 48786be9a04SYue Hin Lau MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 48886be9a04SYue Hin Lau SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 48986be9a04SYue Hin Lau PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 49086be9a04SYue Hin Lau } 49186be9a04SYue Hin Lau 49286be9a04SYue Hin Lau 49386be9a04SYue Hin Lau void hubp1_program_deadline( 49486be9a04SYue Hin Lau struct hubp *hubp, 49586be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 49686be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 49786be9a04SYue Hin Lau { 49886be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 49986be9a04SYue Hin Lau 50086be9a04SYue Hin Lau /* DLG - Per hubp */ 50186be9a04SYue Hin Lau REG_SET_2(BLANK_OFFSET_0, 0, 50286be9a04SYue Hin Lau REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 50386be9a04SYue Hin Lau DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 50486be9a04SYue Hin Lau 50586be9a04SYue Hin Lau REG_SET(BLANK_OFFSET_1, 0, 50686be9a04SYue Hin Lau MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 50786be9a04SYue Hin Lau 50886be9a04SYue Hin Lau REG_SET(DST_DIMENSIONS, 0, 50986be9a04SYue Hin Lau REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 51086be9a04SYue Hin Lau 51186be9a04SYue Hin Lau REG_SET_2(DST_AFTER_SCALER, 0, 51286be9a04SYue Hin Lau REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 51386be9a04SYue Hin Lau DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 51486be9a04SYue Hin Lau 51586be9a04SYue Hin Lau if (REG(PREFETCH_SETTINS)) 51686be9a04SYue Hin Lau REG_SET_2(PREFETCH_SETTINS, 0, 51786be9a04SYue Hin Lau DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 51886be9a04SYue Hin Lau VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 51986be9a04SYue Hin Lau else 52086be9a04SYue Hin Lau REG_SET_2(PREFETCH_SETTINGS, 0, 52186be9a04SYue Hin Lau DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 52286be9a04SYue Hin Lau VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 52386be9a04SYue Hin Lau 52486be9a04SYue Hin Lau REG_SET_2(VBLANK_PARAMETERS_0, 0, 52586be9a04SYue Hin Lau DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 52686be9a04SYue Hin Lau DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 52786be9a04SYue Hin Lau 52886be9a04SYue Hin Lau REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 52986be9a04SYue Hin Lau REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 53086be9a04SYue Hin Lau 53186be9a04SYue Hin Lau /* DLG - Per luma/chroma */ 53286be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_1, 0, 53386be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 53486be9a04SYue Hin Lau 53586be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_3, 0, 53686be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 53786be9a04SYue Hin Lau 538b552204bSNikola Cornij if (REG(NOM_PARAMETERS_0)) 53986be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_0, 0, 54086be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 54186be9a04SYue Hin Lau 542b552204bSNikola Cornij if (REG(NOM_PARAMETERS_1)) 54386be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_1, 0, 54486be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 54586be9a04SYue Hin Lau 54686be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_4, 0, 54786be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 54886be9a04SYue Hin Lau 54986be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_5, 0, 55086be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 55186be9a04SYue Hin Lau 55286be9a04SYue Hin Lau REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 55386be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 55486be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 55586be9a04SYue Hin Lau 55686be9a04SYue Hin Lau REG_SET_2(PER_LINE_DELIVERY, 0, 55786be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 55886be9a04SYue Hin Lau REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 55986be9a04SYue Hin Lau 56086be9a04SYue Hin Lau if (REG(PREFETCH_SETTINS_C)) 56186be9a04SYue Hin Lau REG_SET(PREFETCH_SETTINS_C, 0, 56286be9a04SYue Hin Lau VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 56386be9a04SYue Hin Lau else 56486be9a04SYue Hin Lau REG_SET(PREFETCH_SETTINGS_C, 0, 56586be9a04SYue Hin Lau VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 56686be9a04SYue Hin Lau 56786be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_2, 0, 56886be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 56986be9a04SYue Hin Lau 57086be9a04SYue Hin Lau REG_SET(VBLANK_PARAMETERS_4, 0, 57186be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 57286be9a04SYue Hin Lau 573b552204bSNikola Cornij if (REG(NOM_PARAMETERS_2)) 57486be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_2, 0, 57586be9a04SYue Hin Lau DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 57686be9a04SYue Hin Lau 577b552204bSNikola Cornij if (REG(NOM_PARAMETERS_3)) 57886be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_3, 0, 57986be9a04SYue Hin Lau REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 58086be9a04SYue Hin Lau 58186be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_6, 0, 58286be9a04SYue Hin Lau DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 58386be9a04SYue Hin Lau 58486be9a04SYue Hin Lau REG_SET(NOM_PARAMETERS_7, 0, 58586be9a04SYue Hin Lau REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 58686be9a04SYue Hin Lau 58786be9a04SYue Hin Lau /* TTU - per hubp */ 58886be9a04SYue Hin Lau REG_SET_2(DCN_TTU_QOS_WM, 0, 58986be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 59086be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 59186be9a04SYue Hin Lau 59286be9a04SYue Hin Lau REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 59386be9a04SYue Hin Lau MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 59486be9a04SYue Hin Lau QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 59586be9a04SYue Hin Lau 59686be9a04SYue Hin Lau /* TTU - per luma/chroma */ 59786be9a04SYue Hin Lau /* Assumed surf0 is luma and 1 is chroma */ 59886be9a04SYue Hin Lau 59986be9a04SYue Hin Lau REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 60086be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 60186be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 60286be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 60386be9a04SYue Hin Lau 60486be9a04SYue Hin Lau REG_SET(DCN_SURF0_TTU_CNTL1, 0, 60586be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY_PRE, 60686be9a04SYue Hin Lau ttu_attr->refcyc_per_req_delivery_pre_l); 60786be9a04SYue Hin Lau 60886be9a04SYue Hin Lau REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 60986be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 61086be9a04SYue Hin Lau QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 61186be9a04SYue Hin Lau QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 61286be9a04SYue Hin Lau 61386be9a04SYue Hin Lau REG_SET(DCN_SURF1_TTU_CNTL1, 0, 61486be9a04SYue Hin Lau REFCYC_PER_REQ_DELIVERY_PRE, 61586be9a04SYue Hin Lau ttu_attr->refcyc_per_req_delivery_pre_c); 61686be9a04SYue Hin Lau } 61786be9a04SYue Hin Lau 61886be9a04SYue Hin Lau static void hubp1_setup( 61986be9a04SYue Hin Lau struct hubp *hubp, 62086be9a04SYue Hin Lau struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 62186be9a04SYue Hin Lau struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 62286be9a04SYue Hin Lau struct _vcs_dpi_display_rq_regs_st *rq_regs, 62386be9a04SYue Hin Lau struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 62486be9a04SYue Hin Lau { 62586be9a04SYue Hin Lau /* otg is locked when this func is called. Register are double buffered. 62686be9a04SYue Hin Lau * disable the requestors is not needed 62786be9a04SYue Hin Lau */ 62886be9a04SYue Hin Lau hubp1_program_requestor(hubp, rq_regs); 62986be9a04SYue Hin Lau hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 63086be9a04SYue Hin Lau hubp1_vready_workaround(hubp, pipe_dest); 63186be9a04SYue Hin Lau } 63286be9a04SYue Hin Lau 63386be9a04SYue Hin Lau bool hubp1_is_flip_pending(struct hubp *hubp) 63486be9a04SYue Hin Lau { 63586be9a04SYue Hin Lau uint32_t flip_pending = 0; 63686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 63786be9a04SYue Hin Lau struct dc_plane_address earliest_inuse_address; 63886be9a04SYue Hin Lau 63986be9a04SYue Hin Lau REG_GET(DCSURF_FLIP_CONTROL, 64086be9a04SYue Hin Lau SURFACE_FLIP_PENDING, &flip_pending); 64186be9a04SYue Hin Lau 64286be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 64386be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 64486be9a04SYue Hin Lau 64586be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 64686be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 64786be9a04SYue Hin Lau 64886be9a04SYue Hin Lau if (flip_pending) 64986be9a04SYue Hin Lau return true; 65086be9a04SYue Hin Lau 65186be9a04SYue Hin Lau if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 65286be9a04SYue Hin Lau return true; 65386be9a04SYue Hin Lau 65486be9a04SYue Hin Lau hubp->current_address = hubp->request_address; 65586be9a04SYue Hin Lau return false; 65686be9a04SYue Hin Lau } 65786be9a04SYue Hin Lau 65886be9a04SYue Hin Lau uint32_t aperture_default_system = 1; 65986be9a04SYue Hin Lau uint32_t context0_default_system; /* = 0;*/ 66086be9a04SYue Hin Lau 66186be9a04SYue Hin Lau static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 66286be9a04SYue Hin Lau struct vm_system_aperture_param *apt) 66386be9a04SYue Hin Lau { 66486be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 66586be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 66686be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 66786be9a04SYue Hin Lau PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 66886be9a04SYue Hin Lau 66986be9a04SYue Hin Lau mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 67086be9a04SYue Hin Lau mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 67186be9a04SYue Hin Lau mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 67286be9a04SYue Hin Lau 67386be9a04SYue Hin Lau REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 67486be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 67586be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 67686be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 67786be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 67886be9a04SYue Hin Lau 67986be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 68086be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 68186be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 68286be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 68386be9a04SYue Hin Lau 68486be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 68586be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 68686be9a04SYue Hin Lau REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 68786be9a04SYue Hin Lau MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 68886be9a04SYue Hin Lau } 68986be9a04SYue Hin Lau 69086be9a04SYue Hin Lau static void hubp1_set_vm_context0_settings(struct hubp *hubp, 69186be9a04SYue Hin Lau const struct vm_context0_param *vm0) 69286be9a04SYue Hin Lau { 69386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 69486be9a04SYue Hin Lau /* pte base */ 69586be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 69686be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 69786be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 69886be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 69986be9a04SYue Hin Lau 70086be9a04SYue Hin Lau /* pte start */ 70186be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 70286be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 70386be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 70486be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 70586be9a04SYue Hin Lau 70686be9a04SYue Hin Lau /* pte end */ 70786be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 70886be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 70986be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 71086be9a04SYue Hin Lau VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 71186be9a04SYue Hin Lau 71286be9a04SYue Hin Lau /* fault handling */ 71386be9a04SYue Hin Lau REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 71486be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 71586be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 71686be9a04SYue Hin Lau REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 71786be9a04SYue Hin Lau VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 71886be9a04SYue Hin Lau 71986be9a04SYue Hin Lau /* control: enable VM PTE*/ 72086be9a04SYue Hin Lau REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 72186be9a04SYue Hin Lau ENABLE_L1_TLB, 1, 72286be9a04SYue Hin Lau SYSTEM_ACCESS_MODE, 3); 72386be9a04SYue Hin Lau } 72486be9a04SYue Hin Lau 72586be9a04SYue Hin Lau void min_set_viewport( 72686be9a04SYue Hin Lau struct hubp *hubp, 72786be9a04SYue Hin Lau const struct rect *viewport, 72886be9a04SYue Hin Lau const struct rect *viewport_c) 72986be9a04SYue Hin Lau { 73086be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73186be9a04SYue Hin Lau 73286be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 73386be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, viewport->width, 73486be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, viewport->height); 73586be9a04SYue Hin Lau 73686be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 73786be9a04SYue Hin Lau PRI_VIEWPORT_X_START, viewport->x, 73886be9a04SYue Hin Lau PRI_VIEWPORT_Y_START, viewport->y); 73986be9a04SYue Hin Lau 74086be9a04SYue Hin Lau /*for stereo*/ 74186be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 74286be9a04SYue Hin Lau SEC_VIEWPORT_WIDTH, viewport->width, 74386be9a04SYue Hin Lau SEC_VIEWPORT_HEIGHT, viewport->height); 74486be9a04SYue Hin Lau 74586be9a04SYue Hin Lau REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 74686be9a04SYue Hin Lau SEC_VIEWPORT_X_START, viewport->x, 74786be9a04SYue Hin Lau SEC_VIEWPORT_Y_START, viewport->y); 74886be9a04SYue Hin Lau 74986be9a04SYue Hin Lau /* DC supports NV12 only at the moment */ 75086be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 75186be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH_C, viewport_c->width, 75286be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 75386be9a04SYue Hin Lau 75486be9a04SYue Hin Lau REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 75586be9a04SYue Hin Lau PRI_VIEWPORT_X_START_C, viewport_c->x, 75686be9a04SYue Hin Lau PRI_VIEWPORT_Y_START_C, viewport_c->y); 75786be9a04SYue Hin Lau } 75886be9a04SYue Hin Lau 7590a93dc7fSDmytro Laktyushkin void hubp1_read_state(struct hubp *hubp, 76086be9a04SYue Hin Lau struct dcn_hubp_state *s) 76186be9a04SYue Hin Lau { 7620a93dc7fSDmytro Laktyushkin struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 7630a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 7640a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 7650a93dc7fSDmytro Laktyushkin struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 7660a93dc7fSDmytro Laktyushkin 7670a93dc7fSDmytro Laktyushkin /* Requester */ 7680a93dc7fSDmytro Laktyushkin REG_GET(HUBPRET_CONTROL, 7690a93dc7fSDmytro Laktyushkin DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 7700a93dc7fSDmytro Laktyushkin REG_GET_4(DCN_EXPANSION_MODE, 7710a93dc7fSDmytro Laktyushkin DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 7720a93dc7fSDmytro Laktyushkin PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 7730a93dc7fSDmytro Laktyushkin MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 7740a93dc7fSDmytro Laktyushkin CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 7750a93dc7fSDmytro Laktyushkin REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 7760a93dc7fSDmytro Laktyushkin CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 7770a93dc7fSDmytro Laktyushkin MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 7780a93dc7fSDmytro Laktyushkin META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 7790a93dc7fSDmytro Laktyushkin MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 7800a93dc7fSDmytro Laktyushkin DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 7810a93dc7fSDmytro Laktyushkin MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 7820a93dc7fSDmytro Laktyushkin SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 7830a93dc7fSDmytro Laktyushkin PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 7840a93dc7fSDmytro Laktyushkin REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 7850a93dc7fSDmytro Laktyushkin CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 7860a93dc7fSDmytro Laktyushkin MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 7870a93dc7fSDmytro Laktyushkin META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 7880a93dc7fSDmytro Laktyushkin MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 7890a93dc7fSDmytro Laktyushkin DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 7900a93dc7fSDmytro Laktyushkin MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 7910a93dc7fSDmytro Laktyushkin SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 7920a93dc7fSDmytro Laktyushkin PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 7930a93dc7fSDmytro Laktyushkin 7940a93dc7fSDmytro Laktyushkin /* DLG - Per hubp */ 7950a93dc7fSDmytro Laktyushkin REG_GET_2(BLANK_OFFSET_0, 7960a93dc7fSDmytro Laktyushkin REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 7970a93dc7fSDmytro Laktyushkin DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 7980a93dc7fSDmytro Laktyushkin 7990a93dc7fSDmytro Laktyushkin REG_GET(BLANK_OFFSET_1, 8000a93dc7fSDmytro Laktyushkin MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 8010a93dc7fSDmytro Laktyushkin 8020a93dc7fSDmytro Laktyushkin REG_GET(DST_DIMENSIONS, 8030a93dc7fSDmytro Laktyushkin REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 8040a93dc7fSDmytro Laktyushkin 8050a93dc7fSDmytro Laktyushkin REG_GET_2(DST_AFTER_SCALER, 8060a93dc7fSDmytro Laktyushkin REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 8070a93dc7fSDmytro Laktyushkin DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 8080a93dc7fSDmytro Laktyushkin 8090a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS)) 8100a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINS, 8110a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8120a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8130a93dc7fSDmytro Laktyushkin else 8140a93dc7fSDmytro Laktyushkin REG_GET_2(PREFETCH_SETTINGS, 8150a93dc7fSDmytro Laktyushkin DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 8160a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 8170a93dc7fSDmytro Laktyushkin 8180a93dc7fSDmytro Laktyushkin REG_GET_2(VBLANK_PARAMETERS_0, 8190a93dc7fSDmytro Laktyushkin DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 8200a93dc7fSDmytro Laktyushkin DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 8210a93dc7fSDmytro Laktyushkin 8220a93dc7fSDmytro Laktyushkin REG_GET(REF_FREQ_TO_PIX_FREQ, 8230a93dc7fSDmytro Laktyushkin REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 8240a93dc7fSDmytro Laktyushkin 8250a93dc7fSDmytro Laktyushkin /* DLG - Per luma/chroma */ 8260a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_1, 8270a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 8280a93dc7fSDmytro Laktyushkin 8290a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_3, 8300a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 8310a93dc7fSDmytro Laktyushkin 8320a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_0)) 8330a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_0, 8340a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 8350a93dc7fSDmytro Laktyushkin 8360a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_1)) 8370a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_1, 8380a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 8390a93dc7fSDmytro Laktyushkin 8400a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_4, 8410a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 8420a93dc7fSDmytro Laktyushkin 8430a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_5, 8440a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 8450a93dc7fSDmytro Laktyushkin 8460a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY_PRE, 8470a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 8480a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 8490a93dc7fSDmytro Laktyushkin 8500a93dc7fSDmytro Laktyushkin REG_GET_2(PER_LINE_DELIVERY, 8510a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 8520a93dc7fSDmytro Laktyushkin REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 8530a93dc7fSDmytro Laktyushkin 8540a93dc7fSDmytro Laktyushkin if (REG(PREFETCH_SETTINS_C)) 8550a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINS_C, 8560a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 8570a93dc7fSDmytro Laktyushkin else 8580a93dc7fSDmytro Laktyushkin REG_GET(PREFETCH_SETTINGS_C, 8590a93dc7fSDmytro Laktyushkin VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 8600a93dc7fSDmytro Laktyushkin 8610a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_2, 8620a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 8630a93dc7fSDmytro Laktyushkin 8640a93dc7fSDmytro Laktyushkin REG_GET(VBLANK_PARAMETERS_4, 8650a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 8660a93dc7fSDmytro Laktyushkin 8670a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_2)) 8680a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_2, 8690a93dc7fSDmytro Laktyushkin DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 8700a93dc7fSDmytro Laktyushkin 8710a93dc7fSDmytro Laktyushkin if (REG(NOM_PARAMETERS_3)) 8720a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_3, 8730a93dc7fSDmytro Laktyushkin REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 8740a93dc7fSDmytro Laktyushkin 8750a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_6, 8760a93dc7fSDmytro Laktyushkin DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 8770a93dc7fSDmytro Laktyushkin 8780a93dc7fSDmytro Laktyushkin REG_GET(NOM_PARAMETERS_7, 8790a93dc7fSDmytro Laktyushkin REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 8800a93dc7fSDmytro Laktyushkin 8810a93dc7fSDmytro Laktyushkin /* TTU - per hubp */ 8820a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_TTU_QOS_WM, 8830a93dc7fSDmytro Laktyushkin QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 8840a93dc7fSDmytro Laktyushkin QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 8850a93dc7fSDmytro Laktyushkin 8860a93dc7fSDmytro Laktyushkin REG_GET_2(DCN_GLOBAL_TTU_CNTL, 8870a93dc7fSDmytro Laktyushkin MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 8880a93dc7fSDmytro Laktyushkin QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 8890a93dc7fSDmytro Laktyushkin 8900a93dc7fSDmytro Laktyushkin /* TTU - per luma/chroma */ 8910a93dc7fSDmytro Laktyushkin /* Assumed surf0 is luma and 1 is chroma */ 8920a93dc7fSDmytro Laktyushkin 8930a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF0_TTU_CNTL0, 8940a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 8950a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 8960a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 8970a93dc7fSDmytro Laktyushkin 8980a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF0_TTU_CNTL1, 8990a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9000a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_l); 9010a93dc7fSDmytro Laktyushkin 9020a93dc7fSDmytro Laktyushkin REG_GET_3(DCN_SURF1_TTU_CNTL0, 9030a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 9040a93dc7fSDmytro Laktyushkin QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 9050a93dc7fSDmytro Laktyushkin QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 9060a93dc7fSDmytro Laktyushkin 9070a93dc7fSDmytro Laktyushkin REG_GET(DCN_SURF1_TTU_CNTL1, 9080a93dc7fSDmytro Laktyushkin REFCYC_PER_REQ_DELIVERY_PRE, 9090a93dc7fSDmytro Laktyushkin &ttu_attr->refcyc_per_req_delivery_pre_c); 9100a93dc7fSDmytro Laktyushkin 9110a93dc7fSDmytro Laktyushkin /* Rest of hubp */ 91286be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONFIG, 91386be9a04SYue Hin Lau SURFACE_PIXEL_FORMAT, &s->pixel_format); 91486be9a04SYue Hin Lau 91586be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 91686be9a04SYue Hin Lau SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 91786be9a04SYue Hin Lau 91886be9a04SYue Hin Lau REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 91986be9a04SYue Hin Lau PRI_VIEWPORT_WIDTH, &s->viewport_width, 92086be9a04SYue Hin Lau PRI_VIEWPORT_HEIGHT, &s->viewport_height); 92186be9a04SYue Hin Lau 92286be9a04SYue Hin Lau REG_GET_2(DCSURF_SURFACE_CONFIG, 92386be9a04SYue Hin Lau ROTATION_ANGLE, &s->rotation_angle, 92486be9a04SYue Hin Lau H_MIRROR_EN, &s->h_mirror_en); 92586be9a04SYue Hin Lau 92686be9a04SYue Hin Lau REG_GET(DCSURF_TILING_CONFIG, 92786be9a04SYue Hin Lau SW_MODE, &s->sw_mode); 92886be9a04SYue Hin Lau 92986be9a04SYue Hin Lau REG_GET(DCSURF_SURFACE_CONTROL, 93086be9a04SYue Hin Lau PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 93186be9a04SYue Hin Lau 93286be9a04SYue Hin Lau REG_GET_3(DCHUBP_CNTL, 93386be9a04SYue Hin Lau HUBP_BLANK_EN, &s->blank_en, 93486be9a04SYue Hin Lau HUBP_TTU_DISABLE, &s->ttu_disable, 93586be9a04SYue Hin Lau HUBP_UNDERFLOW_STATUS, &s->underflow_status); 93686be9a04SYue Hin Lau 93786be9a04SYue Hin Lau REG_GET(DCN_GLOBAL_TTU_CNTL, 93886be9a04SYue Hin Lau MIN_TTU_VBLANK, &s->min_ttu_vblank); 93986be9a04SYue Hin Lau 94086be9a04SYue Hin Lau REG_GET_2(DCN_TTU_QOS_WM, 94186be9a04SYue Hin Lau QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 94286be9a04SYue Hin Lau QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 94386be9a04SYue Hin Lau } 94486be9a04SYue Hin Lau 94536192e7eSEric Bernstein enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 94686be9a04SYue Hin Lau { 94786be9a04SYue Hin Lau enum cursor_pitch hw_pitch; 94886be9a04SYue Hin Lau 94986be9a04SYue Hin Lau switch (pitch) { 95086be9a04SYue Hin Lau case 64: 95186be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 95286be9a04SYue Hin Lau break; 95386be9a04SYue Hin Lau case 128: 95486be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_128_PIXELS; 95586be9a04SYue Hin Lau break; 95686be9a04SYue Hin Lau case 256: 95786be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_256_PIXELS; 95886be9a04SYue Hin Lau break; 95986be9a04SYue Hin Lau default: 96086be9a04SYue Hin Lau DC_ERR("Invalid cursor pitch of %d. " 96186be9a04SYue Hin Lau "Only 64/128/256 is supported on DCN.\n", pitch); 96286be9a04SYue Hin Lau hw_pitch = CURSOR_PITCH_64_PIXELS; 96386be9a04SYue Hin Lau break; 96486be9a04SYue Hin Lau } 96586be9a04SYue Hin Lau return hw_pitch; 96686be9a04SYue Hin Lau } 96786be9a04SYue Hin Lau 96836192e7eSEric Bernstein static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 96986be9a04SYue Hin Lau unsigned int cur_width, 97086be9a04SYue Hin Lau enum dc_cursor_color_format format) 97186be9a04SYue Hin Lau { 97286be9a04SYue Hin Lau enum cursor_lines_per_chunk line_per_chunk; 97386be9a04SYue Hin Lau 97486be9a04SYue Hin Lau if (format == CURSOR_MODE_MONO) 97586be9a04SYue Hin Lau /* impl B. expansion in CUR Buffer reader */ 97686be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 97786be9a04SYue Hin Lau else if (cur_width <= 32) 97886be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 97986be9a04SYue Hin Lau else if (cur_width <= 64) 98086be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 98186be9a04SYue Hin Lau else if (cur_width <= 128) 98286be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 98386be9a04SYue Hin Lau else 98486be9a04SYue Hin Lau line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 98586be9a04SYue Hin Lau 98686be9a04SYue Hin Lau return line_per_chunk; 98786be9a04SYue Hin Lau } 98886be9a04SYue Hin Lau 98986be9a04SYue Hin Lau void hubp1_cursor_set_attributes( 99086be9a04SYue Hin Lau struct hubp *hubp, 99186be9a04SYue Hin Lau const struct dc_cursor_attributes *attr) 99286be9a04SYue Hin Lau { 99386be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 99436192e7eSEric Bernstein enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 99536192e7eSEric Bernstein enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 99686be9a04SYue Hin Lau attr->width, attr->color_format); 99786be9a04SYue Hin Lau 99886be9a04SYue Hin Lau hubp->curs_attr = *attr; 99986be9a04SYue Hin Lau 100086be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 100186be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 100286be9a04SYue Hin Lau REG_UPDATE(CURSOR_SURFACE_ADDRESS, 100386be9a04SYue Hin Lau CURSOR_SURFACE_ADDRESS, attr->address.low_part); 100486be9a04SYue Hin Lau 100586be9a04SYue Hin Lau REG_UPDATE_2(CURSOR_SIZE, 100686be9a04SYue Hin Lau CURSOR_WIDTH, attr->width, 100786be9a04SYue Hin Lau CURSOR_HEIGHT, attr->height); 100836192e7eSEric Bernstein 100986be9a04SYue Hin Lau REG_UPDATE_3(CURSOR_CONTROL, 101086be9a04SYue Hin Lau CURSOR_MODE, attr->color_format, 101186be9a04SYue Hin Lau CURSOR_PITCH, hw_pitch, 101286be9a04SYue Hin Lau CURSOR_LINES_PER_CHUNK, lpc); 101336192e7eSEric Bernstein 1014e9be38b4SEric Bernstein REG_SET_2(CURSOR_SETTINS, 0, 1015e9be38b4SEric Bernstein /* no shift of the cursor HDL schedule */ 1016e9be38b4SEric Bernstein CURSOR0_DST_Y_OFFSET, 0, 1017e9be38b4SEric Bernstein /* used to shift the cursor chunk request deadline */ 1018e9be38b4SEric Bernstein CURSOR0_CHUNK_HDL_ADJUST, 3); 101986be9a04SYue Hin Lau } 102086be9a04SYue Hin Lau 102186be9a04SYue Hin Lau void hubp1_cursor_set_position( 102286be9a04SYue Hin Lau struct hubp *hubp, 102386be9a04SYue Hin Lau const struct dc_cursor_position *pos, 102486be9a04SYue Hin Lau const struct dc_cursor_mi_param *param) 102586be9a04SYue Hin Lau { 102686be9a04SYue Hin Lau struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 102786be9a04SYue Hin Lau int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start; 102886be9a04SYue Hin Lau uint32_t cur_en = pos->enable ? 1 : 0; 102986be9a04SYue Hin Lau uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 103086be9a04SYue Hin Lau 103186be9a04SYue Hin Lau /* 103286be9a04SYue Hin Lau * Guard aganst cursor_set_position() from being called with invalid 103386be9a04SYue Hin Lau * attributes 103486be9a04SYue Hin Lau * 103586be9a04SYue Hin Lau * TODO: Look at combining cursor_set_position() and 103686be9a04SYue Hin Lau * cursor_set_attributes() into cursor_update() 103786be9a04SYue Hin Lau */ 103886be9a04SYue Hin Lau if (hubp->curs_attr.address.quad_part == 0) 103986be9a04SYue Hin Lau return; 104086be9a04SYue Hin Lau 104186be9a04SYue Hin Lau dst_x_offset *= param->ref_clk_khz; 104286be9a04SYue Hin Lau dst_x_offset /= param->pixel_clk_khz; 104386be9a04SYue Hin Lau 104486be9a04SYue Hin Lau ASSERT(param->h_scale_ratio.value); 104586be9a04SYue Hin Lau 104686be9a04SYue Hin Lau if (param->h_scale_ratio.value) 104786be9a04SYue Hin Lau dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div( 104886be9a04SYue Hin Lau dal_fixed31_32_from_int(dst_x_offset), 104986be9a04SYue Hin Lau param->h_scale_ratio)); 105086be9a04SYue Hin Lau 105186be9a04SYue Hin Lau if (src_x_offset >= (int)param->viewport_width) 105286be9a04SYue Hin Lau cur_en = 0; /* not visible beyond right edge*/ 105386be9a04SYue Hin Lau 105435d13315SMartin Tsai if (src_x_offset + (int)hubp->curs_attr.width <= 0) 105586be9a04SYue Hin Lau cur_en = 0; /* not visible beyond left edge*/ 105686be9a04SYue Hin Lau 105786be9a04SYue Hin Lau if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 105836192e7eSEric Bernstein hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 105936192e7eSEric Bernstein 106086be9a04SYue Hin Lau REG_UPDATE(CURSOR_CONTROL, 106186be9a04SYue Hin Lau CURSOR_ENABLE, cur_en); 106286be9a04SYue Hin Lau 106386be9a04SYue Hin Lau REG_SET_2(CURSOR_POSITION, 0, 106486be9a04SYue Hin Lau CURSOR_X_POSITION, pos->x, 106586be9a04SYue Hin Lau CURSOR_Y_POSITION, pos->y); 106686be9a04SYue Hin Lau 106786be9a04SYue Hin Lau REG_SET_2(CURSOR_HOT_SPOT, 0, 106886be9a04SYue Hin Lau CURSOR_HOT_SPOT_X, pos->x_hotspot, 106986be9a04SYue Hin Lau CURSOR_HOT_SPOT_Y, pos->y_hotspot); 107086be9a04SYue Hin Lau 107186be9a04SYue Hin Lau REG_SET(CURSOR_DST_OFFSET, 0, 107286be9a04SYue Hin Lau CURSOR_DST_X_OFFSET, dst_x_offset); 107386be9a04SYue Hin Lau /* TODO Handle surface pixel formats other than 4:4:4 */ 107486be9a04SYue Hin Lau } 107586be9a04SYue Hin Lau 1076c8242b98SYongqiang Sun void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1077c8242b98SYongqiang Sun { 1078c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1079c8242b98SYongqiang Sun uint32_t clk_enable = enable ? 1 : 0; 1080c8242b98SYongqiang Sun 1081c8242b98SYongqiang Sun REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1082c8242b98SYongqiang Sun } 1083c8242b98SYongqiang Sun 1084c8242b98SYongqiang Sun void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1085c8242b98SYongqiang Sun { 1086c8242b98SYongqiang Sun struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1087c8242b98SYongqiang Sun 1088c8242b98SYongqiang Sun REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1089c8242b98SYongqiang Sun } 1090c8242b98SYongqiang Sun 109186be9a04SYue Hin Lau static struct hubp_funcs dcn10_hubp_funcs = { 109286be9a04SYue Hin Lau .hubp_program_surface_flip_and_addr = 109386be9a04SYue Hin Lau hubp1_program_surface_flip_and_addr, 109486be9a04SYue Hin Lau .hubp_program_surface_config = 109586be9a04SYue Hin Lau hubp1_program_surface_config, 109686be9a04SYue Hin Lau .hubp_is_flip_pending = hubp1_is_flip_pending, 109786be9a04SYue Hin Lau .hubp_setup = hubp1_setup, 109886be9a04SYue Hin Lau .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 109986be9a04SYue Hin Lau .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 110086be9a04SYue Hin Lau .set_blank = hubp1_set_blank, 110186be9a04SYue Hin Lau .dcc_control = hubp1_dcc_control, 110286be9a04SYue Hin Lau .mem_program_viewport = min_set_viewport, 110386be9a04SYue Hin Lau .set_hubp_blank_en = hubp1_set_hubp_blank_en, 110486be9a04SYue Hin Lau .set_cursor_attributes = hubp1_cursor_set_attributes, 110586be9a04SYue Hin Lau .set_cursor_position = hubp1_cursor_set_position, 11061dbac201SYongqiang Sun .hubp_disconnect = hubp1_disconnect, 1107c8242b98SYongqiang Sun .hubp_clk_cntl = hubp1_clk_cntl, 1108c8242b98SYongqiang Sun .hubp_vtg_sel = hubp1_vtg_sel, 11090a93dc7fSDmytro Laktyushkin .hubp_read_state = hubp1_read_state, 111086be9a04SYue Hin Lau }; 111186be9a04SYue Hin Lau 111286be9a04SYue Hin Lau /*****************************************/ 111386be9a04SYue Hin Lau /* Constructor, Destructor */ 111486be9a04SYue Hin Lau /*****************************************/ 111586be9a04SYue Hin Lau 111686be9a04SYue Hin Lau void dcn10_hubp_construct( 111786be9a04SYue Hin Lau struct dcn10_hubp *hubp1, 111886be9a04SYue Hin Lau struct dc_context *ctx, 111986be9a04SYue Hin Lau uint32_t inst, 1120c42c275cSYue Hin Lau const struct dcn_mi_registers *hubp_regs, 1121c42c275cSYue Hin Lau const struct dcn_mi_shift *hubp_shift, 1122c42c275cSYue Hin Lau const struct dcn_mi_mask *hubp_mask) 112386be9a04SYue Hin Lau { 112486be9a04SYue Hin Lau hubp1->base.funcs = &dcn10_hubp_funcs; 112586be9a04SYue Hin Lau hubp1->base.ctx = ctx; 1126c42c275cSYue Hin Lau hubp1->hubp_regs = hubp_regs; 1127c42c275cSYue Hin Lau hubp1->hubp_shift = hubp_shift; 1128c42c275cSYue Hin Lau hubp1->hubp_mask = hubp_mask; 112986be9a04SYue Hin Lau hubp1->base.inst = inst; 113086be9a04SYue Hin Lau hubp1->base.opp_id = 0xf; 113186be9a04SYue Hin Lau hubp1->base.mpcc_id = 0xf; 113286be9a04SYue Hin Lau } 113386be9a04SYue Hin Lau 113486be9a04SYue Hin Lau 1135