1 /* 2 * Copyright 2012-17 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 27 28 #include "reg_helper.h" 29 #include "resource.h" 30 #include "dwb.h" 31 #include "dcn10_dwb.h" 32 33 34 #define REG(reg)\ 35 dwbc10->dwbc_regs->reg 36 37 #define CTX \ 38 dwbc10->base.ctx 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name 43 44 #define TO_DCN10_DWBC(dwbc_base) \ 45 container_of(dwbc_base, struct dcn10_dwbc, base) 46 47 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) 48 { 49 if (caps) { 50 caps->adapter_id = 0; /* we only support 1 adapter currently */ 51 caps->hw_version = DCN_VERSION_1_0; 52 caps->num_pipes = 2; 53 memset(&caps->reserved, 0, sizeof(caps->reserved)); 54 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); 55 caps->sw_version = dwb_ver_1_0; 56 caps->caps.support_dwb = true; 57 caps->caps.support_ogam = false; 58 caps->caps.support_wbscl = true; 59 caps->caps.support_ocsc = false; 60 return true; 61 } else { 62 return false; 63 } 64 } 65 66 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) 67 { 68 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); 69 70 /* disable first. */ 71 dwbc->funcs->disable(dwbc); 72 73 /* disable power gating */ 74 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1, 75 DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1, 76 WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1); 77 78 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); 79 80 return true; 81 } 82 83 static bool dwb1_disable(struct dwbc *dwbc) 84 { 85 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); 86 87 /* disable CNV */ 88 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0); 89 90 /* disable WB */ 91 REG_UPDATE(WB_ENABLE, WB_ENABLE, 0); 92 93 /* soft reset */ 94 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1); 95 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0); 96 97 /* enable power gating */ 98 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0, 99 DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0, 100 WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0); 101 102 return true; 103 } 104 105 const struct dwbc_funcs dcn10_dwbc_funcs = { 106 .get_caps = dwb1_get_caps, 107 .enable = dwb1_enable, 108 .disable = dwb1_disable, 109 .update = NULL, 110 .set_stereo = NULL, 111 .set_new_content = NULL, 112 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 113 .set_warmup = NULL, 114 #endif 115 .dwb_set_scaler = NULL, 116 }; 117 118 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, 119 struct dc_context *ctx, 120 const struct dcn10_dwbc_registers *dwbc_regs, 121 const struct dcn10_dwbc_shift *dwbc_shift, 122 const struct dcn10_dwbc_mask *dwbc_mask, 123 int inst) 124 { 125 dwbc10->base.ctx = ctx; 126 127 dwbc10->base.inst = inst; 128 dwbc10->base.funcs = &dcn10_dwbc_funcs; 129 130 dwbc10->dwbc_regs = dwbc_regs; 131 dwbc10->dwbc_shift = dwbc_shift; 132 dwbc10->dwbc_mask = dwbc_mask; 133 } 134 135 136 #endif 137