1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn10_dpp.h" 32 #include "basics/conversion.h" 33 34 35 #define NUM_PHASES 64 36 #define HORZ_MAX_TAPS 8 37 #define VERT_MAX_TAPS 8 38 39 #define BLACK_OFFSET_RGB_Y 0x0 40 #define BLACK_OFFSET_CBCR 0x8000 41 42 #define REG(reg)\ 43 dpp->tf_regs->reg 44 45 #define CTX \ 46 dpp->base.ctx 47 48 #undef FN 49 #define FN(reg_name, field_name) \ 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 52 enum dcn10_coef_filter_type_sel { 53 SCL_COEF_LUMA_VERT_FILTER = 0, 54 SCL_COEF_LUMA_HORZ_FILTER = 1, 55 SCL_COEF_CHROMA_VERT_FILTER = 2, 56 SCL_COEF_CHROMA_HORZ_FILTER = 3, 57 SCL_COEF_ALPHA_VERT_FILTER = 4, 58 SCL_COEF_ALPHA_HORZ_FILTER = 5 59 }; 60 61 enum dscl_autocal_mode { 62 AUTOCAL_MODE_OFF = 0, 63 64 /* Autocal calculate the scaling ratio and initial phase and the 65 * DSCL_MODE_SEL must be set to 1 66 */ 67 AUTOCAL_MODE_AUTOSCALE = 1, 68 /* Autocal perform auto centering without replication and the 69 * DSCL_MODE_SEL must be set to 0 70 */ 71 AUTOCAL_MODE_AUTOCENTER = 2, 72 /* Autocal perform auto centering and auto replication and the 73 * DSCL_MODE_SEL must be set to 0 74 */ 75 AUTOCAL_MODE_AUTOREPLICATE = 3 76 }; 77 78 enum dscl_mode_sel { 79 DSCL_MODE_SCALING_444_BYPASS = 0, 80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 85 DSCL_MODE_DSCL_BYPASS = 6 86 }; 87 88 static void dpp1_dscl_set_overscan( 89 struct dcn10_dpp *dpp, 90 const struct scaler_data *data) 91 { 92 uint32_t left = data->recout.x; 93 uint32_t top = data->recout.y; 94 95 int right = data->h_active - data->recout.x - data->recout.width; 96 int bottom = data->v_active - data->recout.y - data->recout.height; 97 98 if (right < 0) { 99 BREAK_TO_DEBUGGER(); 100 right = 0; 101 } 102 if (bottom < 0) { 103 BREAK_TO_DEBUGGER(); 104 bottom = 0; 105 } 106 107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, 108 EXT_OVERSCAN_LEFT, left, 109 EXT_OVERSCAN_RIGHT, right); 110 111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, 112 EXT_OVERSCAN_BOTTOM, bottom, 113 EXT_OVERSCAN_TOP, top); 114 } 115 116 static void dpp1_dscl_set_otg_blank( 117 struct dcn10_dpp *dpp, const struct scaler_data *data) 118 { 119 uint32_t h_blank_start = data->h_active; 120 uint32_t h_blank_end = 0; 121 uint32_t v_blank_start = data->v_active; 122 uint32_t v_blank_end = 0; 123 124 REG_SET_2(OTG_H_BLANK, 0, 125 OTG_H_BLANK_START, h_blank_start, 126 OTG_H_BLANK_END, h_blank_end); 127 128 REG_SET_2(OTG_V_BLANK, 0, 129 OTG_V_BLANK_START, v_blank_start, 130 OTG_V_BLANK_END, v_blank_end); 131 } 132 133 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) 134 { 135 if (depth == LB_PIXEL_DEPTH_30BPP) 136 return 0; /* 10 bpc */ 137 else if (depth == LB_PIXEL_DEPTH_24BPP) 138 return 1; /* 8 bpc */ 139 else if (depth == LB_PIXEL_DEPTH_18BPP) 140 return 2; /* 6 bpc */ 141 else if (depth == LB_PIXEL_DEPTH_36BPP) 142 return 3; /* 12 bpc */ 143 else { 144 ASSERT(0); 145 return -1; /* Unsupported */ 146 } 147 } 148 149 static bool dpp1_dscl_is_video_format(enum pixel_format format) 150 { 151 if (format >= PIXEL_FORMAT_VIDEO_BEGIN 152 && format <= PIXEL_FORMAT_VIDEO_END) 153 return true; 154 else 155 return false; 156 } 157 158 static bool dpp1_dscl_is_420_format(enum pixel_format format) 159 { 160 if (format == PIXEL_FORMAT_420BPP8 || 161 format == PIXEL_FORMAT_420BPP10) 162 return true; 163 else 164 return false; 165 } 166 167 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode( 168 struct dpp *dpp_base, 169 const struct scaler_data *data, 170 bool dbg_always_scale) 171 { 172 const long long one = dc_fixpt_one.value; 173 174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 175 /* DSCL is processing data in fixed format */ 176 if (data->format == PIXEL_FORMAT_FP16) 177 return DSCL_MODE_DSCL_BYPASS; 178 } 179 180 if (data->ratios.horz.value == one 181 && data->ratios.vert.value == one 182 && data->ratios.horz_c.value == one 183 && data->ratios.vert_c.value == one 184 && !dbg_always_scale) 185 return DSCL_MODE_SCALING_444_BYPASS; 186 187 if (!dpp1_dscl_is_420_format(data->format)) { 188 if (dpp1_dscl_is_video_format(data->format)) 189 return DSCL_MODE_SCALING_444_YCBCR_ENABLE; 190 else 191 return DSCL_MODE_SCALING_444_RGB_ENABLE; 192 } 193 if (data->ratios.horz.value == one && data->ratios.vert.value == one) 194 return DSCL_MODE_SCALING_420_LUMA_BYPASS; 195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) 196 return DSCL_MODE_SCALING_420_CHROMA_BYPASS; 197 198 return DSCL_MODE_SCALING_420_YCBCR_ENABLE; 199 } 200 201 static void dpp1_dscl_set_lb( 202 struct dcn10_dpp *dpp, 203 const struct line_buffer_params *lb_params, 204 enum lb_memory_config mem_size_config) 205 { 206 /* LB */ 207 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 208 /* DSCL caps: pixel data processed in fixed format */ 209 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth); 210 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth; 211 212 REG_SET_7(LB_DATA_FORMAT, 0, 213 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */ 214 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */ 215 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */ 216 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */ 217 DITHER_EN, 0, /* Dithering enable: Disabled */ 218 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ 219 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ 220 } 221 else { 222 /* DSCL caps: pixel data processed in float format */ 223 REG_SET_2(LB_DATA_FORMAT, 0, 224 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ 225 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ 226 } 227 228 REG_SET_2(LB_MEMORY_CTRL, 0, 229 MEMORY_CONFIG, mem_size_config, 230 LB_MAX_PARTITIONS, 63); 231 } 232 233 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) 234 { 235 if (taps == 8) 236 return get_filter_8tap_64p(ratio); 237 else if (taps == 7) 238 return get_filter_7tap_64p(ratio); 239 else if (taps == 6) 240 return get_filter_6tap_64p(ratio); 241 else if (taps == 5) 242 return get_filter_5tap_64p(ratio); 243 else if (taps == 4) 244 return get_filter_4tap_64p(ratio); 245 else if (taps == 3) 246 return get_filter_3tap_64p(ratio); 247 else if (taps == 2) 248 return get_filter_2tap_64p(); 249 else if (taps == 1) 250 return NULL; 251 else { 252 /* should never happen, bug */ 253 BREAK_TO_DEBUGGER(); 254 return NULL; 255 } 256 } 257 258 static void dpp1_dscl_set_scaler_filter( 259 struct dcn10_dpp *dpp, 260 uint32_t taps, 261 enum dcn10_coef_filter_type_sel filter_type, 262 const uint16_t *filter) 263 { 264 const int tap_pairs = (taps + 1) / 2; 265 int phase; 266 int pair; 267 uint16_t odd_coef, even_coef; 268 269 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, 270 SCL_COEF_RAM_TAP_PAIR_IDX, 0, 271 SCL_COEF_RAM_PHASE, 0, 272 SCL_COEF_RAM_FILTER_TYPE, filter_type); 273 274 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { 275 for (pair = 0; pair < tap_pairs; pair++) { 276 even_coef = filter[phase * taps + 2 * pair]; 277 if ((pair * 2 + 1) < taps) 278 odd_coef = filter[phase * taps + 2 * pair + 1]; 279 else 280 odd_coef = 0; 281 282 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, 283 /* Even tap coefficient (bits 1:0 fixed to 0) */ 284 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, 285 /* Write/read control for even coefficient */ 286 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1, 287 /* Odd tap coefficient (bits 1:0 fixed to 0) */ 288 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, 289 /* Write/read control for odd coefficient */ 290 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1); 291 } 292 } 293 294 } 295 296 static void dpp1_dscl_set_scl_filter( 297 struct dcn10_dpp *dpp, 298 const struct scaler_data *scl_data, 299 bool chroma_coef_mode) 300 { 301 bool h_2tap_hardcode_coef_en = false; 302 bool v_2tap_hardcode_coef_en = false; 303 bool h_2tap_sharp_en = false; 304 bool v_2tap_sharp_en = false; 305 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; 306 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; 307 bool coef_ram_current; 308 const uint16_t *filter_h = NULL; 309 const uint16_t *filter_v = NULL; 310 const uint16_t *filter_h_c = NULL; 311 const uint16_t *filter_v_c = NULL; 312 313 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 314 && scl_data->taps.h_taps_c < 3 315 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); 316 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 317 && scl_data->taps.v_taps_c < 3 318 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); 319 320 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0; 321 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0; 322 323 REG_UPDATE_6(DSCL_2TAP_CONTROL, 324 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en, 325 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, 326 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor, 327 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, 328 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en, 329 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor); 330 331 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) { 332 bool filter_updated = false; 333 334 filter_h = dpp1_dscl_get_filter_coeffs_64p( 335 scl_data->taps.h_taps, scl_data->ratios.horz); 336 filter_v = dpp1_dscl_get_filter_coeffs_64p( 337 scl_data->taps.v_taps, scl_data->ratios.vert); 338 339 filter_updated = (filter_h && (filter_h != dpp->filter_h)) 340 || (filter_v && (filter_v != dpp->filter_v)); 341 342 if (chroma_coef_mode) { 343 filter_h_c = dpp1_dscl_get_filter_coeffs_64p( 344 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); 345 filter_v_c = dpp1_dscl_get_filter_coeffs_64p( 346 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); 347 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c)) 348 || (filter_v_c && (filter_v_c != dpp->filter_v_c)); 349 } 350 351 if (filter_updated) { 352 uint32_t scl_mode = REG_READ(SCL_MODE); 353 354 if (!h_2tap_hardcode_coef_en && filter_h) { 355 dpp1_dscl_set_scaler_filter( 356 dpp, scl_data->taps.h_taps, 357 SCL_COEF_LUMA_HORZ_FILTER, filter_h); 358 } 359 dpp->filter_h = filter_h; 360 if (!v_2tap_hardcode_coef_en && filter_v) { 361 dpp1_dscl_set_scaler_filter( 362 dpp, scl_data->taps.v_taps, 363 SCL_COEF_LUMA_VERT_FILTER, filter_v); 364 } 365 dpp->filter_v = filter_v; 366 if (chroma_coef_mode) { 367 if (!h_2tap_hardcode_coef_en && filter_h_c) { 368 dpp1_dscl_set_scaler_filter( 369 dpp, scl_data->taps.h_taps_c, 370 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); 371 } 372 if (!v_2tap_hardcode_coef_en && filter_v_c) { 373 dpp1_dscl_set_scaler_filter( 374 dpp, scl_data->taps.v_taps_c, 375 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); 376 } 377 } 378 dpp->filter_h_c = filter_h_c; 379 dpp->filter_v_c = filter_v_c; 380 381 coef_ram_current = get_reg_field_value_ex( 382 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, 383 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); 384 385 /* Swap coefficient RAM and set chroma coefficient mode */ 386 REG_SET_2(SCL_MODE, scl_mode, 387 SCL_COEF_RAM_SELECT, !coef_ram_current, 388 SCL_CHROMA_COEF_MODE, chroma_coef_mode); 389 } 390 } 391 } 392 393 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth) 394 { 395 if (depth == LB_PIXEL_DEPTH_30BPP) 396 return 10; 397 else if (depth == LB_PIXEL_DEPTH_24BPP) 398 return 8; 399 else if (depth == LB_PIXEL_DEPTH_18BPP) 400 return 6; 401 else if (depth == LB_PIXEL_DEPTH_36BPP) 402 return 12; 403 else { 404 BREAK_TO_DEBUGGER(); 405 return -1; /* Unsupported */ 406 } 407 } 408 409 void dpp1_dscl_calc_lb_num_partitions( 410 const struct scaler_data *scl_data, 411 enum lb_memory_config lb_config, 412 int *num_part_y, 413 int *num_part_c) 414 { 415 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a, 416 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a; 417 418 int line_size = scl_data->viewport.width < scl_data->recout.width ? 419 scl_data->viewport.width : scl_data->recout.width; 420 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? 421 scl_data->viewport_c.width : scl_data->recout.width; 422 423 if (line_size == 0) 424 line_size = 1; 425 426 if (line_size_c == 0) 427 line_size_c = 1; 428 429 430 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth); 431 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */ 432 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */ 433 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ 434 435 if (lb_config == LB_MEMORY_CONFIG_1) { 436 lb_memory_size = 816; 437 lb_memory_size_c = 816; 438 lb_memory_size_a = 984; 439 } else if (lb_config == LB_MEMORY_CONFIG_2) { 440 lb_memory_size = 1088; 441 lb_memory_size_c = 1088; 442 lb_memory_size_a = 1312; 443 } else if (lb_config == LB_MEMORY_CONFIG_3) { 444 /* 420 mode: using 3rd mem from Y, Cr and Cb */ 445 lb_memory_size = 816 + 1088 + 848 + 848 + 848; 446 lb_memory_size_c = 816 + 1088; 447 lb_memory_size_a = 984 + 1312 + 456; 448 } else { 449 lb_memory_size = 816 + 1088 + 848; 450 lb_memory_size_c = 816 + 1088 + 848; 451 lb_memory_size_a = 984 + 1312 + 456; 452 } 453 *num_part_y = lb_memory_size / memory_line_size_y; 454 *num_part_c = lb_memory_size_c / memory_line_size_c; 455 num_partitions_a = lb_memory_size_a / memory_line_size_a; 456 457 if (scl_data->lb_params.alpha_en 458 && (num_partitions_a < *num_part_y)) 459 *num_part_y = num_partitions_a; 460 461 if (*num_part_y > 64) 462 *num_part_y = 64; 463 if (*num_part_c > 64) 464 *num_part_c = 64; 465 466 } 467 468 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) 469 { 470 if (ceil_vratio > 2) 471 return vtaps <= (num_partitions - ceil_vratio + 2); 472 else 473 return vtaps <= num_partitions; 474 } 475 476 /*find first match configuration which meets the min required lb size*/ 477 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, 478 const struct scaler_data *scl_data) 479 { 480 int num_part_y, num_part_c; 481 int vtaps = scl_data->taps.v_taps; 482 int vtaps_c = scl_data->taps.v_taps_c; 483 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); 484 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 485 enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0; 486 487 if (dpp->base.ctx->dc->debug.use_max_lb) 488 return mem_cfg; 489 490 dpp->base.caps->dscl_calc_lb_num_partitions( 491 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); 492 493 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 494 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 495 return LB_MEMORY_CONFIG_1; 496 497 dpp->base.caps->dscl_calc_lb_num_partitions( 498 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c); 499 500 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 501 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 502 return LB_MEMORY_CONFIG_2; 503 504 if (scl_data->format == PIXEL_FORMAT_420BPP8 505 || scl_data->format == PIXEL_FORMAT_420BPP10) { 506 dpp->base.caps->dscl_calc_lb_num_partitions( 507 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); 508 509 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 510 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 511 return LB_MEMORY_CONFIG_3; 512 } 513 514 dpp->base.caps->dscl_calc_lb_num_partitions( 515 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c); 516 517 /*Ensure we can support the requested number of vtaps*/ 518 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 519 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)); 520 521 return LB_MEMORY_CONFIG_0; 522 } 523 524 void dpp1_dscl_set_scaler_auto_scale( 525 struct dpp *dpp_base, 526 const struct scaler_data *scl_data) 527 { 528 enum lb_memory_config lb_config; 529 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 530 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode( 531 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); 532 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN 533 && scl_data->format <= PIXEL_FORMAT_VIDEO_END; 534 535 dpp1_dscl_set_overscan(dpp, scl_data); 536 537 dpp1_dscl_set_otg_blank(dpp, scl_data); 538 539 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); 540 541 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) 542 return; 543 544 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); 545 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); 546 547 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) 548 return; 549 550 /* TODO: v_min */ 551 REG_SET_3(DSCL_AUTOCAL, 0, 552 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, 553 AUTOCAL_NUM_PIPE, 0, 554 AUTOCAL_PIPE_ID, 0); 555 556 /* Black offsets */ 557 if (ycbcr) 558 REG_SET_2(SCL_BLACK_OFFSET, 0, 559 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 560 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); 561 else 562 563 REG_SET_2(SCL_BLACK_OFFSET, 0, 564 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 565 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); 566 567 REG_SET_4(SCL_TAP_CONTROL, 0, 568 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, 569 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, 570 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, 571 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); 572 573 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); 574 } 575 576 577 static void dpp1_dscl_set_manual_ratio_init( 578 struct dcn10_dpp *dpp, const struct scaler_data *data) 579 { 580 uint32_t init_frac = 0; 581 uint32_t init_int = 0; 582 583 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 584 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5); 585 586 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 587 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); 588 589 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, 590 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5); 591 592 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, 593 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5); 594 595 /* 596 * 0.24 format for fraction, first five bits zeroed 597 */ 598 init_frac = dc_fixpt_u0d19(data->inits.h) << 5; 599 init_int = dc_fixpt_floor(data->inits.h); 600 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, 601 SCL_H_INIT_FRAC, init_frac, 602 SCL_H_INIT_INT, init_int); 603 604 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5; 605 init_int = dc_fixpt_floor(data->inits.h_c); 606 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, 607 SCL_H_INIT_FRAC_C, init_frac, 608 SCL_H_INIT_INT_C, init_int); 609 610 init_frac = dc_fixpt_u0d19(data->inits.v) << 5; 611 init_int = dc_fixpt_floor(data->inits.v); 612 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 613 SCL_V_INIT_FRAC, init_frac, 614 SCL_V_INIT_INT, init_int); 615 616 if (REG(SCL_VERT_FILTER_INIT_BOT)) { 617 init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5; 618 init_int = dc_fixpt_floor(data->inits.v_bot); 619 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, 620 SCL_V_INIT_FRAC_BOT, init_frac, 621 SCL_V_INIT_INT_BOT, init_int); 622 } 623 624 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5; 625 init_int = dc_fixpt_floor(data->inits.v_c); 626 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, 627 SCL_V_INIT_FRAC_C, init_frac, 628 SCL_V_INIT_INT_C, init_int); 629 630 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { 631 init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5; 632 init_int = dc_fixpt_floor(data->inits.v_c_bot); 633 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, 634 SCL_V_INIT_FRAC_BOT_C, init_frac, 635 SCL_V_INIT_INT_BOT_C, init_int); 636 } 637 } 638 639 640 641 static void dpp1_dscl_set_recout( 642 struct dcn10_dpp *dpp, const struct rect *recout) 643 { 644 int visual_confirm_on = 0; 645 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) 646 visual_confirm_on = 1; 647 648 REG_SET_2(RECOUT_START, 0, 649 /* First pixel of RECOUT */ 650 RECOUT_START_X, recout->x, 651 /* First line of RECOUT */ 652 RECOUT_START_Y, recout->y); 653 654 REG_SET_2(RECOUT_SIZE, 0, 655 /* Number of RECOUT horizontal pixels */ 656 RECOUT_WIDTH, recout->width, 657 /* Number of RECOUT vertical lines */ 658 RECOUT_HEIGHT, recout->height 659 - visual_confirm_on * 4 * (dpp->base.inst + 1)); 660 } 661 662 /* Main function to program scaler and line buffer in manual scaling mode */ 663 void dpp1_dscl_set_scaler_manual_scale( 664 struct dpp *dpp_base, 665 const struct scaler_data *scl_data) 666 { 667 enum lb_memory_config lb_config; 668 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 669 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode( 670 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); 671 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN 672 && scl_data->format <= PIXEL_FORMAT_VIDEO_END; 673 674 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) 675 return; 676 677 PERF_TRACE(); 678 679 dpp->scl_data = *scl_data; 680 681 /* Autocal off */ 682 REG_SET_3(DSCL_AUTOCAL, 0, 683 AUTOCAL_MODE, AUTOCAL_MODE_OFF, 684 AUTOCAL_NUM_PIPE, 0, 685 AUTOCAL_PIPE_ID, 0); 686 687 /* Recout */ 688 dpp1_dscl_set_recout(dpp, &scl_data->recout); 689 690 /* MPC Size */ 691 REG_SET_2(MPC_SIZE, 0, 692 /* Number of horizontal pixels of MPC */ 693 MPC_WIDTH, scl_data->h_active, 694 /* Number of vertical lines of MPC */ 695 MPC_HEIGHT, scl_data->v_active); 696 697 /* SCL mode */ 698 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); 699 700 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) 701 return; 702 703 /* LB */ 704 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); 705 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); 706 707 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) 708 return; 709 710 /* Black offsets */ 711 if (REG(SCL_BLACK_OFFSET)) { 712 if (ycbcr) 713 REG_SET_2(SCL_BLACK_OFFSET, 0, 714 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 715 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); 716 else 717 718 REG_SET_2(SCL_BLACK_OFFSET, 0, 719 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 720 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); 721 } 722 723 /* Manually calculate scale ratio and init values */ 724 dpp1_dscl_set_manual_ratio_init(dpp, scl_data); 725 726 /* HTaps/VTaps */ 727 REG_SET_4(SCL_TAP_CONTROL, 0, 728 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, 729 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, 730 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, 731 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); 732 733 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); 734 PERF_TRACE(); 735 } 736