1 /* Copyright 2016 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DAL_DPP_DCN10_H__ 26 #define __DAL_DPP_DCN10_H__ 27 28 #include "transform.h" 29 30 #define TO_DCN10_DPP(transform)\ 31 container_of(transform, struct dcn10_dpp, base) 32 33 /* TODO: Use correct number of taps. Using polaris values for now */ 34 #define LB_TOTAL_NUMBER_OF_ENTRIES 5124 35 #define LB_BITS_PER_ENTRY 144 36 37 #define TF_SF(reg_name, field_name, post_fix)\ 38 .field_name = reg_name ## __ ## field_name ## post_fix 39 40 //Used to resolve corner case 41 #define TF2_SF(reg_name, field_name, post_fix)\ 42 .field_name = reg_name ## _ ## field_name ## post_fix 43 44 #define TF_REG_LIST_DCN(id) \ 45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ 46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ 47 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ 48 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ 49 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ 50 SRI(OTG_H_BLANK, DSCL, id), \ 51 SRI(OTG_V_BLANK, DSCL, id), \ 52 SRI(SCL_MODE, DSCL, id), \ 53 SRI(LB_DATA_FORMAT, DSCL, id), \ 54 SRI(LB_MEMORY_CTRL, DSCL, id), \ 55 SRI(DSCL_AUTOCAL, DSCL, id), \ 56 SRI(SCL_BLACK_OFFSET, DSCL, id), \ 57 SRI(DSCL_CONTROL, DSCL, id), \ 58 SRI(SCL_TAP_CONTROL, DSCL, id), \ 59 SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ 60 SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ 61 SRI(DSCL_2TAP_CONTROL, DSCL, id), \ 62 SRI(MPC_SIZE, DSCL, id), \ 63 SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ 64 SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ 65 SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ 66 SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ 67 SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \ 68 SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ 69 SRI(SCL_VERT_FILTER_INIT, DSCL, id), \ 70 SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \ 71 SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \ 72 SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ 73 SRI(RECOUT_START, DSCL, id), \ 74 SRI(RECOUT_SIZE, DSCL, id), \ 75 SRI(OBUF_CONTROL, DSCL, id), \ 76 SRI(CM_ICSC_CONTROL, CM, id), \ 77 SRI(CM_ICSC_C11_C12, CM, id), \ 78 SRI(CM_ICSC_C33_C34, CM, id), \ 79 SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ 80 SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ 81 SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ 82 SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 83 SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 84 SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 85 SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ 86 SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ 87 SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ 88 SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ 89 SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ 90 SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ 91 SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ 92 SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ 93 SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ 94 SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ 95 SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ 96 SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ 97 SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ 98 SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ 99 SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ 100 SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ 101 SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ 102 SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ 103 SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ 104 SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ 105 SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ 106 SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ 107 SRI(CM_MEM_PWR_CTRL, CM, id), \ 108 SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ 109 SRI(CM_DGAM_LUT_INDEX, CM, id), \ 110 SRI(CM_DGAM_LUT_DATA, CM, id), \ 111 SRI(CM_CONTROL, CM, id), \ 112 SRI(CM_DGAM_CONTROL, CM, id), \ 113 SRI(FORMAT_CONTROL, CNVC_CFG, id), \ 114 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 115 SRI(CURSOR0_CONTROL, CNVC_CUR, id) 116 117 118 119 #define TF_REG_LIST_DCN10(id) \ 120 TF_REG_LIST_DCN(id), \ 121 SRI(CM_COMA_C11_C12, CM, id),\ 122 SRI(CM_COMA_C33_C34, CM, id),\ 123 SRI(CM_COMB_C11_C12, CM, id),\ 124 SRI(CM_COMB_C33_C34, CM, id),\ 125 SRI(CM_OCSC_CONTROL, CM, id), \ 126 SRI(CM_OCSC_C11_C12, CM, id), \ 127 SRI(CM_OCSC_C33_C34, CM, id), \ 128 SRI(CM_MEM_PWR_CTRL, CM, id), \ 129 SRI(CM_RGAM_LUT_DATA, CM, id), \ 130 SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ 131 SRI(CM_RGAM_LUT_INDEX, CM, id), \ 132 SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ 133 SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ 134 SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ 135 SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 136 SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 137 SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 138 SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ 139 SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ 140 SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ 141 SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ 142 SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ 143 SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ 144 SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ 145 SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ 146 SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ 147 SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ 148 SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ 149 SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ 150 SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ 151 SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ 152 SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ 153 SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ 154 SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ 155 SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ 156 SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ 157 SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ 158 SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ 159 SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ 160 SRI(CM_RGAM_CONTROL, CM, id), \ 161 SRI(CM_IGAM_CONTROL, CM, id), \ 162 SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ 163 SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ 164 SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ 165 SRI(CURSOR_CONTROL, CURSOR, id) 166 167 168 #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ 169 TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ 170 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\ 171 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\ 172 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\ 173 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\ 174 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ 175 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ 176 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ 177 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ 178 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ 179 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ 180 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ 181 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ 182 TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ 183 TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ 184 TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ 185 TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ 186 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ 187 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ 188 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ 189 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ 190 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ 191 TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\ 192 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ 193 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ 194 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ 195 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ 196 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ 197 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ 198 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ 199 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ 200 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ 201 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ 202 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ 203 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ 204 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ 205 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ 206 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ 207 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ 208 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ 209 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ 210 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ 211 TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ 212 TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ 213 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ 214 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ 215 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ 216 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ 217 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ 218 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ 219 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ 220 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ 221 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ 222 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ 223 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ 224 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ 225 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ 226 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ 227 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ 228 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ 229 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ 230 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ 231 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ 232 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ 233 TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ 234 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ 235 TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ 236 TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ 237 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ 238 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ 239 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ 240 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ 241 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ 242 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ 243 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ 244 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ 245 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ 246 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ 247 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 248 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 249 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 250 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ 251 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ 252 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ 253 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ 254 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ 255 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ 256 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ 257 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ 258 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ 259 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ 260 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 261 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ 262 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 263 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ 264 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 265 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ 266 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 267 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ 268 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ 269 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ 270 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ 271 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ 272 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ 273 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 274 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 275 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 276 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ 277 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ 278 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ 279 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ 280 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ 281 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ 282 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ 283 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ 284 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ 285 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ 286 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 287 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ 288 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 289 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ 290 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 291 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ 292 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 293 TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ 294 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ 295 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ 296 TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ 297 TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ 298 TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ 299 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ 300 TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ 301 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ 302 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ 303 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ 304 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ 305 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh) 306 307 #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ 308 TF_REG_LIST_SH_MASK_DCN(mask_sh),\ 309 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\ 310 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\ 311 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\ 312 TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\ 313 TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\ 314 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\ 315 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\ 316 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\ 317 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\ 318 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\ 319 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\ 320 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\ 321 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\ 322 TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ 323 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ 324 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ 325 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ 326 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ 327 TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ 328 TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ 329 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ 330 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ 331 TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ 332 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ 333 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ 334 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ 335 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ 336 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ 337 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ 338 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 339 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 340 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 341 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ 342 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ 343 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ 344 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ 345 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ 346 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ 347 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ 348 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ 349 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ 350 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ 351 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 352 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ 353 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 354 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ 355 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ 356 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ 357 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ 358 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ 359 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ 360 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ 361 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ 362 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ 363 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ 364 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 365 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 366 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 367 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ 368 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ 369 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ 370 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ 371 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ 372 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ 373 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ 374 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ 375 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ 376 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ 377 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 378 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ 379 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 380 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ 381 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ 382 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ 383 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ 384 TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ 385 TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ 386 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ 387 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ 388 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ 389 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ 390 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ 391 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ 392 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ 393 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ 394 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ 395 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ 396 TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ 397 TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ 398 TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ 399 TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ 400 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 401 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 402 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 403 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh) 404 405 #define TF_REG_FIELD_LIST(type) \ 406 type EXT_OVERSCAN_LEFT; \ 407 type EXT_OVERSCAN_RIGHT; \ 408 type EXT_OVERSCAN_BOTTOM; \ 409 type EXT_OVERSCAN_TOP; \ 410 type OTG_H_BLANK_START; \ 411 type OTG_H_BLANK_END; \ 412 type OTG_V_BLANK_START; \ 413 type OTG_V_BLANK_END; \ 414 type PIXEL_DEPTH; \ 415 type PIXEL_EXPAN_MODE; \ 416 type PIXEL_REDUCE_MODE; \ 417 type DYNAMIC_PIXEL_DEPTH; \ 418 type DITHER_EN; \ 419 type INTERLEAVE_EN; \ 420 type LB_DATA_FORMAT__ALPHA_EN; \ 421 type MEMORY_CONFIG; \ 422 type LB_MAX_PARTITIONS; \ 423 type AUTOCAL_MODE; \ 424 type AUTOCAL_NUM_PIPE; \ 425 type AUTOCAL_PIPE_ID; \ 426 type SCL_BLACK_OFFSET_RGB_Y; \ 427 type SCL_BLACK_OFFSET_CBCR; \ 428 type SCL_BOUNDARY_MODE; \ 429 type SCL_V_NUM_TAPS; \ 430 type SCL_H_NUM_TAPS; \ 431 type SCL_V_NUM_TAPS_C; \ 432 type SCL_H_NUM_TAPS_C; \ 433 type SCL_COEF_RAM_TAP_PAIR_IDX; \ 434 type SCL_COEF_RAM_PHASE; \ 435 type SCL_COEF_RAM_FILTER_TYPE; \ 436 type SCL_COEF_RAM_EVEN_TAP_COEF; \ 437 type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \ 438 type SCL_COEF_RAM_ODD_TAP_COEF; \ 439 type SCL_COEF_RAM_ODD_TAP_COEF_EN; \ 440 type SCL_H_2TAP_HARDCODE_COEF_EN; \ 441 type SCL_H_2TAP_SHARP_EN; \ 442 type SCL_H_2TAP_SHARP_FACTOR; \ 443 type SCL_V_2TAP_HARDCODE_COEF_EN; \ 444 type SCL_V_2TAP_SHARP_EN; \ 445 type SCL_V_2TAP_SHARP_FACTOR; \ 446 type SCL_COEF_RAM_SELECT; \ 447 type DSCL_MODE; \ 448 type RECOUT_START_X; \ 449 type RECOUT_START_Y; \ 450 type RECOUT_WIDTH; \ 451 type RECOUT_HEIGHT; \ 452 type MPC_WIDTH; \ 453 type MPC_HEIGHT; \ 454 type SCL_H_SCALE_RATIO; \ 455 type SCL_V_SCALE_RATIO; \ 456 type SCL_H_SCALE_RATIO_C; \ 457 type SCL_V_SCALE_RATIO_C; \ 458 type SCL_H_INIT_FRAC; \ 459 type SCL_H_INIT_INT; \ 460 type SCL_H_INIT_FRAC_C; \ 461 type SCL_H_INIT_INT_C; \ 462 type SCL_V_INIT_FRAC; \ 463 type SCL_V_INIT_INT; \ 464 type SCL_V_INIT_FRAC_BOT; \ 465 type SCL_V_INIT_INT_BOT; \ 466 type SCL_V_INIT_FRAC_C; \ 467 type SCL_V_INIT_INT_C; \ 468 type SCL_V_INIT_FRAC_BOT_C; \ 469 type SCL_V_INIT_INT_BOT_C; \ 470 type SCL_CHROMA_COEF_MODE; \ 471 type SCL_COEF_RAM_SELECT_CURRENT; \ 472 type CM_GAMUT_REMAP_MODE; \ 473 type CM_GAMUT_REMAP_C11; \ 474 type CM_GAMUT_REMAP_C12; \ 475 type CM_GAMUT_REMAP_C33; \ 476 type CM_GAMUT_REMAP_C34; \ 477 type CM_COMA_C11; \ 478 type CM_COMA_C12; \ 479 type CM_COMA_C33; \ 480 type CM_COMA_C34; \ 481 type CM_COMB_C11; \ 482 type CM_COMB_C12; \ 483 type CM_COMB_C33; \ 484 type CM_COMB_C34; \ 485 type CM_OCSC_MODE; \ 486 type CM_OCSC_C11; \ 487 type CM_OCSC_C12; \ 488 type CM_OCSC_C33; \ 489 type CM_OCSC_C34; \ 490 type RGAM_MEM_PWR_FORCE; \ 491 type CM_RGAM_LUT_DATA; \ 492 type CM_RGAM_LUT_WRITE_EN_MASK; \ 493 type CM_RGAM_LUT_WRITE_SEL; \ 494 type CM_RGAM_LUT_INDEX; \ 495 type CM_RGAM_RAMB_EXP_REGION_START_B; \ 496 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 497 type CM_RGAM_RAMB_EXP_REGION_START_G; \ 498 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 499 type CM_RGAM_RAMB_EXP_REGION_START_R; \ 500 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 501 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 502 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 503 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 504 type CM_RGAM_RAMB_EXP_REGION_END_B; \ 505 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 506 type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \ 507 type CM_RGAM_RAMB_EXP_REGION_END_G; \ 508 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 509 type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \ 510 type CM_RGAM_RAMB_EXP_REGION_END_R; \ 511 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 512 type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \ 513 type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 514 type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 515 type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 516 type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 517 type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ 518 type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 519 type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ 520 type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 521 type CM_RGAM_RAMA_EXP_REGION_START_B; \ 522 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 523 type CM_RGAM_RAMA_EXP_REGION_START_G; \ 524 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 525 type CM_RGAM_RAMA_EXP_REGION_START_R; \ 526 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 527 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 528 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 529 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 530 type CM_RGAM_RAMA_EXP_REGION_END_B; \ 531 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 532 type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \ 533 type CM_RGAM_RAMA_EXP_REGION_END_G; \ 534 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 535 type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \ 536 type CM_RGAM_RAMA_EXP_REGION_END_R; \ 537 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 538 type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \ 539 type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 540 type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 541 type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 542 type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 543 type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ 544 type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 545 type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ 546 type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 547 type CM_RGAM_LUT_MODE; \ 548 type OBUF_BYPASS; \ 549 type OBUF_H_2X_UPSCALE_EN; \ 550 type CM_BLNDGAM_LUT_MODE; \ 551 type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \ 552 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 553 type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \ 554 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 555 type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \ 556 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 557 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 558 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 559 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 560 type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \ 561 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 562 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \ 563 type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \ 564 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 565 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \ 566 type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \ 567 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 568 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \ 569 type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 570 type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 571 type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 572 type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 573 type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ 574 type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ 575 type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ 576 type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ 577 type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ 578 type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ 579 type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ 580 type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ 581 type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ 582 type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ 583 type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ 584 type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ 585 type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ 586 type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ 587 type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ 588 type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ 589 type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ 590 type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ 591 type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ 592 type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ 593 type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ 594 type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ 595 type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ 596 type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ 597 type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ 598 type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 599 type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ 600 type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 601 type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \ 602 type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \ 603 type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \ 604 type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \ 605 type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \ 606 type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \ 607 type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \ 608 type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \ 609 type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \ 610 type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \ 611 type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \ 612 type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \ 613 type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \ 614 type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \ 615 type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \ 616 type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \ 617 type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \ 618 type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \ 619 type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \ 620 type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \ 621 type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \ 622 type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \ 623 type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \ 624 type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \ 625 type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \ 626 type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \ 627 type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \ 628 type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \ 629 type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \ 630 type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \ 631 type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \ 632 type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \ 633 type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ 634 type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 635 type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ 636 type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 637 type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \ 638 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 639 type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \ 640 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 641 type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \ 642 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 643 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 644 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 645 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 646 type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \ 647 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 648 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \ 649 type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \ 650 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 651 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \ 652 type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \ 653 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 654 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \ 655 type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 656 type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 657 type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 658 type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 659 type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ 660 type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 661 type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ 662 type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 663 type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ 664 type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 665 type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ 666 type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 667 type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ 668 type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 669 type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ 670 type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 671 type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ 672 type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 673 type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ 674 type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 675 type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ 676 type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 677 type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ 678 type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 679 type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ 680 type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 681 type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ 682 type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 683 type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 684 type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 685 type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 686 type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 687 type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ 688 type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 689 type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ 690 type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 691 type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ 692 type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 693 type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ 694 type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 695 type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ 696 type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 697 type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ 698 type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 699 type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ 700 type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 701 type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ 702 type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 703 type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ 704 type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 705 type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ 706 type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 707 type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ 708 type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 709 type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ 710 type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 711 type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ 712 type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 713 type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ 714 type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 715 type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ 716 type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 717 type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ 718 type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 719 type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ 720 type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 721 type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ 722 type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 723 type CM_BLNDGAM_LUT_WRITE_EN_MASK; \ 724 type CM_BLNDGAM_LUT_WRITE_SEL; \ 725 type CM_BLNDGAM_LUT_INDEX; \ 726 type CM_BLNDGAM_LUT_DATA; \ 727 type CM_3DLUT_MODE; \ 728 type CM_3DLUT_SIZE; \ 729 type CM_3DLUT_INDEX; \ 730 type CM_3DLUT_DATA0; \ 731 type CM_3DLUT_DATA1; \ 732 type CM_3DLUT_DATA_30BIT; \ 733 type CM_3DLUT_WRITE_EN_MASK; \ 734 type CM_3DLUT_RAM_SEL; \ 735 type CM_3DLUT_30BIT_EN; \ 736 type CM_3DLUT_CONFIG_STATUS; \ 737 type CM_3DLUT_READ_SEL; \ 738 type CM_SHAPER_LUT_MODE; \ 739 type CM_SHAPER_RAMB_EXP_REGION_START_B; \ 740 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \ 741 type CM_SHAPER_RAMB_EXP_REGION_START_G; \ 742 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \ 743 type CM_SHAPER_RAMB_EXP_REGION_START_R; \ 744 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \ 745 type CM_SHAPER_RAMB_EXP_REGION_END_B; \ 746 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \ 747 type CM_SHAPER_RAMB_EXP_REGION_END_G; \ 748 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \ 749 type CM_SHAPER_RAMB_EXP_REGION_END_R; \ 750 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \ 751 type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \ 752 type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 753 type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \ 754 type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 755 type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \ 756 type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \ 757 type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \ 758 type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \ 759 type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \ 760 type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \ 761 type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \ 762 type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \ 763 type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \ 764 type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \ 765 type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \ 766 type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \ 767 type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \ 768 type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \ 769 type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \ 770 type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \ 771 type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \ 772 type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \ 773 type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \ 774 type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \ 775 type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \ 776 type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \ 777 type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \ 778 type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \ 779 type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \ 780 type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 781 type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \ 782 type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 783 type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \ 784 type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \ 785 type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \ 786 type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \ 787 type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \ 788 type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \ 789 type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \ 790 type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \ 791 type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \ 792 type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \ 793 type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \ 794 type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \ 795 type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \ 796 type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \ 797 type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \ 798 type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \ 799 type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \ 800 type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \ 801 type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \ 802 type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \ 803 type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \ 804 type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \ 805 type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \ 806 type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \ 807 type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \ 808 type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \ 809 type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \ 810 type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \ 811 type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \ 812 type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \ 813 type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \ 814 type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \ 815 type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \ 816 type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 817 type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \ 818 type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 819 type CM_SHAPER_RAMA_EXP_REGION_START_B; \ 820 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ 821 type CM_SHAPER_RAMA_EXP_REGION_START_G; \ 822 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \ 823 type CM_SHAPER_RAMA_EXP_REGION_START_R; \ 824 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \ 825 type CM_SHAPER_RAMA_EXP_REGION_END_B; \ 826 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \ 827 type CM_SHAPER_RAMA_EXP_REGION_END_G; \ 828 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \ 829 type CM_SHAPER_RAMA_EXP_REGION_END_R; \ 830 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \ 831 type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \ 832 type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 833 type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ 834 type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 835 type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ 836 type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 837 type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \ 838 type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 839 type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \ 840 type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 841 type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \ 842 type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 843 type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ 844 type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 845 type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ 846 type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 847 type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \ 848 type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 849 type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \ 850 type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 851 type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \ 852 type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 853 type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ 854 type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 855 type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ 856 type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 857 type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \ 858 type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 859 type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \ 860 type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 861 type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \ 862 type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 863 type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ 864 type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 865 type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ 866 type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 867 type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \ 868 type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 869 type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \ 870 type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 871 type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \ 872 type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 873 type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ 874 type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 875 type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ 876 type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 877 type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \ 878 type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 879 type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \ 880 type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 881 type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \ 882 type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 883 type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ 884 type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 885 type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ 886 type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 887 type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \ 888 type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 889 type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \ 890 type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 891 type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \ 892 type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 893 type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ 894 type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 895 type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ 896 type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 897 type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \ 898 type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 899 type CM_SHAPER_LUT_WRITE_EN_MASK; \ 900 type CM_SHAPER_LUT_WRITE_SEL; \ 901 type CM_SHAPER_LUT_INDEX; \ 902 type CM_SHAPER_LUT_DATA; \ 903 type CM_DGAM_CONFIG_STATUS; \ 904 type CM_ICSC_MODE; \ 905 type CM_ICSC_C11; \ 906 type CM_ICSC_C12; \ 907 type CM_ICSC_C33; \ 908 type CM_ICSC_C34; \ 909 type CM_DGAM_RAMB_EXP_REGION_START_B; \ 910 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 911 type CM_DGAM_RAMB_EXP_REGION_START_G; \ 912 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 913 type CM_DGAM_RAMB_EXP_REGION_START_R; \ 914 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 915 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 916 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 917 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 918 type CM_DGAM_RAMB_EXP_REGION_END_B; \ 919 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 920 type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \ 921 type CM_DGAM_RAMB_EXP_REGION_END_G; \ 922 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 923 type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \ 924 type CM_DGAM_RAMB_EXP_REGION_END_R; \ 925 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 926 type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \ 927 type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 928 type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 929 type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 930 type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 931 type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ 932 type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 933 type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ 934 type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 935 type CM_DGAM_RAMA_EXP_REGION_START_B; \ 936 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 937 type CM_DGAM_RAMA_EXP_REGION_START_G; \ 938 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 939 type CM_DGAM_RAMA_EXP_REGION_START_R; \ 940 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 941 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 942 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 943 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 944 type CM_DGAM_RAMA_EXP_REGION_END_B; \ 945 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 946 type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \ 947 type CM_DGAM_RAMA_EXP_REGION_END_G; \ 948 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 949 type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \ 950 type CM_DGAM_RAMA_EXP_REGION_END_R; \ 951 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 952 type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \ 953 type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 954 type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 955 type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 956 type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 957 type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 958 type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 959 type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 960 type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 961 type SHARED_MEM_PWR_DIS; \ 962 type CM_IGAM_LUT_FORMAT_R; \ 963 type CM_IGAM_LUT_FORMAT_G; \ 964 type CM_IGAM_LUT_FORMAT_B; \ 965 type CM_IGAM_LUT_HOST_EN; \ 966 type CM_IGAM_LUT_RW_MODE; \ 967 type CM_IGAM_LUT_WRITE_EN_MASK; \ 968 type CM_IGAM_LUT_SEL; \ 969 type CM_IGAM_LUT_SEQ_COLOR; \ 970 type CM_IGAM_DGAM_CONFIG_STATUS; \ 971 type CM_DGAM_LUT_WRITE_EN_MASK; \ 972 type CM_DGAM_LUT_WRITE_SEL; \ 973 type CM_DGAM_LUT_INDEX; \ 974 type CM_DGAM_LUT_DATA; \ 975 type CM_DGAM_LUT_MODE; \ 976 type CM_IGAM_LUT_MODE; \ 977 type CM_IGAM_INPUT_FORMAT; \ 978 type CM_IGAM_LUT_RW_INDEX; \ 979 type CM_BYPASS_EN; \ 980 type FORMAT_EXPANSION_MODE; \ 981 type CNVC_BYPASS; \ 982 type OUTPUT_FP; \ 983 type CNVC_SURFACE_PIXEL_FORMAT; \ 984 type CURSOR_MODE; \ 985 type CURSOR_PITCH; \ 986 type CURSOR_LINES_PER_CHUNK; \ 987 type CURSOR_ENABLE; \ 988 type CUR0_MODE; \ 989 type CUR0_EXPANSION_MODE; \ 990 type CUR0_ENABLE; \ 991 type CM_BYPASS; \ 992 type FORMAT_CONTROL__ALPHA_EN 993 994 995 996 struct dcn_dpp_shift { 997 TF_REG_FIELD_LIST(uint8_t); 998 }; 999 1000 struct dcn_dpp_mask { 1001 TF_REG_FIELD_LIST(uint32_t); 1002 }; 1003 1004 1005 1006 1007 struct dcn_dpp_registers { 1008 uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; 1009 uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; 1010 uint32_t OTG_H_BLANK; 1011 uint32_t OTG_V_BLANK; 1012 uint32_t SCL_MODE; 1013 uint32_t LB_DATA_FORMAT; 1014 uint32_t LB_MEMORY_CTRL; 1015 uint32_t DSCL_AUTOCAL; 1016 uint32_t SCL_BLACK_OFFSET; 1017 uint32_t DSCL_CONTROL; 1018 uint32_t SCL_TAP_CONTROL; 1019 uint32_t SCL_COEF_RAM_TAP_SELECT; 1020 uint32_t SCL_COEF_RAM_TAP_DATA; 1021 uint32_t DSCL_2TAP_CONTROL; 1022 uint32_t MPC_SIZE; 1023 uint32_t SCL_HORZ_FILTER_SCALE_RATIO; 1024 uint32_t SCL_VERT_FILTER_SCALE_RATIO; 1025 uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; 1026 uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; 1027 uint32_t SCL_HORZ_FILTER_INIT; 1028 uint32_t SCL_HORZ_FILTER_INIT_C; 1029 uint32_t SCL_VERT_FILTER_INIT; 1030 uint32_t SCL_VERT_FILTER_INIT_BOT; 1031 uint32_t SCL_VERT_FILTER_INIT_C; 1032 uint32_t SCL_VERT_FILTER_INIT_BOT_C; 1033 uint32_t RECOUT_START; 1034 uint32_t RECOUT_SIZE; 1035 uint32_t CM_GAMUT_REMAP_CONTROL; 1036 uint32_t CM_GAMUT_REMAP_C11_C12; 1037 uint32_t CM_GAMUT_REMAP_C33_C34; 1038 uint32_t CM_COMA_C11_C12; 1039 uint32_t CM_COMA_C33_C34; 1040 uint32_t CM_COMB_C11_C12; 1041 uint32_t CM_COMB_C33_C34; 1042 uint32_t CM_OCSC_CONTROL; 1043 uint32_t CM_OCSC_C11_C12; 1044 uint32_t CM_OCSC_C33_C34; 1045 uint32_t CM_MEM_PWR_CTRL; 1046 uint32_t CM_RGAM_LUT_DATA; 1047 uint32_t CM_RGAM_LUT_WRITE_EN_MASK; 1048 uint32_t CM_RGAM_LUT_INDEX; 1049 uint32_t CM_RGAM_RAMB_START_CNTL_B; 1050 uint32_t CM_RGAM_RAMB_START_CNTL_G; 1051 uint32_t CM_RGAM_RAMB_START_CNTL_R; 1052 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; 1053 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; 1054 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; 1055 uint32_t CM_RGAM_RAMB_END_CNTL1_B; 1056 uint32_t CM_RGAM_RAMB_END_CNTL2_B; 1057 uint32_t CM_RGAM_RAMB_END_CNTL1_G; 1058 uint32_t CM_RGAM_RAMB_END_CNTL2_G; 1059 uint32_t CM_RGAM_RAMB_END_CNTL1_R; 1060 uint32_t CM_RGAM_RAMB_END_CNTL2_R; 1061 uint32_t CM_RGAM_RAMB_REGION_0_1; 1062 uint32_t CM_RGAM_RAMB_REGION_32_33; 1063 uint32_t CM_RGAM_RAMA_START_CNTL_B; 1064 uint32_t CM_RGAM_RAMA_START_CNTL_G; 1065 uint32_t CM_RGAM_RAMA_START_CNTL_R; 1066 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; 1067 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; 1068 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; 1069 uint32_t CM_RGAM_RAMA_END_CNTL1_B; 1070 uint32_t CM_RGAM_RAMA_END_CNTL2_B; 1071 uint32_t CM_RGAM_RAMA_END_CNTL1_G; 1072 uint32_t CM_RGAM_RAMA_END_CNTL2_G; 1073 uint32_t CM_RGAM_RAMA_END_CNTL1_R; 1074 uint32_t CM_RGAM_RAMA_END_CNTL2_R; 1075 uint32_t CM_RGAM_RAMA_REGION_0_1; 1076 uint32_t CM_RGAM_RAMA_REGION_32_33; 1077 uint32_t CM_RGAM_CONTROL; 1078 uint32_t OBUF_CONTROL; 1079 uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; 1080 uint32_t CM_BLNDGAM_CONTROL; 1081 uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; 1082 uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; 1083 uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; 1084 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; 1085 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; 1086 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; 1087 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; 1088 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; 1089 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; 1090 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; 1091 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; 1092 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; 1093 uint32_t CM_BLNDGAM_RAMB_REGION_0_1; 1094 uint32_t CM_BLNDGAM_RAMB_REGION_2_3; 1095 uint32_t CM_BLNDGAM_RAMB_REGION_4_5; 1096 uint32_t CM_BLNDGAM_RAMB_REGION_6_7; 1097 uint32_t CM_BLNDGAM_RAMB_REGION_8_9; 1098 uint32_t CM_BLNDGAM_RAMB_REGION_10_11; 1099 uint32_t CM_BLNDGAM_RAMB_REGION_12_13; 1100 uint32_t CM_BLNDGAM_RAMB_REGION_14_15; 1101 uint32_t CM_BLNDGAM_RAMB_REGION_16_17; 1102 uint32_t CM_BLNDGAM_RAMB_REGION_18_19; 1103 uint32_t CM_BLNDGAM_RAMB_REGION_20_21; 1104 uint32_t CM_BLNDGAM_RAMB_REGION_22_23; 1105 uint32_t CM_BLNDGAM_RAMB_REGION_24_25; 1106 uint32_t CM_BLNDGAM_RAMB_REGION_26_27; 1107 uint32_t CM_BLNDGAM_RAMB_REGION_28_29; 1108 uint32_t CM_BLNDGAM_RAMB_REGION_30_31; 1109 uint32_t CM_BLNDGAM_RAMB_REGION_32_33; 1110 uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; 1111 uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; 1112 uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; 1113 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; 1114 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; 1115 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; 1116 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; 1117 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; 1118 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; 1119 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; 1120 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; 1121 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; 1122 uint32_t CM_BLNDGAM_RAMA_REGION_0_1; 1123 uint32_t CM_BLNDGAM_RAMA_REGION_2_3; 1124 uint32_t CM_BLNDGAM_RAMA_REGION_4_5; 1125 uint32_t CM_BLNDGAM_RAMA_REGION_6_7; 1126 uint32_t CM_BLNDGAM_RAMA_REGION_8_9; 1127 uint32_t CM_BLNDGAM_RAMA_REGION_10_11; 1128 uint32_t CM_BLNDGAM_RAMA_REGION_12_13; 1129 uint32_t CM_BLNDGAM_RAMA_REGION_14_15; 1130 uint32_t CM_BLNDGAM_RAMA_REGION_16_17; 1131 uint32_t CM_BLNDGAM_RAMA_REGION_18_19; 1132 uint32_t CM_BLNDGAM_RAMA_REGION_20_21; 1133 uint32_t CM_BLNDGAM_RAMA_REGION_22_23; 1134 uint32_t CM_BLNDGAM_RAMA_REGION_24_25; 1135 uint32_t CM_BLNDGAM_RAMA_REGION_26_27; 1136 uint32_t CM_BLNDGAM_RAMA_REGION_28_29; 1137 uint32_t CM_BLNDGAM_RAMA_REGION_30_31; 1138 uint32_t CM_BLNDGAM_RAMA_REGION_32_33; 1139 uint32_t CM_BLNDGAM_LUT_INDEX; 1140 uint32_t CM_BLNDGAM_LUT_DATA; 1141 uint32_t CM_3DLUT_MODE; 1142 uint32_t CM_3DLUT_INDEX; 1143 uint32_t CM_3DLUT_DATA; 1144 uint32_t CM_3DLUT_DATA_30BIT; 1145 uint32_t CM_3DLUT_READ_WRITE_CONTROL; 1146 uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; 1147 uint32_t CM_SHAPER_CONTROL; 1148 uint32_t CM_SHAPER_RAMB_START_CNTL_B; 1149 uint32_t CM_SHAPER_RAMB_START_CNTL_G; 1150 uint32_t CM_SHAPER_RAMB_START_CNTL_R; 1151 uint32_t CM_SHAPER_RAMB_END_CNTL_B; 1152 uint32_t CM_SHAPER_RAMB_END_CNTL_G; 1153 uint32_t CM_SHAPER_RAMB_END_CNTL_R; 1154 uint32_t CM_SHAPER_RAMB_REGION_0_1; 1155 uint32_t CM_SHAPER_RAMB_REGION_2_3; 1156 uint32_t CM_SHAPER_RAMB_REGION_4_5; 1157 uint32_t CM_SHAPER_RAMB_REGION_6_7; 1158 uint32_t CM_SHAPER_RAMB_REGION_8_9; 1159 uint32_t CM_SHAPER_RAMB_REGION_10_11; 1160 uint32_t CM_SHAPER_RAMB_REGION_12_13; 1161 uint32_t CM_SHAPER_RAMB_REGION_14_15; 1162 uint32_t CM_SHAPER_RAMB_REGION_16_17; 1163 uint32_t CM_SHAPER_RAMB_REGION_18_19; 1164 uint32_t CM_SHAPER_RAMB_REGION_20_21; 1165 uint32_t CM_SHAPER_RAMB_REGION_22_23; 1166 uint32_t CM_SHAPER_RAMB_REGION_24_25; 1167 uint32_t CM_SHAPER_RAMB_REGION_26_27; 1168 uint32_t CM_SHAPER_RAMB_REGION_28_29; 1169 uint32_t CM_SHAPER_RAMB_REGION_30_31; 1170 uint32_t CM_SHAPER_RAMB_REGION_32_33; 1171 uint32_t CM_SHAPER_RAMA_START_CNTL_B; 1172 uint32_t CM_SHAPER_RAMA_START_CNTL_G; 1173 uint32_t CM_SHAPER_RAMA_START_CNTL_R; 1174 uint32_t CM_SHAPER_RAMA_END_CNTL_B; 1175 uint32_t CM_SHAPER_RAMA_END_CNTL_G; 1176 uint32_t CM_SHAPER_RAMA_END_CNTL_R; 1177 uint32_t CM_SHAPER_RAMA_REGION_0_1; 1178 uint32_t CM_SHAPER_RAMA_REGION_2_3; 1179 uint32_t CM_SHAPER_RAMA_REGION_4_5; 1180 uint32_t CM_SHAPER_RAMA_REGION_6_7; 1181 uint32_t CM_SHAPER_RAMA_REGION_8_9; 1182 uint32_t CM_SHAPER_RAMA_REGION_10_11; 1183 uint32_t CM_SHAPER_RAMA_REGION_12_13; 1184 uint32_t CM_SHAPER_RAMA_REGION_14_15; 1185 uint32_t CM_SHAPER_RAMA_REGION_16_17; 1186 uint32_t CM_SHAPER_RAMA_REGION_18_19; 1187 uint32_t CM_SHAPER_RAMA_REGION_20_21; 1188 uint32_t CM_SHAPER_RAMA_REGION_22_23; 1189 uint32_t CM_SHAPER_RAMA_REGION_24_25; 1190 uint32_t CM_SHAPER_RAMA_REGION_26_27; 1191 uint32_t CM_SHAPER_RAMA_REGION_28_29; 1192 uint32_t CM_SHAPER_RAMA_REGION_30_31; 1193 uint32_t CM_SHAPER_RAMA_REGION_32_33; 1194 uint32_t CM_SHAPER_LUT_INDEX; 1195 uint32_t CM_SHAPER_LUT_DATA; 1196 uint32_t CM_ICSC_CONTROL; 1197 uint32_t CM_ICSC_C11_C12; 1198 uint32_t CM_ICSC_C33_C34; 1199 uint32_t CM_DGAM_RAMB_START_CNTL_B; 1200 uint32_t CM_DGAM_RAMB_START_CNTL_G; 1201 uint32_t CM_DGAM_RAMB_START_CNTL_R; 1202 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; 1203 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; 1204 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; 1205 uint32_t CM_DGAM_RAMB_END_CNTL1_B; 1206 uint32_t CM_DGAM_RAMB_END_CNTL2_B; 1207 uint32_t CM_DGAM_RAMB_END_CNTL1_G; 1208 uint32_t CM_DGAM_RAMB_END_CNTL2_G; 1209 uint32_t CM_DGAM_RAMB_END_CNTL1_R; 1210 uint32_t CM_DGAM_RAMB_END_CNTL2_R; 1211 uint32_t CM_DGAM_RAMB_REGION_0_1; 1212 uint32_t CM_DGAM_RAMB_REGION_14_15; 1213 uint32_t CM_DGAM_RAMA_START_CNTL_B; 1214 uint32_t CM_DGAM_RAMA_START_CNTL_G; 1215 uint32_t CM_DGAM_RAMA_START_CNTL_R; 1216 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; 1217 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; 1218 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; 1219 uint32_t CM_DGAM_RAMA_END_CNTL1_B; 1220 uint32_t CM_DGAM_RAMA_END_CNTL2_B; 1221 uint32_t CM_DGAM_RAMA_END_CNTL1_G; 1222 uint32_t CM_DGAM_RAMA_END_CNTL2_G; 1223 uint32_t CM_DGAM_RAMA_END_CNTL1_R; 1224 uint32_t CM_DGAM_RAMA_END_CNTL2_R; 1225 uint32_t CM_DGAM_RAMA_REGION_0_1; 1226 uint32_t CM_DGAM_RAMA_REGION_14_15; 1227 uint32_t CM_DGAM_LUT_WRITE_EN_MASK; 1228 uint32_t CM_DGAM_LUT_INDEX; 1229 uint32_t CM_DGAM_LUT_DATA; 1230 uint32_t CM_CONTROL; 1231 uint32_t CM_DGAM_CONTROL; 1232 uint32_t CM_IGAM_CONTROL; 1233 uint32_t CM_IGAM_LUT_RW_CONTROL; 1234 uint32_t CM_IGAM_LUT_RW_INDEX; 1235 uint32_t CM_IGAM_LUT_SEQ_COLOR; 1236 uint32_t FORMAT_CONTROL; 1237 uint32_t CNVC_SURFACE_PIXEL_FORMAT; 1238 uint32_t CURSOR_CONTROL; 1239 uint32_t CURSOR0_CONTROL; 1240 }; 1241 1242 struct dcn10_dpp { 1243 struct transform base; 1244 1245 const struct dcn_dpp_registers *tf_regs; 1246 const struct dcn_dpp_shift *tf_shift; 1247 const struct dcn_dpp_mask *tf_mask; 1248 1249 const uint16_t *filter_v; 1250 const uint16_t *filter_h; 1251 const uint16_t *filter_v_c; 1252 const uint16_t *filter_h_c; 1253 int lb_pixel_depth_supported; 1254 int lb_memory_size; 1255 int lb_bits_per_entry; 1256 bool is_write_to_ram_a_safe; 1257 }; 1258 1259 1260 1261 enum dcn10_input_csc_select { 1262 INPUT_CSC_SELECT_BYPASS = 0, 1263 INPUT_CSC_SELECT_ICSC, 1264 INPUT_CSC_SELECT_COMA 1265 }; 1266 1267 void ippn10_degamma_ram_select( 1268 struct transform *xfm_base, 1269 bool use_ram_a); 1270 1271 void ippn10_program_degamma_luta_settings( 1272 struct transform *xfm_base, 1273 const struct pwl_params *params); 1274 1275 void ippn10_program_degamma_lutb_settings( 1276 struct transform *xfm_base, 1277 const struct pwl_params *params); 1278 1279 void ippn10_program_degamma_lut( 1280 struct transform *xfm_base, 1281 const struct pwl_result_data *rgb, 1282 uint32_t num, 1283 bool is_ram_a); 1284 1285 void ippn10_power_on_degamma_lut( 1286 struct transform *xfm_base, 1287 bool power_on); 1288 1289 void ippn10_program_input_csc( 1290 struct transform *xfm_base, 1291 enum dc_color_space color_space, 1292 enum dcn10_input_csc_select select); 1293 1294 void ippn10_program_input_lut( 1295 struct transform *xfm_base, 1296 const struct dc_gamma *gamma); 1297 1298 void ippn10_full_bypass(struct transform *xfm_base); 1299 1300 void ippn10_set_degamma( 1301 struct transform *xfm_base, 1302 enum ipp_degamma_mode mode); 1303 1304 void ippn10_set_degamma_pwl(struct transform *xfm_base, 1305 const struct pwl_params *params); 1306 1307 bool dpp_get_optimal_number_of_taps( 1308 struct transform *xfm, 1309 struct scaler_data *scl_data, 1310 const struct scaling_taps *in_taps); 1311 1312 void dpp_reset(struct transform *xfm_base); 1313 1314 void dcn10_dpp_cm_program_regamma_lut( 1315 struct transform *xfm_base, 1316 const struct pwl_result_data *rgb, 1317 uint32_t num); 1318 1319 void dcn10_dpp_cm_power_on_regamma_lut( 1320 struct transform *xfm_base, 1321 bool power_on); 1322 1323 void dcn10_dpp_cm_configure_regamma_lut( 1324 struct transform *xfm_base, 1325 bool is_ram_a); 1326 1327 /*program re gamma RAM A*/ 1328 void dcn10_dpp_cm_program_regamma_luta_settings( 1329 struct transform *xfm_base, 1330 const struct pwl_params *params); 1331 1332 /*program re gamma RAM B*/ 1333 void dcn10_dpp_cm_program_regamma_lutb_settings( 1334 struct transform *xfm_base, 1335 const struct pwl_params *params); 1336 void dcn10_dpp_cm_set_output_csc_adjustment( 1337 struct transform *xfm_base, 1338 const struct out_csc_color_matrix *tbl_entry); 1339 1340 void dcn10_dpp_cm_set_output_csc_default( 1341 struct transform *xfm_base, 1342 const struct default_adjustment *default_adjust); 1343 1344 void dcn10_dpp_cm_set_gamut_remap( 1345 struct transform *xfm, 1346 const struct xfm_grph_csc_adjustment *adjust); 1347 1348 void dcn10_dpp_dscl_set_scaler_manual_scale( 1349 struct transform *xfm_base, 1350 const struct scaler_data *scl_data); 1351 1352 void ippn10_cnv_setup ( 1353 struct transform *xfm_base, 1354 enum surface_pixel_format input_format, 1355 enum expansion_mode mode); 1356 1357 void ippn10_full_bypass(struct transform *xfm_base); 1358 1359 bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, 1360 struct dc_context *ctx, 1361 uint32_t inst, 1362 const struct dcn_dpp_registers *tf_regs, 1363 const struct dcn_dpp_shift *tf_shift, 1364 const struct dcn_dpp_mask *tf_mask); 1365 #endif 1366