1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "core_types.h"
29 
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33 
34 #define NUM_PHASES    64
35 #define HORZ_MAX_TAPS 8
36 #define VERT_MAX_TAPS 8
37 
38 #define BLACK_OFFSET_RGB_Y 0x0
39 #define BLACK_OFFSET_CBCR  0x8000
40 
41 #define REG(reg)\
42 	dpp->tf_regs->reg
43 
44 #define CTX \
45 	dpp->base.ctx
46 
47 #undef FN
48 #define FN(reg_name, field_name) \
49 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 
51 enum pixel_format_description {
52 	PIXEL_FORMAT_FIXED = 0,
53 	PIXEL_FORMAT_FIXED16,
54 	PIXEL_FORMAT_FLOAT
55 
56 };
57 
58 enum dcn10_coef_filter_type_sel {
59 	SCL_COEF_LUMA_VERT_FILTER = 0,
60 	SCL_COEF_LUMA_HORZ_FILTER = 1,
61 	SCL_COEF_CHROMA_VERT_FILTER = 2,
62 	SCL_COEF_CHROMA_HORZ_FILTER = 3,
63 	SCL_COEF_ALPHA_VERT_FILTER = 4,
64 	SCL_COEF_ALPHA_HORZ_FILTER = 5
65 };
66 
67 enum dscl_autocal_mode {
68 	AUTOCAL_MODE_OFF = 0,
69 
70 	/* Autocal calculate the scaling ratio and initial phase and the
71 	 * DSCL_MODE_SEL must be set to 1
72 	 */
73 	AUTOCAL_MODE_AUTOSCALE = 1,
74 	/* Autocal perform auto centering without replication and the
75 	 * DSCL_MODE_SEL must be set to 0
76 	 */
77 	AUTOCAL_MODE_AUTOCENTER = 2,
78 	/* Autocal perform auto centering and auto replication and the
79 	 * DSCL_MODE_SEL must be set to 0
80 	 */
81 	AUTOCAL_MODE_AUTOREPLICATE = 3
82 };
83 
84 enum dscl_mode_sel {
85 	DSCL_MODE_SCALING_444_BYPASS = 0,
86 	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
87 	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
88 	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
89 	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
90 	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
91 	DSCL_MODE_DSCL_BYPASS = 6
92 };
93 
94 enum gamut_remap_select {
95 	GAMUT_REMAP_BYPASS = 0,
96 	GAMUT_REMAP_COEFF,
97 	GAMUT_REMAP_COMA_COEFF,
98 	GAMUT_REMAP_COMB_COEFF
99 };
100 
101 /* Program gamut remap in bypass mode */
102 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
103 {
104 	REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
105 			CM_GAMUT_REMAP_MODE, 0);
106 	/* Gamut remap in bypass */
107 }
108 
109 #define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
110 
111 
112 bool dpp_get_optimal_number_of_taps(
113 		struct dpp *dpp,
114 		struct scaler_data *scl_data,
115 		const struct scaling_taps *in_taps)
116 {
117 	uint32_t pixel_width;
118 
119 	if (scl_data->viewport.width > scl_data->recout.width)
120 		pixel_width = scl_data->recout.width;
121 	else
122 		pixel_width = scl_data->viewport.width;
123 
124 	/* TODO: add lb check */
125 
126 	/* No support for programming ratio of 4, drop to 3.99999.. */
127 	if (scl_data->ratios.horz.value == (4ll << 32))
128 		scl_data->ratios.horz.value--;
129 	if (scl_data->ratios.vert.value == (4ll << 32))
130 		scl_data->ratios.vert.value--;
131 	if (scl_data->ratios.horz_c.value == (4ll << 32))
132 		scl_data->ratios.horz_c.value--;
133 	if (scl_data->ratios.vert_c.value == (4ll << 32))
134 		scl_data->ratios.vert_c.value--;
135 
136 	/* Set default taps if none are provided */
137 	if (in_taps->h_taps == 0)
138 		scl_data->taps.h_taps = 4;
139 	else
140 		scl_data->taps.h_taps = in_taps->h_taps;
141 	if (in_taps->v_taps == 0)
142 		scl_data->taps.v_taps = 4;
143 	else
144 		scl_data->taps.v_taps = in_taps->v_taps;
145 	if (in_taps->v_taps_c == 0)
146 		scl_data->taps.v_taps_c = 2;
147 	else
148 		scl_data->taps.v_taps_c = in_taps->v_taps_c;
149 	if (in_taps->h_taps_c == 0)
150 		scl_data->taps.h_taps_c = 2;
151 	/* Only 1 and even h_taps_c are supported by hw */
152 	else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
153 		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
154 	else
155 		scl_data->taps.h_taps_c = in_taps->h_taps_c;
156 
157 	if (!dpp->ctx->dc->debug.always_scale) {
158 		if (IDENTITY_RATIO(scl_data->ratios.horz))
159 			scl_data->taps.h_taps = 1;
160 		if (IDENTITY_RATIO(scl_data->ratios.vert))
161 			scl_data->taps.v_taps = 1;
162 		if (IDENTITY_RATIO(scl_data->ratios.horz_c))
163 			scl_data->taps.h_taps_c = 1;
164 		if (IDENTITY_RATIO(scl_data->ratios.vert_c))
165 			scl_data->taps.v_taps_c = 1;
166 	}
167 
168 	return true;
169 }
170 
171 void dpp_reset(struct dpp *dpp_base)
172 {
173 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
174 
175 	dpp->filter_h_c = NULL;
176 	dpp->filter_v_c = NULL;
177 	dpp->filter_h = NULL;
178 	dpp->filter_v = NULL;
179 
180 	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
181 	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
182 }
183 
184 
185 
186 static void dpp1_cm_set_regamma_pwl(
187 	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
188 {
189 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
190 	uint32_t re_mode = 0;
191 
192 	switch (mode) {
193 	case OPP_REGAMMA_BYPASS:
194 		re_mode = 0;
195 		break;
196 	case OPP_REGAMMA_SRGB:
197 		re_mode = 1;
198 		break;
199 	case OPP_REGAMMA_XVYCC:
200 		re_mode = 2;
201 		break;
202 	case OPP_REGAMMA_USER:
203 		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
204 		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
205 			break;
206 
207 		dpp1_cm_power_on_regamma_lut(dpp_base, true);
208 		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
209 
210 		if (dpp->is_write_to_ram_a_safe)
211 			dpp1_cm_program_regamma_luta_settings(dpp_base, params);
212 		else
213 			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
214 
215 		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
216 					    params->hw_points_num);
217 		dpp->pwl_data = *params;
218 
219 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
220 		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
221 		break;
222 	default:
223 		break;
224 	}
225 	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
226 }
227 
228 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
229 						enum pixel_format_description *fmt)
230 {
231 
232 	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
233 		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
234 		*fmt = PIXEL_FORMAT_FLOAT;
235 	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
236 		*fmt = PIXEL_FORMAT_FIXED16;
237 	else
238 		*fmt = PIXEL_FORMAT_FIXED;
239 }
240 
241 static void dpp1_set_degamma_format_float(
242 		struct dpp *dpp_base,
243 		bool is_float)
244 {
245 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
246 
247 	if (is_float) {
248 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
249 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
250 	} else {
251 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
252 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
253 	}
254 }
255 
256 void dpp1_cnv_setup (
257 		struct dpp *dpp_base,
258 		enum surface_pixel_format format,
259 		enum expansion_mode mode,
260 		struct csc_transform input_csc_color_matrix,
261 		enum dc_color_space input_color_space)
262 {
263 	uint32_t pixel_format;
264 	uint32_t alpha_en;
265 	enum pixel_format_description fmt ;
266 	enum dc_color_space color_space;
267 	enum dcn10_input_csc_select select;
268 	bool is_float;
269 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
270 	bool force_disable_cursor = false;
271 	struct out_csc_color_matrix tbl_entry;
272 	int i = 0;
273 
274 	dpp1_setup_format_flags(format, &fmt);
275 	alpha_en = 1;
276 	pixel_format = 0;
277 	color_space = COLOR_SPACE_SRGB;
278 	select = INPUT_CSC_SELECT_BYPASS;
279 	is_float = false;
280 
281 	switch (fmt) {
282 	case PIXEL_FORMAT_FIXED:
283 	case PIXEL_FORMAT_FIXED16:
284 	/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
285 		REG_SET_3(FORMAT_CONTROL, 0,
286 			CNVC_BYPASS, 0,
287 			FORMAT_EXPANSION_MODE, mode,
288 			OUTPUT_FP, 0);
289 		break;
290 	case PIXEL_FORMAT_FLOAT:
291 		REG_SET_3(FORMAT_CONTROL, 0,
292 			CNVC_BYPASS, 0,
293 			FORMAT_EXPANSION_MODE, mode,
294 			OUTPUT_FP, 1);
295 		is_float = true;
296 		break;
297 	default:
298 
299 		break;
300 	}
301 
302 	dpp1_set_degamma_format_float(dpp_base, is_float);
303 
304 	switch (format) {
305 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
306 		pixel_format = 1;
307 		break;
308 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
309 		pixel_format = 3;
310 		alpha_en = 0;
311 		break;
312 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
313 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
314 		pixel_format = 8;
315 		break;
316 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
317 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
318 		pixel_format = 10;
319 		break;
320 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
321 		force_disable_cursor = false;
322 		pixel_format = 65;
323 		color_space = COLOR_SPACE_YCBCR709;
324 		select = INPUT_CSC_SELECT_ICSC;
325 		break;
326 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
327 		force_disable_cursor = true;
328 		pixel_format = 64;
329 		color_space = COLOR_SPACE_YCBCR709;
330 		select = INPUT_CSC_SELECT_ICSC;
331 		break;
332 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
333 		force_disable_cursor = true;
334 		pixel_format = 67;
335 		color_space = COLOR_SPACE_YCBCR709;
336 		select = INPUT_CSC_SELECT_ICSC;
337 		break;
338 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
339 		force_disable_cursor = true;
340 		pixel_format = 66;
341 		color_space = COLOR_SPACE_YCBCR709;
342 		select = INPUT_CSC_SELECT_ICSC;
343 		break;
344 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
345 		pixel_format = 22;
346 		break;
347 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
348 		pixel_format = 24;
349 		break;
350 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
351 		pixel_format = 25;
352 		break;
353 	default:
354 		break;
355 	}
356 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
357 			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
358 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
359 
360 	// if input adjustments exist, program icsc with those values
361 
362 	if (input_csc_color_matrix.enable_adjustment
363 				== true) {
364 		for (i = 0; i < 12; i++)
365 			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
366 
367 		tbl_entry.color_space = input_color_space;
368 
369 		if (color_space >= COLOR_SPACE_YCBCR601)
370 			select = INPUT_CSC_SELECT_ICSC;
371 		else
372 			select = INPUT_CSC_SELECT_BYPASS;
373 
374 		dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
375 	} else
376 		dpp1_program_input_csc(dpp_base, color_space, select, NULL);
377 
378 	if (force_disable_cursor) {
379 		REG_UPDATE(CURSOR_CONTROL,
380 				CURSOR_ENABLE, 0);
381 		REG_UPDATE(CURSOR0_CONTROL,
382 				CUR0_ENABLE, 0);
383 	}
384 }
385 
386 void dpp1_set_cursor_attributes(
387 		struct dpp *dpp_base,
388 		enum dc_cursor_color_format color_format)
389 {
390 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
391 
392 	REG_UPDATE_2(CURSOR0_CONTROL,
393 			CUR0_MODE, color_format,
394 			CUR0_EXPANSION_MODE, 0);
395 
396 	if (color_format == CURSOR_MODE_MONO) {
397 		/* todo: clarify what to program these to */
398 		REG_UPDATE(CURSOR0_COLOR0,
399 				CUR0_COLOR0, 0x00000000);
400 		REG_UPDATE(CURSOR0_COLOR1,
401 				CUR0_COLOR1, 0xFFFFFFFF);
402 	}
403 }
404 
405 
406 void dpp1_set_cursor_position(
407 		struct dpp *dpp_base,
408 		const struct dc_cursor_position *pos,
409 		const struct dc_cursor_mi_param *param,
410 		uint32_t width)
411 {
412 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
413 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
414 	uint32_t cur_en = pos->enable ? 1 : 0;
415 
416 	if (src_x_offset >= (int)param->viewport_width)
417 		cur_en = 0;  /* not visible beyond right edge*/
418 
419 	if (src_x_offset + (int)width < 0)
420 		cur_en = 0;  /* not visible beyond left edge*/
421 
422 	REG_UPDATE(CURSOR0_CONTROL,
423 			CUR0_ENABLE, cur_en);
424 
425 }
426 
427 void dpp1_dppclk_control(
428 		struct dpp *dpp_base,
429 		bool dppclk_div,
430 		bool enable)
431 {
432 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
433 
434 	if (enable) {
435 		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
436 			REG_UPDATE_2(DPP_CONTROL,
437 				DPPCLK_RATE_CONTROL, dppclk_div,
438 				DPP_CLOCK_ENABLE, 1);
439 		else
440 			REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
441 	} else
442 		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
443 }
444 
445 static const struct dpp_funcs dcn10_dpp_funcs = {
446 		.dpp_reset = dpp_reset,
447 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
448 		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
449 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
450 		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
451 		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
452 		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
453 		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
454 		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
455 		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
456 		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
457 		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
458 		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
459 		.dpp_set_degamma = dpp1_set_degamma,
460 		.dpp_program_input_lut		= dpp1_program_input_lut,
461 		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,
462 		.dpp_setup			= dpp1_cnv_setup,
463 		.dpp_full_bypass		= dpp1_full_bypass,
464 		.set_cursor_attributes = dpp1_set_cursor_attributes,
465 		.set_cursor_position = dpp1_set_cursor_position,
466 		.dpp_dppclk_control = dpp1_dppclk_control,
467 		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
468 };
469 
470 static struct dpp_caps dcn10_dpp_cap = {
471 	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
472 	.dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
473 };
474 
475 /*****************************************/
476 /* Constructor, Destructor               */
477 /*****************************************/
478 
479 void dpp1_construct(
480 	struct dcn10_dpp *dpp,
481 	struct dc_context *ctx,
482 	uint32_t inst,
483 	const struct dcn_dpp_registers *tf_regs,
484 	const struct dcn_dpp_shift *tf_shift,
485 	const struct dcn_dpp_mask *tf_mask)
486 {
487 	dpp->base.ctx = ctx;
488 
489 	dpp->base.inst = inst;
490 	dpp->base.funcs = &dcn10_dpp_funcs;
491 	dpp->base.caps = &dcn10_dpp_cap;
492 
493 	dpp->tf_regs = tf_regs;
494 	dpp->tf_shift = tf_shift;
495 	dpp->tf_mask = tf_mask;
496 
497 	dpp->lb_pixel_depth_supported =
498 		LB_PIXEL_DEPTH_18BPP |
499 		LB_PIXEL_DEPTH_24BPP |
500 		LB_PIXEL_DEPTH_30BPP;
501 
502 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
503 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
504 }
505