1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "core_types.h"
29 
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33 
34 #define NUM_PHASES    64
35 #define HORZ_MAX_TAPS 8
36 #define VERT_MAX_TAPS 8
37 
38 #define BLACK_OFFSET_RGB_Y 0x0
39 #define BLACK_OFFSET_CBCR  0x8000
40 
41 #define REG(reg)\
42 	dpp->tf_regs->reg
43 
44 #define CTX \
45 	dpp->base.ctx
46 
47 #undef FN
48 #define FN(reg_name, field_name) \
49 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 
51 enum pixel_format_description {
52 	PIXEL_FORMAT_FIXED = 0,
53 	PIXEL_FORMAT_FIXED16,
54 	PIXEL_FORMAT_FLOAT
55 
56 };
57 
58 enum dcn10_coef_filter_type_sel {
59 	SCL_COEF_LUMA_VERT_FILTER = 0,
60 	SCL_COEF_LUMA_HORZ_FILTER = 1,
61 	SCL_COEF_CHROMA_VERT_FILTER = 2,
62 	SCL_COEF_CHROMA_HORZ_FILTER = 3,
63 	SCL_COEF_ALPHA_VERT_FILTER = 4,
64 	SCL_COEF_ALPHA_HORZ_FILTER = 5
65 };
66 
67 enum dscl_autocal_mode {
68 	AUTOCAL_MODE_OFF = 0,
69 
70 	/* Autocal calculate the scaling ratio and initial phase and the
71 	 * DSCL_MODE_SEL must be set to 1
72 	 */
73 	AUTOCAL_MODE_AUTOSCALE = 1,
74 	/* Autocal perform auto centering without replication and the
75 	 * DSCL_MODE_SEL must be set to 0
76 	 */
77 	AUTOCAL_MODE_AUTOCENTER = 2,
78 	/* Autocal perform auto centering and auto replication and the
79 	 * DSCL_MODE_SEL must be set to 0
80 	 */
81 	AUTOCAL_MODE_AUTOREPLICATE = 3
82 };
83 
84 enum dscl_mode_sel {
85 	DSCL_MODE_SCALING_444_BYPASS = 0,
86 	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
87 	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
88 	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
89 	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
90 	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
91 	DSCL_MODE_DSCL_BYPASS = 6
92 };
93 
94 enum gamut_remap_select {
95 	GAMUT_REMAP_BYPASS = 0,
96 	GAMUT_REMAP_COEFF,
97 	GAMUT_REMAP_COMA_COEFF,
98 	GAMUT_REMAP_COMB_COEFF
99 };
100 
101 void dpp_read_state(struct dpp *dpp_base,
102 		struct dcn_dpp_state *s)
103 {
104 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
105 
106 	REG_GET(DPP_CONTROL,
107 			DPP_CLOCK_ENABLE, &s->is_enabled);
108 	REG_GET(CM_IGAM_CONTROL,
109 			CM_IGAM_LUT_MODE, &s->igam_lut_mode);
110 	REG_GET(CM_IGAM_CONTROL,
111 			CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
112 	REG_GET(CM_DGAM_CONTROL,
113 			CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
114 	REG_GET(CM_RGAM_CONTROL,
115 			CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
116 	REG_GET(CM_GAMUT_REMAP_CONTROL,
117 			CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
118 
119 	if (s->gamut_remap_mode) {
120 		s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
121 		s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
122 		s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
123 		s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
124 		s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
125 		s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
126 	}
127 }
128 
129 /* Program gamut remap in bypass mode */
130 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
131 {
132 	REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
133 			CM_GAMUT_REMAP_MODE, 0);
134 	/* Gamut remap in bypass */
135 }
136 
137 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
138 
139 static bool dpp_get_optimal_number_of_taps(
140 		struct dpp *dpp,
141 		struct scaler_data *scl_data,
142 		const struct scaling_taps *in_taps)
143 {
144 	uint32_t pixel_width;
145 
146 	if (scl_data->viewport.width > scl_data->recout.width)
147 		pixel_width = scl_data->recout.width;
148 	else
149 		pixel_width = scl_data->viewport.width;
150 
151 	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
152 	if (scl_data->format == PIXEL_FORMAT_FP16 &&
153 		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
154 		scl_data->ratios.horz.value != dc_fixpt_one.value &&
155 		scl_data->ratios.vert.value != dc_fixpt_one.value)
156 		return false;
157 
158 	if (scl_data->viewport.width > scl_data->h_active &&
159 		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
160 		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
161 		return false;
162 
163 	/* TODO: add lb check */
164 
165 	/* No support for programming ratio of 4, drop to 3.99999.. */
166 	if (scl_data->ratios.horz.value == (4ll << 32))
167 		scl_data->ratios.horz.value--;
168 	if (scl_data->ratios.vert.value == (4ll << 32))
169 		scl_data->ratios.vert.value--;
170 	if (scl_data->ratios.horz_c.value == (4ll << 32))
171 		scl_data->ratios.horz_c.value--;
172 	if (scl_data->ratios.vert_c.value == (4ll << 32))
173 		scl_data->ratios.vert_c.value--;
174 
175 	/* Set default taps if none are provided */
176 	if (in_taps->h_taps == 0)
177 		scl_data->taps.h_taps = 4;
178 	else
179 		scl_data->taps.h_taps = in_taps->h_taps;
180 	if (in_taps->v_taps == 0)
181 		scl_data->taps.v_taps = 4;
182 	else
183 		scl_data->taps.v_taps = in_taps->v_taps;
184 	if (in_taps->v_taps_c == 0)
185 		scl_data->taps.v_taps_c = 2;
186 	else
187 		scl_data->taps.v_taps_c = in_taps->v_taps_c;
188 	if (in_taps->h_taps_c == 0)
189 		scl_data->taps.h_taps_c = 2;
190 	/* Only 1 and even h_taps_c are supported by hw */
191 	else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
192 		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
193 	else
194 		scl_data->taps.h_taps_c = in_taps->h_taps_c;
195 
196 	if (!dpp->ctx->dc->debug.always_scale) {
197 		if (IDENTITY_RATIO(scl_data->ratios.horz))
198 			scl_data->taps.h_taps = 1;
199 		if (IDENTITY_RATIO(scl_data->ratios.vert))
200 			scl_data->taps.v_taps = 1;
201 		if (IDENTITY_RATIO(scl_data->ratios.horz_c))
202 			scl_data->taps.h_taps_c = 1;
203 		if (IDENTITY_RATIO(scl_data->ratios.vert_c))
204 			scl_data->taps.v_taps_c = 1;
205 	}
206 
207 	return true;
208 }
209 
210 void dpp_reset(struct dpp *dpp_base)
211 {
212 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
213 
214 	dpp->filter_h_c = NULL;
215 	dpp->filter_v_c = NULL;
216 	dpp->filter_h = NULL;
217 	dpp->filter_v = NULL;
218 
219 	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
220 	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
221 }
222 
223 
224 
225 static void dpp1_cm_set_regamma_pwl(
226 	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
227 {
228 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
229 	uint32_t re_mode = 0;
230 
231 	switch (mode) {
232 	case OPP_REGAMMA_BYPASS:
233 		re_mode = 0;
234 		break;
235 	case OPP_REGAMMA_SRGB:
236 		re_mode = 1;
237 		break;
238 	case OPP_REGAMMA_XVYCC:
239 		re_mode = 2;
240 		break;
241 	case OPP_REGAMMA_USER:
242 		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
243 		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
244 			break;
245 
246 		dpp1_cm_power_on_regamma_lut(dpp_base, true);
247 		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
248 
249 		if (dpp->is_write_to_ram_a_safe)
250 			dpp1_cm_program_regamma_luta_settings(dpp_base, params);
251 		else
252 			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
253 
254 		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
255 					    params->hw_points_num);
256 		dpp->pwl_data = *params;
257 
258 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
259 		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
260 		break;
261 	default:
262 		break;
263 	}
264 	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
265 }
266 
267 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
268 						enum pixel_format_description *fmt)
269 {
270 
271 	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
272 		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
273 		*fmt = PIXEL_FORMAT_FLOAT;
274 	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
275 		*fmt = PIXEL_FORMAT_FIXED16;
276 	else
277 		*fmt = PIXEL_FORMAT_FIXED;
278 }
279 
280 static void dpp1_set_degamma_format_float(
281 		struct dpp *dpp_base,
282 		bool is_float)
283 {
284 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
285 
286 	if (is_float) {
287 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
288 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
289 	} else {
290 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
291 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
292 	}
293 }
294 
295 void dpp1_cnv_setup (
296 		struct dpp *dpp_base,
297 		enum surface_pixel_format format,
298 		enum expansion_mode mode,
299 		struct dc_csc_transform input_csc_color_matrix,
300 		enum dc_color_space input_color_space)
301 {
302 	uint32_t pixel_format;
303 	uint32_t alpha_en;
304 	enum pixel_format_description fmt ;
305 	enum dc_color_space color_space;
306 	enum dcn10_input_csc_select select;
307 	bool is_float;
308 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
309 	bool force_disable_cursor = false;
310 	struct out_csc_color_matrix tbl_entry;
311 	int i = 0;
312 
313 	dpp1_setup_format_flags(format, &fmt);
314 	alpha_en = 1;
315 	pixel_format = 0;
316 	color_space = COLOR_SPACE_SRGB;
317 	select = INPUT_CSC_SELECT_BYPASS;
318 	is_float = false;
319 
320 	switch (fmt) {
321 	case PIXEL_FORMAT_FIXED:
322 	case PIXEL_FORMAT_FIXED16:
323 	/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
324 		REG_SET_3(FORMAT_CONTROL, 0,
325 			CNVC_BYPASS, 0,
326 			FORMAT_EXPANSION_MODE, mode,
327 			OUTPUT_FP, 0);
328 		break;
329 	case PIXEL_FORMAT_FLOAT:
330 		REG_SET_3(FORMAT_CONTROL, 0,
331 			CNVC_BYPASS, 0,
332 			FORMAT_EXPANSION_MODE, mode,
333 			OUTPUT_FP, 1);
334 		is_float = true;
335 		break;
336 	default:
337 
338 		break;
339 	}
340 
341 	dpp1_set_degamma_format_float(dpp_base, is_float);
342 
343 	switch (format) {
344 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
345 		pixel_format = 1;
346 		break;
347 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
348 		pixel_format = 3;
349 		alpha_en = 0;
350 		break;
351 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
352 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
353 		pixel_format = 8;
354 		break;
355 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
356 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
357 		pixel_format = 10;
358 		break;
359 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
360 		force_disable_cursor = false;
361 		pixel_format = 65;
362 		color_space = COLOR_SPACE_YCBCR709;
363 		select = INPUT_CSC_SELECT_ICSC;
364 		break;
365 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
366 		force_disable_cursor = true;
367 		pixel_format = 64;
368 		color_space = COLOR_SPACE_YCBCR709;
369 		select = INPUT_CSC_SELECT_ICSC;
370 		break;
371 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
372 		force_disable_cursor = true;
373 		pixel_format = 67;
374 		color_space = COLOR_SPACE_YCBCR709;
375 		select = INPUT_CSC_SELECT_ICSC;
376 		break;
377 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
378 		force_disable_cursor = true;
379 		pixel_format = 66;
380 		color_space = COLOR_SPACE_YCBCR709;
381 		select = INPUT_CSC_SELECT_ICSC;
382 		break;
383 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
384 		pixel_format = 22;
385 		break;
386 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
387 		pixel_format = 24;
388 		break;
389 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
390 		pixel_format = 25;
391 		break;
392 	default:
393 		break;
394 	}
395 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
396 			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
397 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
398 
399 	// if input adjustments exist, program icsc with those values
400 
401 	if (input_csc_color_matrix.enable_adjustment
402 				== true) {
403 		for (i = 0; i < 12; i++)
404 			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
405 
406 		tbl_entry.color_space = input_color_space;
407 
408 		if (color_space >= COLOR_SPACE_YCBCR601)
409 			select = INPUT_CSC_SELECT_ICSC;
410 		else
411 			select = INPUT_CSC_SELECT_BYPASS;
412 
413 		dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
414 	} else
415 		dpp1_program_input_csc(dpp_base, color_space, select, NULL);
416 
417 	if (force_disable_cursor) {
418 		REG_UPDATE(CURSOR_CONTROL,
419 				CURSOR_ENABLE, 0);
420 		REG_UPDATE(CURSOR0_CONTROL,
421 				CUR0_ENABLE, 0);
422 	}
423 }
424 
425 void dpp1_set_cursor_attributes(
426 		struct dpp *dpp_base,
427 		enum dc_cursor_color_format color_format)
428 {
429 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
430 
431 	REG_UPDATE_2(CURSOR0_CONTROL,
432 			CUR0_MODE, color_format,
433 			CUR0_EXPANSION_MODE, 0);
434 
435 	if (color_format == CURSOR_MODE_MONO) {
436 		/* todo: clarify what to program these to */
437 		REG_UPDATE(CURSOR0_COLOR0,
438 				CUR0_COLOR0, 0x00000000);
439 		REG_UPDATE(CURSOR0_COLOR1,
440 				CUR0_COLOR1, 0xFFFFFFFF);
441 	}
442 }
443 
444 
445 void dpp1_set_cursor_position(
446 		struct dpp *dpp_base,
447 		const struct dc_cursor_position *pos,
448 		const struct dc_cursor_mi_param *param,
449 		uint32_t width,
450 		uint32_t height)
451 {
452 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
453 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
454 	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
455 	uint32_t cur_en = pos->enable ? 1 : 0;
456 
457 	if (src_x_offset >= (int)param->viewport.width)
458 		cur_en = 0;  /* not visible beyond right edge*/
459 
460 	if (src_x_offset + (int)width <= 0)
461 		cur_en = 0;  /* not visible beyond left edge*/
462 
463 	if (src_y_offset >= (int)param->viewport.height)
464 		cur_en = 0;  /* not visible beyond bottom edge*/
465 
466 	if (src_y_offset + (int)height <= 0)
467 		cur_en = 0;  /* not visible beyond top edge*/
468 
469 	REG_UPDATE(CURSOR0_CONTROL,
470 			CUR0_ENABLE, cur_en);
471 
472 }
473 
474 void dpp1_cnv_set_optional_cursor_attributes(
475 		struct dpp *dpp_base,
476 		struct dpp_cursor_attributes *attr)
477 {
478 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
479 
480 	if (attr) {
481 		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
482 		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
483 	}
484 }
485 
486 void dpp1_dppclk_control(
487 		struct dpp *dpp_base,
488 		bool dppclk_div,
489 		bool enable)
490 {
491 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
492 
493 	if (enable) {
494 		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
495 			REG_UPDATE_2(DPP_CONTROL,
496 				DPPCLK_RATE_CONTROL, dppclk_div,
497 				DPP_CLOCK_ENABLE, 1);
498 		else
499 			REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
500 	} else
501 		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
502 }
503 
504 static const struct dpp_funcs dcn10_dpp_funcs = {
505 		.dpp_read_state = dpp_read_state,
506 		.dpp_reset = dpp_reset,
507 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
508 		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
509 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
510 		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
511 		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
512 		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
513 		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
514 		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
515 		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
516 		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
517 		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
518 		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
519 		.dpp_set_degamma = dpp1_set_degamma,
520 		.dpp_program_input_lut		= dpp1_program_input_lut,
521 		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,
522 		.dpp_setup			= dpp1_cnv_setup,
523 		.dpp_full_bypass		= dpp1_full_bypass,
524 		.set_cursor_attributes = dpp1_set_cursor_attributes,
525 		.set_cursor_position = dpp1_set_cursor_position,
526 		.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
527 		.dpp_dppclk_control = dpp1_dppclk_control,
528 		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
529 };
530 
531 static struct dpp_caps dcn10_dpp_cap = {
532 	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
533 	.dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
534 };
535 
536 /*****************************************/
537 /* Constructor, Destructor               */
538 /*****************************************/
539 
540 void dpp1_construct(
541 	struct dcn10_dpp *dpp,
542 	struct dc_context *ctx,
543 	uint32_t inst,
544 	const struct dcn_dpp_registers *tf_regs,
545 	const struct dcn_dpp_shift *tf_shift,
546 	const struct dcn_dpp_mask *tf_mask)
547 {
548 	dpp->base.ctx = ctx;
549 
550 	dpp->base.inst = inst;
551 	dpp->base.funcs = &dcn10_dpp_funcs;
552 	dpp->base.caps = &dcn10_dpp_cap;
553 
554 	dpp->tf_regs = tf_regs;
555 	dpp->tf_shift = tf_shift;
556 	dpp->tf_mask = tf_mask;
557 
558 	dpp->lb_pixel_depth_supported =
559 		LB_PIXEL_DEPTH_18BPP |
560 		LB_PIXEL_DEPTH_24BPP |
561 		LB_PIXEL_DEPTH_30BPP;
562 
563 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
564 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
565 }
566