1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn10_dpp.h" 32 #include "basics/conversion.h" 33 34 #define NUM_PHASES 64 35 #define HORZ_MAX_TAPS 8 36 #define VERT_MAX_TAPS 8 37 38 #define BLACK_OFFSET_RGB_Y 0x0 39 #define BLACK_OFFSET_CBCR 0x8000 40 41 #define REG(reg)\ 42 dpp->tf_regs->reg 43 44 #define CTX \ 45 dpp->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 50 51 enum pixel_format_description { 52 PIXEL_FORMAT_FIXED = 0, 53 PIXEL_FORMAT_FIXED16, 54 PIXEL_FORMAT_FLOAT 55 56 }; 57 58 enum dcn10_coef_filter_type_sel { 59 SCL_COEF_LUMA_VERT_FILTER = 0, 60 SCL_COEF_LUMA_HORZ_FILTER = 1, 61 SCL_COEF_CHROMA_VERT_FILTER = 2, 62 SCL_COEF_CHROMA_HORZ_FILTER = 3, 63 SCL_COEF_ALPHA_VERT_FILTER = 4, 64 SCL_COEF_ALPHA_HORZ_FILTER = 5 65 }; 66 67 enum dscl_autocal_mode { 68 AUTOCAL_MODE_OFF = 0, 69 70 /* Autocal calculate the scaling ratio and initial phase and the 71 * DSCL_MODE_SEL must be set to 1 72 */ 73 AUTOCAL_MODE_AUTOSCALE = 1, 74 /* Autocal perform auto centering without replication and the 75 * DSCL_MODE_SEL must be set to 0 76 */ 77 AUTOCAL_MODE_AUTOCENTER = 2, 78 /* Autocal perform auto centering and auto replication and the 79 * DSCL_MODE_SEL must be set to 0 80 */ 81 AUTOCAL_MODE_AUTOREPLICATE = 3 82 }; 83 84 enum dscl_mode_sel { 85 DSCL_MODE_SCALING_444_BYPASS = 0, 86 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 87 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 88 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 89 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 90 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 91 DSCL_MODE_DSCL_BYPASS = 6 92 }; 93 94 enum gamut_remap_select { 95 GAMUT_REMAP_BYPASS = 0, 96 GAMUT_REMAP_COEFF, 97 GAMUT_REMAP_COMA_COEFF, 98 GAMUT_REMAP_COMB_COEFF 99 }; 100 101 void dpp_read_state(struct dpp *dpp_base, 102 struct dcn_dpp_state *s) 103 { 104 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 105 106 REG_GET(CM_IGAM_CONTROL, 107 CM_IGAM_LUT_MODE, &s->igam_lut_mode); 108 REG_GET(CM_IGAM_CONTROL, 109 CM_IGAM_INPUT_FORMAT, &s->igam_input_format); 110 REG_GET(CM_DGAM_CONTROL, 111 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); 112 REG_GET(CM_RGAM_CONTROL, 113 CM_RGAM_LUT_MODE, &s->rgam_lut_mode); 114 REG_GET(CM_GAMUT_REMAP_CONTROL, 115 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); 116 117 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); 118 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); 119 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); 120 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); 121 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); 122 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); 123 } 124 125 /* Program gamut remap in bypass mode */ 126 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) 127 { 128 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, 129 CM_GAMUT_REMAP_MODE, 0); 130 /* Gamut remap in bypass */ 131 } 132 133 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) 134 135 static bool dpp_get_optimal_number_of_taps( 136 struct dpp *dpp, 137 struct scaler_data *scl_data, 138 const struct scaling_taps *in_taps) 139 { 140 uint32_t pixel_width; 141 142 if (scl_data->viewport.width > scl_data->recout.width) 143 pixel_width = scl_data->recout.width; 144 else 145 pixel_width = scl_data->viewport.width; 146 147 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ 148 if (scl_data->format == PIXEL_FORMAT_FP16 && 149 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 150 scl_data->ratios.horz.value != dc_fixpt_one.value && 151 scl_data->ratios.vert.value != dc_fixpt_one.value) 152 return false; 153 154 if (scl_data->viewport.width > scl_data->h_active && 155 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 156 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 157 return false; 158 159 /* TODO: add lb check */ 160 161 /* No support for programming ratio of 4, drop to 3.99999.. */ 162 if (scl_data->ratios.horz.value == (4ll << 32)) 163 scl_data->ratios.horz.value--; 164 if (scl_data->ratios.vert.value == (4ll << 32)) 165 scl_data->ratios.vert.value--; 166 if (scl_data->ratios.horz_c.value == (4ll << 32)) 167 scl_data->ratios.horz_c.value--; 168 if (scl_data->ratios.vert_c.value == (4ll << 32)) 169 scl_data->ratios.vert_c.value--; 170 171 /* Set default taps if none are provided */ 172 if (in_taps->h_taps == 0) 173 scl_data->taps.h_taps = 4; 174 else 175 scl_data->taps.h_taps = in_taps->h_taps; 176 if (in_taps->v_taps == 0) 177 scl_data->taps.v_taps = 4; 178 else 179 scl_data->taps.v_taps = in_taps->v_taps; 180 if (in_taps->v_taps_c == 0) 181 scl_data->taps.v_taps_c = 2; 182 else 183 scl_data->taps.v_taps_c = in_taps->v_taps_c; 184 if (in_taps->h_taps_c == 0) 185 scl_data->taps.h_taps_c = 2; 186 /* Only 1 and even h_taps_c are supported by hw */ 187 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 188 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 189 else 190 scl_data->taps.h_taps_c = in_taps->h_taps_c; 191 192 if (!dpp->ctx->dc->debug.always_scale) { 193 if (IDENTITY_RATIO(scl_data->ratios.horz)) 194 scl_data->taps.h_taps = 1; 195 if (IDENTITY_RATIO(scl_data->ratios.vert)) 196 scl_data->taps.v_taps = 1; 197 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 198 scl_data->taps.h_taps_c = 1; 199 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 200 scl_data->taps.v_taps_c = 1; 201 } 202 203 return true; 204 } 205 206 void dpp_reset(struct dpp *dpp_base) 207 { 208 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 209 210 dpp->filter_h_c = NULL; 211 dpp->filter_v_c = NULL; 212 dpp->filter_h = NULL; 213 dpp->filter_v = NULL; 214 215 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); 216 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); 217 } 218 219 220 221 static void dpp1_cm_set_regamma_pwl( 222 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) 223 { 224 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 225 uint32_t re_mode = 0; 226 227 switch (mode) { 228 case OPP_REGAMMA_BYPASS: 229 re_mode = 0; 230 break; 231 case OPP_REGAMMA_SRGB: 232 re_mode = 1; 233 break; 234 case OPP_REGAMMA_XVYCC: 235 re_mode = 2; 236 break; 237 case OPP_REGAMMA_USER: 238 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; 239 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) 240 break; 241 242 dpp1_cm_power_on_regamma_lut(dpp_base, true); 243 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); 244 245 if (dpp->is_write_to_ram_a_safe) 246 dpp1_cm_program_regamma_luta_settings(dpp_base, params); 247 else 248 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); 249 250 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, 251 params->hw_points_num); 252 dpp->pwl_data = *params; 253 254 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; 255 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; 256 break; 257 default: 258 break; 259 } 260 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); 261 } 262 263 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ 264 enum pixel_format_description *fmt) 265 { 266 267 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || 268 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) 269 *fmt = PIXEL_FORMAT_FLOAT; 270 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) 271 *fmt = PIXEL_FORMAT_FIXED16; 272 else 273 *fmt = PIXEL_FORMAT_FIXED; 274 } 275 276 static void dpp1_set_degamma_format_float( 277 struct dpp *dpp_base, 278 bool is_float) 279 { 280 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 281 282 if (is_float) { 283 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); 284 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); 285 } else { 286 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); 287 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); 288 } 289 } 290 291 void dpp1_cnv_setup ( 292 struct dpp *dpp_base, 293 enum surface_pixel_format format, 294 enum expansion_mode mode, 295 struct dc_csc_transform input_csc_color_matrix, 296 enum dc_color_space input_color_space) 297 { 298 uint32_t pixel_format; 299 uint32_t alpha_en; 300 enum pixel_format_description fmt ; 301 enum dc_color_space color_space; 302 enum dcn10_input_csc_select select; 303 bool is_float; 304 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 305 bool force_disable_cursor = false; 306 struct out_csc_color_matrix tbl_entry; 307 int i = 0; 308 309 dpp1_setup_format_flags(format, &fmt); 310 alpha_en = 1; 311 pixel_format = 0; 312 color_space = COLOR_SPACE_SRGB; 313 select = INPUT_CSC_SELECT_BYPASS; 314 is_float = false; 315 316 switch (fmt) { 317 case PIXEL_FORMAT_FIXED: 318 case PIXEL_FORMAT_FIXED16: 319 /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ 320 REG_SET_3(FORMAT_CONTROL, 0, 321 CNVC_BYPASS, 0, 322 FORMAT_EXPANSION_MODE, mode, 323 OUTPUT_FP, 0); 324 break; 325 case PIXEL_FORMAT_FLOAT: 326 REG_SET_3(FORMAT_CONTROL, 0, 327 CNVC_BYPASS, 0, 328 FORMAT_EXPANSION_MODE, mode, 329 OUTPUT_FP, 1); 330 is_float = true; 331 break; 332 default: 333 334 break; 335 } 336 337 dpp1_set_degamma_format_float(dpp_base, is_float); 338 339 switch (format) { 340 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 341 pixel_format = 1; 342 break; 343 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 344 pixel_format = 3; 345 alpha_en = 0; 346 break; 347 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 348 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 349 pixel_format = 8; 350 break; 351 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 352 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 353 pixel_format = 10; 354 break; 355 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 356 force_disable_cursor = false; 357 pixel_format = 65; 358 color_space = COLOR_SPACE_YCBCR709; 359 select = INPUT_CSC_SELECT_ICSC; 360 break; 361 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 362 force_disable_cursor = true; 363 pixel_format = 64; 364 color_space = COLOR_SPACE_YCBCR709; 365 select = INPUT_CSC_SELECT_ICSC; 366 break; 367 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 368 force_disable_cursor = true; 369 pixel_format = 67; 370 color_space = COLOR_SPACE_YCBCR709; 371 select = INPUT_CSC_SELECT_ICSC; 372 break; 373 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 374 force_disable_cursor = true; 375 pixel_format = 66; 376 color_space = COLOR_SPACE_YCBCR709; 377 select = INPUT_CSC_SELECT_ICSC; 378 break; 379 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 380 pixel_format = 22; 381 break; 382 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 383 pixel_format = 24; 384 break; 385 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 386 pixel_format = 25; 387 break; 388 default: 389 break; 390 } 391 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, 392 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); 393 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 394 395 // if input adjustments exist, program icsc with those values 396 397 if (input_csc_color_matrix.enable_adjustment 398 == true) { 399 for (i = 0; i < 12; i++) 400 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 401 402 tbl_entry.color_space = input_color_space; 403 404 if (color_space >= COLOR_SPACE_YCBCR601) 405 select = INPUT_CSC_SELECT_ICSC; 406 else 407 select = INPUT_CSC_SELECT_BYPASS; 408 409 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); 410 } else 411 dpp1_program_input_csc(dpp_base, color_space, select, NULL); 412 413 if (force_disable_cursor) { 414 REG_UPDATE(CURSOR_CONTROL, 415 CURSOR_ENABLE, 0); 416 REG_UPDATE(CURSOR0_CONTROL, 417 CUR0_ENABLE, 0); 418 } 419 } 420 421 void dpp1_set_cursor_attributes( 422 struct dpp *dpp_base, 423 enum dc_cursor_color_format color_format) 424 { 425 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 426 427 REG_UPDATE_2(CURSOR0_CONTROL, 428 CUR0_MODE, color_format, 429 CUR0_EXPANSION_MODE, 0); 430 431 if (color_format == CURSOR_MODE_MONO) { 432 /* todo: clarify what to program these to */ 433 REG_UPDATE(CURSOR0_COLOR0, 434 CUR0_COLOR0, 0x00000000); 435 REG_UPDATE(CURSOR0_COLOR1, 436 CUR0_COLOR1, 0xFFFFFFFF); 437 } 438 } 439 440 441 void dpp1_set_cursor_position( 442 struct dpp *dpp_base, 443 const struct dc_cursor_position *pos, 444 const struct dc_cursor_mi_param *param, 445 uint32_t width) 446 { 447 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 448 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 449 uint32_t cur_en = pos->enable ? 1 : 0; 450 451 if (src_x_offset >= (int)param->viewport.width) 452 cur_en = 0; /* not visible beyond right edge*/ 453 454 if (src_x_offset + (int)width <= 0) 455 cur_en = 0; /* not visible beyond left edge*/ 456 457 REG_UPDATE(CURSOR0_CONTROL, 458 CUR0_ENABLE, cur_en); 459 460 } 461 462 void dpp1_cnv_set_optional_cursor_attributes( 463 struct dpp *dpp_base, 464 struct dpp_cursor_attributes *attr) 465 { 466 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 467 468 if (attr) { 469 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias); 470 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale); 471 } 472 } 473 474 void dpp1_dppclk_control( 475 struct dpp *dpp_base, 476 bool dppclk_div, 477 bool enable) 478 { 479 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 480 481 if (enable) { 482 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) 483 REG_UPDATE_2(DPP_CONTROL, 484 DPPCLK_RATE_CONTROL, dppclk_div, 485 DPP_CLOCK_ENABLE, 1); 486 else 487 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); 488 } else 489 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); 490 } 491 492 static const struct dpp_funcs dcn10_dpp_funcs = { 493 .dpp_read_state = dpp_read_state, 494 .dpp_reset = dpp_reset, 495 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 496 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, 497 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, 498 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, 499 .dpp_set_csc_default = dpp1_cm_set_output_csc_default, 500 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, 501 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, 502 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, 503 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, 504 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, 505 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, 506 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, 507 .dpp_set_degamma = dpp1_set_degamma, 508 .dpp_program_input_lut = dpp1_program_input_lut, 509 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, 510 .dpp_setup = dpp1_cnv_setup, 511 .dpp_full_bypass = dpp1_full_bypass, 512 .set_cursor_attributes = dpp1_set_cursor_attributes, 513 .set_cursor_position = dpp1_set_cursor_position, 514 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 515 .dpp_dppclk_control = dpp1_dppclk_control, 516 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, 517 }; 518 519 static struct dpp_caps dcn10_dpp_cap = { 520 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT, 521 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions, 522 }; 523 524 /*****************************************/ 525 /* Constructor, Destructor */ 526 /*****************************************/ 527 528 void dpp1_construct( 529 struct dcn10_dpp *dpp, 530 struct dc_context *ctx, 531 uint32_t inst, 532 const struct dcn_dpp_registers *tf_regs, 533 const struct dcn_dpp_shift *tf_shift, 534 const struct dcn_dpp_mask *tf_mask) 535 { 536 dpp->base.ctx = ctx; 537 538 dpp->base.inst = inst; 539 dpp->base.funcs = &dcn10_dpp_funcs; 540 dpp->base.caps = &dcn10_dpp_cap; 541 542 dpp->tf_regs = tf_regs; 543 dpp->tf_shift = tf_shift; 544 dpp->tf_mask = tf_mask; 545 546 dpp->lb_pixel_depth_supported = 547 LB_PIXEL_DEPTH_18BPP | 548 LB_PIXEL_DEPTH_24BPP | 549 LB_PIXEL_DEPTH_30BPP; 550 551 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 552 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 553 } 554