1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "core_types.h"
29 
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33 
34 #define NUM_PHASES    64
35 #define HORZ_MAX_TAPS 8
36 #define VERT_MAX_TAPS 8
37 
38 #define BLACK_OFFSET_RGB_Y 0x0
39 #define BLACK_OFFSET_CBCR  0x8000
40 
41 #define REG(reg)\
42 	dpp->tf_regs->reg
43 
44 #define CTX \
45 	dpp->base.ctx
46 
47 #undef FN
48 #define FN(reg_name, field_name) \
49 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 
51 enum pixel_format_description {
52 	PIXEL_FORMAT_FIXED = 0,
53 	PIXEL_FORMAT_FIXED16,
54 	PIXEL_FORMAT_FLOAT
55 
56 };
57 
58 enum dcn10_coef_filter_type_sel {
59 	SCL_COEF_LUMA_VERT_FILTER = 0,
60 	SCL_COEF_LUMA_HORZ_FILTER = 1,
61 	SCL_COEF_CHROMA_VERT_FILTER = 2,
62 	SCL_COEF_CHROMA_HORZ_FILTER = 3,
63 	SCL_COEF_ALPHA_VERT_FILTER = 4,
64 	SCL_COEF_ALPHA_HORZ_FILTER = 5
65 };
66 
67 enum dscl_autocal_mode {
68 	AUTOCAL_MODE_OFF = 0,
69 
70 	/* Autocal calculate the scaling ratio and initial phase and the
71 	 * DSCL_MODE_SEL must be set to 1
72 	 */
73 	AUTOCAL_MODE_AUTOSCALE = 1,
74 	/* Autocal perform auto centering without replication and the
75 	 * DSCL_MODE_SEL must be set to 0
76 	 */
77 	AUTOCAL_MODE_AUTOCENTER = 2,
78 	/* Autocal perform auto centering and auto replication and the
79 	 * DSCL_MODE_SEL must be set to 0
80 	 */
81 	AUTOCAL_MODE_AUTOREPLICATE = 3
82 };
83 
84 enum dscl_mode_sel {
85 	DSCL_MODE_SCALING_444_BYPASS = 0,
86 	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
87 	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
88 	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
89 	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
90 	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
91 	DSCL_MODE_DSCL_BYPASS = 6
92 };
93 
94 enum gamut_remap_select {
95 	GAMUT_REMAP_BYPASS = 0,
96 	GAMUT_REMAP_COEFF,
97 	GAMUT_REMAP_COMA_COEFF,
98 	GAMUT_REMAP_COMB_COEFF
99 };
100 
101 /* Program gamut remap in bypass mode */
102 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
103 {
104 	REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
105 			CM_GAMUT_REMAP_MODE, 0);
106 	/* Gamut remap in bypass */
107 }
108 
109 #define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
110 
111 
112 bool dpp_get_optimal_number_of_taps(
113 		struct dpp *dpp,
114 		struct scaler_data *scl_data,
115 		const struct scaling_taps *in_taps)
116 {
117 	uint32_t pixel_width;
118 
119 	if (scl_data->viewport.width > scl_data->recout.width)
120 		pixel_width = scl_data->recout.width;
121 	else
122 		pixel_width = scl_data->viewport.width;
123 
124 	/* TODO: add lb check */
125 
126 	/* No support for programming ratio of 4, drop to 3.99999.. */
127 	if (scl_data->ratios.horz.value == (4ll << 32))
128 		scl_data->ratios.horz.value--;
129 	if (scl_data->ratios.vert.value == (4ll << 32))
130 		scl_data->ratios.vert.value--;
131 	if (scl_data->ratios.horz_c.value == (4ll << 32))
132 		scl_data->ratios.horz_c.value--;
133 	if (scl_data->ratios.vert_c.value == (4ll << 32))
134 		scl_data->ratios.vert_c.value--;
135 
136 	/* Set default taps if none are provided */
137 	if (in_taps->h_taps == 0)
138 		scl_data->taps.h_taps = 4;
139 	else
140 		scl_data->taps.h_taps = in_taps->h_taps;
141 	if (in_taps->v_taps == 0)
142 		scl_data->taps.v_taps = 4;
143 	else
144 		scl_data->taps.v_taps = in_taps->v_taps;
145 	if (in_taps->v_taps_c == 0)
146 		scl_data->taps.v_taps_c = 2;
147 	else
148 		scl_data->taps.v_taps_c = in_taps->v_taps_c;
149 	if (in_taps->h_taps_c == 0)
150 		scl_data->taps.h_taps_c = 2;
151 	/* Only 1 and even h_taps_c are supported by hw */
152 	else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
153 		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
154 	else
155 		scl_data->taps.h_taps_c = in_taps->h_taps_c;
156 
157 	if (!dpp->ctx->dc->debug.always_scale) {
158 		if (IDENTITY_RATIO(scl_data->ratios.horz))
159 			scl_data->taps.h_taps = 1;
160 		if (IDENTITY_RATIO(scl_data->ratios.vert))
161 			scl_data->taps.v_taps = 1;
162 		/*
163 		 * Spreadsheet doesn't handle taps_c is one properly,
164 		 * need to force Chroma to always be scaled to pass
165 		 * bandwidth validation.
166 		 */
167 	}
168 
169 	return true;
170 }
171 
172 void dpp_reset(struct dpp *dpp_base)
173 {
174 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
175 
176 	dpp->filter_h_c = NULL;
177 	dpp->filter_v_c = NULL;
178 	dpp->filter_h = NULL;
179 	dpp->filter_v = NULL;
180 
181 	/* set boundary mode to 0 */
182 	REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
183 }
184 
185 
186 
187 static void dpp1_cm_set_regamma_pwl(
188 	struct dpp *dpp_base, const struct pwl_params *params)
189 {
190 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
191 
192 	dpp1_cm_power_on_regamma_lut(dpp_base, true);
193 	dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
194 
195 	if (dpp->is_write_to_ram_a_safe)
196 		dpp1_cm_program_regamma_luta_settings(dpp_base, params);
197 	else
198 		dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
199 
200 	dpp1_cm_program_regamma_lut(
201 			dpp_base, params->rgb_resulted, params->hw_points_num);
202 }
203 
204 static void dpp1_cm_set_regamma_mode(
205 	struct dpp *dpp_base,
206 	enum opp_regamma mode)
207 {
208 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
209 	uint32_t re_mode = 0;
210 	uint32_t obuf_bypass = 0; /* need for pipe split */
211 	uint32_t obuf_hupscale = 0;
212 
213 	switch (mode) {
214 	case OPP_REGAMMA_BYPASS:
215 		re_mode = 0;
216 		break;
217 	case OPP_REGAMMA_SRGB:
218 		re_mode = 1;
219 		break;
220 	case OPP_REGAMMA_3_6:
221 		re_mode = 2;
222 		break;
223 	case OPP_REGAMMA_USER:
224 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
225 		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
226 		break;
227 	default:
228 		break;
229 	}
230 
231 	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
232 	REG_UPDATE_2(OBUF_CONTROL,
233 			OBUF_BYPASS, obuf_bypass,
234 			OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
235 }
236 
237 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
238 						enum pixel_format_description *fmt)
239 {
240 
241 	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
242 		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
243 		*fmt = PIXEL_FORMAT_FLOAT;
244 	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
245 		*fmt = PIXEL_FORMAT_FIXED16;
246 	else
247 		*fmt = PIXEL_FORMAT_FIXED;
248 }
249 
250 static void dpp1_set_degamma_format_float(
251 		struct dpp *dpp_base,
252 		bool is_float)
253 {
254 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
255 
256 	if (is_float) {
257 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
258 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
259 	} else {
260 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
261 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
262 	}
263 }
264 
265 void dpp1_cnv_setup (
266 		struct dpp *dpp_base,
267 		enum surface_pixel_format input_format,
268 		enum expansion_mode mode)
269 {
270 	uint32_t pixel_format;
271 	uint32_t alpha_en;
272 	enum pixel_format_description fmt ;
273 	enum dc_color_space color_space;
274 	enum dcn10_input_csc_select select;
275 	bool is_float;
276 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
277 	bool force_disable_cursor = false;
278 
279 	dpp1_setup_format_flags(input_format, &fmt);
280 	alpha_en = 1;
281 	pixel_format = 0;
282 	color_space = COLOR_SPACE_SRGB;
283 	select = INPUT_CSC_SELECT_BYPASS;
284 	is_float = false;
285 
286 	switch (fmt) {
287 	case PIXEL_FORMAT_FIXED:
288 	case PIXEL_FORMAT_FIXED16:
289 	/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
290 		REG_SET_3(FORMAT_CONTROL, 0,
291 			CNVC_BYPASS, 0,
292 			FORMAT_EXPANSION_MODE, mode,
293 			OUTPUT_FP, 0);
294 		break;
295 	case PIXEL_FORMAT_FLOAT:
296 		REG_SET_3(FORMAT_CONTROL, 0,
297 			CNVC_BYPASS, 0,
298 			FORMAT_EXPANSION_MODE, mode,
299 			OUTPUT_FP, 1);
300 		is_float = true;
301 		break;
302 	default:
303 
304 		break;
305 	}
306 
307 	dpp1_set_degamma_format_float(dpp_base, is_float);
308 
309 	switch (input_format) {
310 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
311 		pixel_format = 1;
312 		break;
313 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
314 		pixel_format = 3;
315 		alpha_en = 0;
316 		break;
317 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
318 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
319 		pixel_format = 8;
320 		break;
321 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
322 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
323 		pixel_format = 10;
324 		break;
325 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
326 		force_disable_cursor = false;
327 		pixel_format = 65;
328 		color_space = COLOR_SPACE_YCBCR709;
329 		select = INPUT_CSC_SELECT_ICSC;
330 		break;
331 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
332 		force_disable_cursor = true;
333 		pixel_format = 64;
334 		color_space = COLOR_SPACE_YCBCR709;
335 		select = INPUT_CSC_SELECT_ICSC;
336 		break;
337 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
338 		force_disable_cursor = true;
339 		pixel_format = 67;
340 		color_space = COLOR_SPACE_YCBCR709;
341 		select = INPUT_CSC_SELECT_ICSC;
342 		break;
343 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
344 		force_disable_cursor = true;
345 		pixel_format = 66;
346 		color_space = COLOR_SPACE_YCBCR709;
347 		select = INPUT_CSC_SELECT_ICSC;
348 		break;
349 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
350 		pixel_format = 22;
351 		break;
352 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
353 		pixel_format = 24;
354 		break;
355 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
356 		pixel_format = 25;
357 		break;
358 	default:
359 		break;
360 	}
361 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
362 			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
363 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
364 
365 	dpp1_program_input_csc(dpp_base, color_space, select);
366 
367 	if (force_disable_cursor) {
368 		REG_UPDATE(CURSOR_CONTROL,
369 				CURSOR_ENABLE, 0);
370 		REG_UPDATE(CURSOR0_CONTROL,
371 				CUR0_ENABLE, 0);
372 	}
373 }
374 
375 void dpp1_set_cursor_attributes(
376 		struct dpp *dpp_base,
377 		const struct dc_cursor_attributes *attr)
378 {
379 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
380 	enum dc_cursor_color_format color_format = attr->color_format;
381 
382 	REG_UPDATE_2(CURSOR0_CONTROL,
383 			CUR0_MODE, color_format,
384 			CUR0_EXPANSION_MODE, 0);
385 
386 	if (color_format == CURSOR_MODE_MONO) {
387 		/* todo: clarify what to program these to */
388 		REG_UPDATE(CURSOR0_COLOR0,
389 				CUR0_COLOR0, 0x00000000);
390 		REG_UPDATE(CURSOR0_COLOR1,
391 				CUR0_COLOR1, 0xFFFFFFFF);
392 	}
393 
394 	/* TODO: Fixed vs float */
395 
396 	REG_UPDATE_3(FORMAT_CONTROL,
397 				CNVC_BYPASS, 0,
398 				FORMAT_CONTROL__ALPHA_EN, 1,
399 				FORMAT_EXPANSION_MODE, 0);
400 }
401 
402 
403 void dpp1_set_cursor_position(
404 		struct dpp *dpp_base,
405 		const struct dc_cursor_position *pos,
406 		const struct dc_cursor_mi_param *param,
407 		uint32_t width)
408 {
409 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
410 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
411 	uint32_t cur_en = pos->enable ? 1 : 0;
412 
413 	if (src_x_offset >= (int)param->viewport_width)
414 		cur_en = 0;  /* not visible beyond right edge*/
415 
416 	if (src_x_offset + (int)width < 0)
417 		cur_en = 0;  /* not visible beyond left edge*/
418 
419 	REG_UPDATE(CURSOR0_CONTROL,
420 			CUR0_ENABLE, cur_en);
421 
422 }
423 
424 static const struct dpp_funcs dcn10_dpp_funcs = {
425 		.dpp_reset = dpp_reset,
426 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
427 		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
428 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
429 		.opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
430 		.opp_set_csc_default = dpp1_cm_set_output_csc_default,
431 		.opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
432 		.opp_program_regamma_lut = dpp1_cm_program_regamma_lut,
433 		.opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
434 		.opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
435 		.opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
436 		.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
437 		.opp_set_regamma_mode = dpp1_cm_set_regamma_mode,
438 		.ipp_set_degamma = dpp1_set_degamma,
439 		.ipp_program_input_lut		= dpp1_program_input_lut,
440 		.ipp_program_degamma_pwl	= dpp1_set_degamma_pwl,
441 		.ipp_setup			= dpp1_cnv_setup,
442 		.ipp_full_bypass		= dpp1_full_bypass,
443 		.set_cursor_attributes = dpp1_set_cursor_attributes,
444 		.set_cursor_position = dpp1_set_cursor_position,
445 };
446 
447 static struct dpp_caps dcn10_dpp_cap = {
448 	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
449 	.dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
450 };
451 
452 /*****************************************/
453 /* Constructor, Destructor               */
454 /*****************************************/
455 
456 void dpp1_construct(
457 	struct dcn10_dpp *dpp,
458 	struct dc_context *ctx,
459 	uint32_t inst,
460 	const struct dcn_dpp_registers *tf_regs,
461 	const struct dcn_dpp_shift *tf_shift,
462 	const struct dcn_dpp_mask *tf_mask)
463 {
464 	dpp->base.ctx = ctx;
465 
466 	dpp->base.inst = inst;
467 	dpp->base.funcs = &dcn10_dpp_funcs;
468 	dpp->base.caps = &dcn10_dpp_cap;
469 
470 	dpp->tf_regs = tf_regs;
471 	dpp->tf_shift = tf_shift;
472 	dpp->tf_mask = tf_mask;
473 
474 	dpp->lb_pixel_depth_supported =
475 		LB_PIXEL_DEPTH_18BPP |
476 		LB_PIXEL_DEPTH_24BPP |
477 		LB_PIXEL_DEPTH_30BPP;
478 
479 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
480 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
481 }
482