1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn10_dpp.h" 32 #include "basics/conversion.h" 33 34 #define NUM_PHASES 64 35 #define HORZ_MAX_TAPS 8 36 #define VERT_MAX_TAPS 8 37 38 #define BLACK_OFFSET_RGB_Y 0x0 39 #define BLACK_OFFSET_CBCR 0x8000 40 41 #define REG(reg)\ 42 dpp->tf_regs->reg 43 44 #define CTX \ 45 dpp->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 50 51 enum pixel_format_description { 52 PIXEL_FORMAT_FIXED = 0, 53 PIXEL_FORMAT_FIXED16, 54 PIXEL_FORMAT_FLOAT 55 56 }; 57 58 enum dcn10_coef_filter_type_sel { 59 SCL_COEF_LUMA_VERT_FILTER = 0, 60 SCL_COEF_LUMA_HORZ_FILTER = 1, 61 SCL_COEF_CHROMA_VERT_FILTER = 2, 62 SCL_COEF_CHROMA_HORZ_FILTER = 3, 63 SCL_COEF_ALPHA_VERT_FILTER = 4, 64 SCL_COEF_ALPHA_HORZ_FILTER = 5 65 }; 66 67 enum dscl_autocal_mode { 68 AUTOCAL_MODE_OFF = 0, 69 70 /* Autocal calculate the scaling ratio and initial phase and the 71 * DSCL_MODE_SEL must be set to 1 72 */ 73 AUTOCAL_MODE_AUTOSCALE = 1, 74 /* Autocal perform auto centering without replication and the 75 * DSCL_MODE_SEL must be set to 0 76 */ 77 AUTOCAL_MODE_AUTOCENTER = 2, 78 /* Autocal perform auto centering and auto replication and the 79 * DSCL_MODE_SEL must be set to 0 80 */ 81 AUTOCAL_MODE_AUTOREPLICATE = 3 82 }; 83 84 enum dscl_mode_sel { 85 DSCL_MODE_SCALING_444_BYPASS = 0, 86 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 87 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 88 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 89 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 90 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 91 DSCL_MODE_DSCL_BYPASS = 6 92 }; 93 94 enum gamut_remap_select { 95 GAMUT_REMAP_BYPASS = 0, 96 GAMUT_REMAP_COEFF, 97 GAMUT_REMAP_COMA_COEFF, 98 GAMUT_REMAP_COMB_COEFF 99 }; 100 101 void dpp_read_state(struct dpp *dpp_base, 102 struct dcn_dpp_state *s) 103 { 104 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 105 106 REG_GET(CM_IGAM_CONTROL, 107 CM_IGAM_LUT_MODE, &s->igam_lut_mode); 108 REG_GET(CM_IGAM_CONTROL, 109 CM_IGAM_INPUT_FORMAT, &s->igam_input_format); 110 REG_GET(CM_DGAM_CONTROL, 111 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); 112 REG_GET(CM_RGAM_CONTROL, 113 CM_RGAM_LUT_MODE, &s->rgam_lut_mode); 114 REG_GET(CM_GAMUT_REMAP_CONTROL, 115 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); 116 117 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); 118 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); 119 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); 120 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); 121 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); 122 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); 123 } 124 125 /* Program gamut remap in bypass mode */ 126 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) 127 { 128 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, 129 CM_GAMUT_REMAP_MODE, 0); 130 /* Gamut remap in bypass */ 131 } 132 133 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) 134 135 136 bool dpp_get_optimal_number_of_taps( 137 struct dpp *dpp, 138 struct scaler_data *scl_data, 139 const struct scaling_taps *in_taps) 140 { 141 uint32_t pixel_width; 142 143 if (scl_data->viewport.width > scl_data->recout.width) 144 pixel_width = scl_data->recout.width; 145 else 146 pixel_width = scl_data->viewport.width; 147 148 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ 149 if (scl_data->viewport.width != scl_data->h_active && 150 scl_data->viewport.height != scl_data->v_active && 151 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 152 scl_data->format == PIXEL_FORMAT_FP16) 153 return false; 154 155 if (scl_data->viewport.width > scl_data->h_active && 156 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 157 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 158 return false; 159 160 /* TODO: add lb check */ 161 162 /* No support for programming ratio of 4, drop to 3.99999.. */ 163 if (scl_data->ratios.horz.value == (4ll << 32)) 164 scl_data->ratios.horz.value--; 165 if (scl_data->ratios.vert.value == (4ll << 32)) 166 scl_data->ratios.vert.value--; 167 if (scl_data->ratios.horz_c.value == (4ll << 32)) 168 scl_data->ratios.horz_c.value--; 169 if (scl_data->ratios.vert_c.value == (4ll << 32)) 170 scl_data->ratios.vert_c.value--; 171 172 /* Set default taps if none are provided */ 173 if (in_taps->h_taps == 0) 174 scl_data->taps.h_taps = 4; 175 else 176 scl_data->taps.h_taps = in_taps->h_taps; 177 if (in_taps->v_taps == 0) 178 scl_data->taps.v_taps = 4; 179 else 180 scl_data->taps.v_taps = in_taps->v_taps; 181 if (in_taps->v_taps_c == 0) 182 scl_data->taps.v_taps_c = 2; 183 else 184 scl_data->taps.v_taps_c = in_taps->v_taps_c; 185 if (in_taps->h_taps_c == 0) 186 scl_data->taps.h_taps_c = 2; 187 /* Only 1 and even h_taps_c are supported by hw */ 188 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 189 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 190 else 191 scl_data->taps.h_taps_c = in_taps->h_taps_c; 192 193 if (!dpp->ctx->dc->debug.always_scale) { 194 if (IDENTITY_RATIO(scl_data->ratios.horz)) 195 scl_data->taps.h_taps = 1; 196 if (IDENTITY_RATIO(scl_data->ratios.vert)) 197 scl_data->taps.v_taps = 1; 198 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 199 scl_data->taps.h_taps_c = 1; 200 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 201 scl_data->taps.v_taps_c = 1; 202 } 203 204 return true; 205 } 206 207 void dpp_reset(struct dpp *dpp_base) 208 { 209 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 210 211 dpp->filter_h_c = NULL; 212 dpp->filter_v_c = NULL; 213 dpp->filter_h = NULL; 214 dpp->filter_v = NULL; 215 216 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); 217 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); 218 } 219 220 221 222 static void dpp1_cm_set_regamma_pwl( 223 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) 224 { 225 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 226 uint32_t re_mode = 0; 227 228 switch (mode) { 229 case OPP_REGAMMA_BYPASS: 230 re_mode = 0; 231 break; 232 case OPP_REGAMMA_SRGB: 233 re_mode = 1; 234 break; 235 case OPP_REGAMMA_XVYCC: 236 re_mode = 2; 237 break; 238 case OPP_REGAMMA_USER: 239 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; 240 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) 241 break; 242 243 dpp1_cm_power_on_regamma_lut(dpp_base, true); 244 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); 245 246 if (dpp->is_write_to_ram_a_safe) 247 dpp1_cm_program_regamma_luta_settings(dpp_base, params); 248 else 249 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); 250 251 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, 252 params->hw_points_num); 253 dpp->pwl_data = *params; 254 255 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; 256 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; 257 break; 258 default: 259 break; 260 } 261 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); 262 } 263 264 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ 265 enum pixel_format_description *fmt) 266 { 267 268 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || 269 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) 270 *fmt = PIXEL_FORMAT_FLOAT; 271 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) 272 *fmt = PIXEL_FORMAT_FIXED16; 273 else 274 *fmt = PIXEL_FORMAT_FIXED; 275 } 276 277 static void dpp1_set_degamma_format_float( 278 struct dpp *dpp_base, 279 bool is_float) 280 { 281 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 282 283 if (is_float) { 284 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); 285 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); 286 } else { 287 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); 288 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); 289 } 290 } 291 292 void dpp1_cnv_setup ( 293 struct dpp *dpp_base, 294 enum surface_pixel_format format, 295 enum expansion_mode mode, 296 struct dc_csc_transform input_csc_color_matrix, 297 enum dc_color_space input_color_space) 298 { 299 uint32_t pixel_format; 300 uint32_t alpha_en; 301 enum pixel_format_description fmt ; 302 enum dc_color_space color_space; 303 enum dcn10_input_csc_select select; 304 bool is_float; 305 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 306 bool force_disable_cursor = false; 307 struct out_csc_color_matrix tbl_entry; 308 int i = 0; 309 310 dpp1_setup_format_flags(format, &fmt); 311 alpha_en = 1; 312 pixel_format = 0; 313 color_space = COLOR_SPACE_SRGB; 314 select = INPUT_CSC_SELECT_BYPASS; 315 is_float = false; 316 317 switch (fmt) { 318 case PIXEL_FORMAT_FIXED: 319 case PIXEL_FORMAT_FIXED16: 320 /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ 321 REG_SET_3(FORMAT_CONTROL, 0, 322 CNVC_BYPASS, 0, 323 FORMAT_EXPANSION_MODE, mode, 324 OUTPUT_FP, 0); 325 break; 326 case PIXEL_FORMAT_FLOAT: 327 REG_SET_3(FORMAT_CONTROL, 0, 328 CNVC_BYPASS, 0, 329 FORMAT_EXPANSION_MODE, mode, 330 OUTPUT_FP, 1); 331 is_float = true; 332 break; 333 default: 334 335 break; 336 } 337 338 dpp1_set_degamma_format_float(dpp_base, is_float); 339 340 switch (format) { 341 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 342 pixel_format = 1; 343 break; 344 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 345 pixel_format = 3; 346 alpha_en = 0; 347 break; 348 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 349 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 350 pixel_format = 8; 351 break; 352 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 353 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 354 pixel_format = 10; 355 break; 356 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 357 force_disable_cursor = false; 358 pixel_format = 65; 359 color_space = COLOR_SPACE_YCBCR709; 360 select = INPUT_CSC_SELECT_ICSC; 361 break; 362 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 363 force_disable_cursor = true; 364 pixel_format = 64; 365 color_space = COLOR_SPACE_YCBCR709; 366 select = INPUT_CSC_SELECT_ICSC; 367 break; 368 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 369 force_disable_cursor = true; 370 pixel_format = 67; 371 color_space = COLOR_SPACE_YCBCR709; 372 select = INPUT_CSC_SELECT_ICSC; 373 break; 374 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 375 force_disable_cursor = true; 376 pixel_format = 66; 377 color_space = COLOR_SPACE_YCBCR709; 378 select = INPUT_CSC_SELECT_ICSC; 379 break; 380 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 381 pixel_format = 22; 382 break; 383 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 384 pixel_format = 24; 385 break; 386 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 387 pixel_format = 25; 388 break; 389 default: 390 break; 391 } 392 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, 393 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); 394 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 395 396 // if input adjustments exist, program icsc with those values 397 398 if (input_csc_color_matrix.enable_adjustment 399 == true) { 400 for (i = 0; i < 12; i++) 401 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 402 403 tbl_entry.color_space = input_color_space; 404 405 if (color_space >= COLOR_SPACE_YCBCR601) 406 select = INPUT_CSC_SELECT_ICSC; 407 else 408 select = INPUT_CSC_SELECT_BYPASS; 409 410 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); 411 } else 412 dpp1_program_input_csc(dpp_base, color_space, select, NULL); 413 414 if (force_disable_cursor) { 415 REG_UPDATE(CURSOR_CONTROL, 416 CURSOR_ENABLE, 0); 417 REG_UPDATE(CURSOR0_CONTROL, 418 CUR0_ENABLE, 0); 419 } 420 } 421 422 void dpp1_set_cursor_attributes( 423 struct dpp *dpp_base, 424 enum dc_cursor_color_format color_format) 425 { 426 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 427 428 REG_UPDATE_2(CURSOR0_CONTROL, 429 CUR0_MODE, color_format, 430 CUR0_EXPANSION_MODE, 0); 431 432 if (color_format == CURSOR_MODE_MONO) { 433 /* todo: clarify what to program these to */ 434 REG_UPDATE(CURSOR0_COLOR0, 435 CUR0_COLOR0, 0x00000000); 436 REG_UPDATE(CURSOR0_COLOR1, 437 CUR0_COLOR1, 0xFFFFFFFF); 438 } 439 } 440 441 442 void dpp1_set_cursor_position( 443 struct dpp *dpp_base, 444 const struct dc_cursor_position *pos, 445 const struct dc_cursor_mi_param *param, 446 uint32_t width) 447 { 448 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 449 int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start; 450 uint32_t cur_en = pos->enable ? 1 : 0; 451 452 if (src_x_offset >= (int)param->viewport_width) 453 cur_en = 0; /* not visible beyond right edge*/ 454 455 if (src_x_offset + (int)width <= 0) 456 cur_en = 0; /* not visible beyond left edge*/ 457 458 REG_UPDATE(CURSOR0_CONTROL, 459 CUR0_ENABLE, cur_en); 460 461 } 462 463 void dpp1_dppclk_control( 464 struct dpp *dpp_base, 465 bool dppclk_div, 466 bool enable) 467 { 468 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 469 470 if (enable) { 471 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) 472 REG_UPDATE_2(DPP_CONTROL, 473 DPPCLK_RATE_CONTROL, dppclk_div, 474 DPP_CLOCK_ENABLE, 1); 475 else 476 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); 477 } else 478 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); 479 } 480 481 static const struct dpp_funcs dcn10_dpp_funcs = { 482 .dpp_read_state = dpp_read_state, 483 .dpp_reset = dpp_reset, 484 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 485 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, 486 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, 487 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, 488 .dpp_set_csc_default = dpp1_cm_set_output_csc_default, 489 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, 490 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, 491 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, 492 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, 493 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, 494 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, 495 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, 496 .dpp_set_degamma = dpp1_set_degamma, 497 .dpp_program_input_lut = dpp1_program_input_lut, 498 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, 499 .dpp_setup = dpp1_cnv_setup, 500 .dpp_full_bypass = dpp1_full_bypass, 501 .set_cursor_attributes = dpp1_set_cursor_attributes, 502 .set_cursor_position = dpp1_set_cursor_position, 503 .dpp_dppclk_control = dpp1_dppclk_control, 504 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, 505 }; 506 507 static struct dpp_caps dcn10_dpp_cap = { 508 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT, 509 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions, 510 }; 511 512 /*****************************************/ 513 /* Constructor, Destructor */ 514 /*****************************************/ 515 516 void dpp1_construct( 517 struct dcn10_dpp *dpp, 518 struct dc_context *ctx, 519 uint32_t inst, 520 const struct dcn_dpp_registers *tf_regs, 521 const struct dcn_dpp_shift *tf_shift, 522 const struct dcn_dpp_mask *tf_mask) 523 { 524 dpp->base.ctx = ctx; 525 526 dpp->base.inst = inst; 527 dpp->base.funcs = &dcn10_dpp_funcs; 528 dpp->base.caps = &dcn10_dpp_cap; 529 530 dpp->tf_regs = tf_regs; 531 dpp->tf_shift = tf_shift; 532 dpp->tf_mask = tf_mask; 533 534 dpp->lb_pixel_depth_supported = 535 LB_PIXEL_DEPTH_18BPP | 536 LB_PIXEL_DEPTH_24BPP | 537 LB_PIXEL_DEPTH_30BPP; 538 539 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 540 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 541 } 542