14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #include "dm_services.h" 274562236bSHarry Wentland 284562236bSHarry Wentland /* include DCE8 register header files */ 294562236bSHarry Wentland #include "dce/dce_8_0_d.h" 304562236bSHarry Wentland #include "dce/dce_8_0_sh_mask.h" 314562236bSHarry Wentland 324562236bSHarry Wentland #include "dc_types.h" 334562236bSHarry Wentland 344562236bSHarry Wentland #include "include/grph_object_id.h" 354562236bSHarry Wentland #include "include/logger_interface.h" 364562236bSHarry Wentland #include "../dce110/dce110_timing_generator.h" 374562236bSHarry Wentland #include "dce80_timing_generator.h" 384562236bSHarry Wentland 394562236bSHarry Wentland #include "timing_generator.h" 404562236bSHarry Wentland 414562236bSHarry Wentland enum black_color_format { 424562236bSHarry Wentland BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */ 434562236bSHarry Wentland BLACK_COLOR_FORMAT_RGB_LIMITED, 444562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_TV, 454562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_CV, 464562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_SUPER_AA, 474562236bSHarry Wentland 484562236bSHarry Wentland BLACK_COLOR_FORMAT_COUNT 494562236bSHarry Wentland }; 504562236bSHarry Wentland 514562236bSHarry Wentland static const struct dce110_timing_generator_offsets reg_offsets[] = { 524562236bSHarry Wentland { 534562236bSHarry Wentland .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 544562236bSHarry Wentland .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 554562236bSHarry Wentland }, 564562236bSHarry Wentland { 574562236bSHarry Wentland .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 584562236bSHarry Wentland .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 594562236bSHarry Wentland }, 604562236bSHarry Wentland { 614562236bSHarry Wentland .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 624562236bSHarry Wentland .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 634562236bSHarry Wentland }, 644562236bSHarry Wentland { 654562236bSHarry Wentland .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 664562236bSHarry Wentland .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 674562236bSHarry Wentland }, 684562236bSHarry Wentland { 694562236bSHarry Wentland .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 704562236bSHarry Wentland .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 714562236bSHarry Wentland }, 724562236bSHarry Wentland { 734562236bSHarry Wentland .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 744562236bSHarry Wentland .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 754562236bSHarry Wentland } 764562236bSHarry Wentland }; 774562236bSHarry Wentland 784562236bSHarry Wentland #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10 794562236bSHarry Wentland 804562236bSHarry Wentland #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1) 814562236bSHarry Wentland #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1) 824562236bSHarry Wentland 834562236bSHarry Wentland #define CRTC_REG(reg) (reg + tg110->offsets.crtc) 844562236bSHarry Wentland #define DCP_REG(reg) (reg + tg110->offsets.dcp) 854562236bSHarry Wentland #define DMIF_REG(reg) (reg + tg110->offsets.dmif) 864562236bSHarry Wentland 87380604e2SKen Chalmers static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) 884562236bSHarry Wentland { 894562236bSHarry Wentland uint64_t pix_dur; 904562236bSHarry Wentland uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 914562236bSHarry Wentland + DCE110TG_FROM_TG(tg)->offsets.dmif; 924562236bSHarry Wentland uint32_t value = dm_read_reg(tg->ctx, addr); 934562236bSHarry Wentland 94380604e2SKen Chalmers if (pix_clk_100hz == 0) 954562236bSHarry Wentland return; 964562236bSHarry Wentland 9732e61361SKen Chalmers pix_dur = div_u64(10000000000ull, pix_clk_100hz); 984562236bSHarry Wentland 994562236bSHarry Wentland set_reg_field_value( 1004562236bSHarry Wentland value, 1014562236bSHarry Wentland pix_dur, 1024562236bSHarry Wentland DPG_PIPE_ARBITRATION_CONTROL1, 1034562236bSHarry Wentland PIXEL_DURATION); 1044562236bSHarry Wentland 1054562236bSHarry Wentland dm_write_reg(tg->ctx, addr, value); 1064562236bSHarry Wentland } 1074562236bSHarry Wentland 1084562236bSHarry Wentland static void program_timing(struct timing_generator *tg, 1094562236bSHarry Wentland const struct dc_crtc_timing *timing, 110e7e10c46SDmytro Laktyushkin int vready_offset, 111e7e10c46SDmytro Laktyushkin int vstartup_start, 112e7e10c46SDmytro Laktyushkin int vupdate_offset, 113e7e10c46SDmytro Laktyushkin int vupdate_width, 114e7e10c46SDmytro Laktyushkin const enum signal_type signal, 1154562236bSHarry Wentland bool use_vbios) 1164562236bSHarry Wentland { 1174562236bSHarry Wentland if (!use_vbios) 118380604e2SKen Chalmers program_pix_dur(tg, timing->pix_clk_100hz); 1194562236bSHarry Wentland 120e7e10c46SDmytro Laktyushkin dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); 1214562236bSHarry Wentland } 1224562236bSHarry Wentland 1233a97f3ffSHarry Wentland static void dce80_timing_generator_enable_advanced_request( 1243a97f3ffSHarry Wentland struct timing_generator *tg, 1253a97f3ffSHarry Wentland bool enable, 1263a97f3ffSHarry Wentland const struct dc_crtc_timing *timing) 1273a97f3ffSHarry Wentland { 1283a97f3ffSHarry Wentland struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); 1293a97f3ffSHarry Wentland uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); 1303a97f3ffSHarry Wentland uint32_t value = dm_read_reg(tg->ctx, addr); 1313a97f3ffSHarry Wentland 1323a97f3ffSHarry Wentland if (enable) { 1333a97f3ffSHarry Wentland set_reg_field_value( 1343a97f3ffSHarry Wentland value, 1353a97f3ffSHarry Wentland 0, 1363a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1373a97f3ffSHarry Wentland CRTC_LEGACY_REQUESTOR_EN); 1383a97f3ffSHarry Wentland } else { 1393a97f3ffSHarry Wentland set_reg_field_value( 1403a97f3ffSHarry Wentland value, 1413a97f3ffSHarry Wentland 1, 1423a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1433a97f3ffSHarry Wentland CRTC_LEGACY_REQUESTOR_EN); 1443a97f3ffSHarry Wentland } 1453a97f3ffSHarry Wentland 1463a97f3ffSHarry Wentland if ((timing->v_sync_width + timing->v_front_porch) <= 3) { 1473a97f3ffSHarry Wentland set_reg_field_value( 1483a97f3ffSHarry Wentland value, 1493a97f3ffSHarry Wentland 3, 1503a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1513a97f3ffSHarry Wentland CRTC_ADVANCED_START_LINE_POSITION); 1523a97f3ffSHarry Wentland set_reg_field_value( 1533a97f3ffSHarry Wentland value, 1543a97f3ffSHarry Wentland 0, 1553a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1563a97f3ffSHarry Wentland CRTC_PREFETCH_EN); 1573a97f3ffSHarry Wentland } else { 1583a97f3ffSHarry Wentland set_reg_field_value( 1593a97f3ffSHarry Wentland value, 1603a97f3ffSHarry Wentland 4, 1613a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1623a97f3ffSHarry Wentland CRTC_ADVANCED_START_LINE_POSITION); 1633a97f3ffSHarry Wentland set_reg_field_value( 1643a97f3ffSHarry Wentland value, 1653a97f3ffSHarry Wentland 1, 1663a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1673a97f3ffSHarry Wentland CRTC_PREFETCH_EN); 1683a97f3ffSHarry Wentland } 1693a97f3ffSHarry Wentland 1703a97f3ffSHarry Wentland set_reg_field_value( 1713a97f3ffSHarry Wentland value, 1723a97f3ffSHarry Wentland 1, 1733a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1743a97f3ffSHarry Wentland CRTC_PROGRESSIVE_START_LINE_EARLY); 1753a97f3ffSHarry Wentland 1763a97f3ffSHarry Wentland set_reg_field_value( 1773a97f3ffSHarry Wentland value, 1783a97f3ffSHarry Wentland 1, 1793a97f3ffSHarry Wentland CRTC_START_LINE_CONTROL, 1803a97f3ffSHarry Wentland CRTC_INTERLACE_START_LINE_EARLY); 1813a97f3ffSHarry Wentland 1823a97f3ffSHarry Wentland dm_write_reg(tg->ctx, addr, value); 1833a97f3ffSHarry Wentland } 1843a97f3ffSHarry Wentland 1854562236bSHarry Wentland static const struct timing_generator_funcs dce80_tg_funcs = { 1864562236bSHarry Wentland .validate_timing = dce110_tg_validate_timing, 1874562236bSHarry Wentland .program_timing = program_timing, 1884562236bSHarry Wentland .enable_crtc = dce110_timing_generator_enable_crtc, 1894562236bSHarry Wentland .disable_crtc = dce110_timing_generator_disable_crtc, 1904562236bSHarry Wentland .is_counter_moving = dce110_timing_generator_is_counter_moving, 19172ada5f7SEric Cook .get_position = dce110_timing_generator_get_position, 1924562236bSHarry Wentland .get_frame_count = dce110_timing_generator_get_vblank_counter, 1934562236bSHarry Wentland .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, 1944562236bSHarry Wentland .set_early_control = dce110_timing_generator_set_early_control, 1954562236bSHarry Wentland .wait_for_state = dce110_tg_wait_for_state, 1964562236bSHarry Wentland .set_blank = dce110_tg_set_blank, 1974562236bSHarry Wentland .is_blanked = dce110_tg_is_blanked, 1984562236bSHarry Wentland .set_colors = dce110_tg_set_colors, 1994562236bSHarry Wentland .set_overscan_blank_color = 2004562236bSHarry Wentland dce110_timing_generator_set_overscan_color_black, 2014562236bSHarry Wentland .set_blank_color = dce110_timing_generator_program_blank_color, 2024562236bSHarry Wentland .disable_vga = dce110_timing_generator_disable_vga, 2034562236bSHarry Wentland .did_triggered_reset_occur = 2044562236bSHarry Wentland dce110_timing_generator_did_triggered_reset_occur, 2054562236bSHarry Wentland .setup_global_swap_lock = 2064562236bSHarry Wentland dce110_timing_generator_setup_global_swap_lock, 2074562236bSHarry Wentland .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, 2084562236bSHarry Wentland .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, 2094562236bSHarry Wentland .tear_down_global_swap_lock = 2104562236bSHarry Wentland dce110_timing_generator_tear_down_global_swap_lock, 21126ada804SJordan Lazare .set_drr = dce110_timing_generator_set_drr, 21226ada804SJordan Lazare .set_static_screen_control = 21326ada804SJordan Lazare dce110_timing_generator_set_static_screen_control, 21426ada804SJordan Lazare .set_test_pattern = dce110_timing_generator_set_test_pattern, 215667e1498SAndrey Grodzovsky .arm_vert_intr = dce110_arm_vert_intr, 2164562236bSHarry Wentland 2174562236bSHarry Wentland /* DCE8.0 overrides */ 2184562236bSHarry Wentland .enable_advanced_request = 2194562236bSHarry Wentland dce80_timing_generator_enable_advanced_request, 220ea41fb64SLeo (Sunpeng) Li .configure_crc = dce110_configure_crc, 221ea41fb64SLeo (Sunpeng) Li .get_crc = dce110_get_crc, 2224562236bSHarry Wentland }; 2234562236bSHarry Wentland 22499913a17SDave Airlie void dce80_timing_generator_construct( 2254562236bSHarry Wentland struct dce110_timing_generator *tg110, 2264562236bSHarry Wentland struct dc_context *ctx, 2274562236bSHarry Wentland uint32_t instance, 2284562236bSHarry Wentland const struct dce110_timing_generator_offsets *offsets) 2294562236bSHarry Wentland { 2304562236bSHarry Wentland tg110->controller_id = CONTROLLER_ID_D0 + instance; 2314562236bSHarry Wentland tg110->base.inst = instance; 2324562236bSHarry Wentland tg110->offsets = *offsets; 2334562236bSHarry Wentland tg110->derived_offsets = reg_offsets[instance]; 2344562236bSHarry Wentland 2354562236bSHarry Wentland tg110->base.funcs = &dce80_tg_funcs; 2364562236bSHarry Wentland 2374562236bSHarry Wentland tg110->base.ctx = ctx; 2384562236bSHarry Wentland tg110->base.bp = ctx->dc_bios; 2394562236bSHarry Wentland 2404562236bSHarry Wentland tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; 2414562236bSHarry Wentland tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; 2424562236bSHarry Wentland 2434562236bSHarry Wentland tg110->min_h_blank = 56; 2444562236bSHarry Wentland tg110->min_h_front_porch = 4; 2454562236bSHarry Wentland tg110->min_h_back_porch = 4; 2464562236bSHarry Wentland } 2474562236bSHarry Wentland 248