14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #include "dm_services.h" 274562236bSHarry Wentland 284562236bSHarry Wentland /* include DCE8 register header files */ 294562236bSHarry Wentland #include "dce/dce_8_0_d.h" 304562236bSHarry Wentland #include "dce/dce_8_0_sh_mask.h" 314562236bSHarry Wentland 324562236bSHarry Wentland #include "dc_types.h" 334562236bSHarry Wentland 344562236bSHarry Wentland #include "include/grph_object_id.h" 354562236bSHarry Wentland #include "include/logger_interface.h" 364562236bSHarry Wentland #include "../dce110/dce110_timing_generator.h" 374562236bSHarry Wentland #include "dce80_timing_generator.h" 384562236bSHarry Wentland 394562236bSHarry Wentland #include "timing_generator.h" 404562236bSHarry Wentland 414562236bSHarry Wentland enum black_color_format { 424562236bSHarry Wentland BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */ 434562236bSHarry Wentland BLACK_COLOR_FORMAT_RGB_LIMITED, 444562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_TV, 454562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_CV, 464562236bSHarry Wentland BLACK_COLOR_FORMAT_YUV_SUPER_AA, 474562236bSHarry Wentland 484562236bSHarry Wentland BLACK_COLOR_FORMAT_COUNT 494562236bSHarry Wentland }; 504562236bSHarry Wentland 514562236bSHarry Wentland static const struct dce110_timing_generator_offsets reg_offsets[] = { 524562236bSHarry Wentland { 534562236bSHarry Wentland .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 544562236bSHarry Wentland .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 554562236bSHarry Wentland }, 564562236bSHarry Wentland { 574562236bSHarry Wentland .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 584562236bSHarry Wentland .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 594562236bSHarry Wentland }, 604562236bSHarry Wentland { 614562236bSHarry Wentland .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 624562236bSHarry Wentland .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 634562236bSHarry Wentland }, 644562236bSHarry Wentland { 654562236bSHarry Wentland .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 664562236bSHarry Wentland .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 674562236bSHarry Wentland }, 684562236bSHarry Wentland { 694562236bSHarry Wentland .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 704562236bSHarry Wentland .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 714562236bSHarry Wentland }, 724562236bSHarry Wentland { 734562236bSHarry Wentland .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL), 744562236bSHarry Wentland .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 754562236bSHarry Wentland } 764562236bSHarry Wentland }; 774562236bSHarry Wentland 784562236bSHarry Wentland #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10 794562236bSHarry Wentland 804562236bSHarry Wentland #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1) 814562236bSHarry Wentland #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1) 824562236bSHarry Wentland 834562236bSHarry Wentland #define CRTC_REG(reg) (reg + tg110->offsets.crtc) 844562236bSHarry Wentland #define DCP_REG(reg) (reg + tg110->offsets.dcp) 854562236bSHarry Wentland #define DMIF_REG(reg) (reg + tg110->offsets.dmif) 864562236bSHarry Wentland 874562236bSHarry Wentland void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz) 884562236bSHarry Wentland { 894562236bSHarry Wentland uint64_t pix_dur; 904562236bSHarry Wentland uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 914562236bSHarry Wentland + DCE110TG_FROM_TG(tg)->offsets.dmif; 924562236bSHarry Wentland uint32_t value = dm_read_reg(tg->ctx, addr); 934562236bSHarry Wentland 944562236bSHarry Wentland if (pix_clk_khz == 0) 954562236bSHarry Wentland return; 964562236bSHarry Wentland 974562236bSHarry Wentland pix_dur = 1000000000 / pix_clk_khz; 984562236bSHarry Wentland 994562236bSHarry Wentland set_reg_field_value( 1004562236bSHarry Wentland value, 1014562236bSHarry Wentland pix_dur, 1024562236bSHarry Wentland DPG_PIPE_ARBITRATION_CONTROL1, 1034562236bSHarry Wentland PIXEL_DURATION); 1044562236bSHarry Wentland 1054562236bSHarry Wentland dm_write_reg(tg->ctx, addr, value); 1064562236bSHarry Wentland } 1074562236bSHarry Wentland 1084562236bSHarry Wentland static void program_timing(struct timing_generator *tg, 1094562236bSHarry Wentland const struct dc_crtc_timing *timing, 1104562236bSHarry Wentland bool use_vbios) 1114562236bSHarry Wentland { 1124562236bSHarry Wentland if (!use_vbios) 1134562236bSHarry Wentland program_pix_dur(tg, timing->pix_clk_khz); 1144562236bSHarry Wentland 1154562236bSHarry Wentland dce110_tg_program_timing(tg, timing, use_vbios); 1164562236bSHarry Wentland } 1174562236bSHarry Wentland 1184562236bSHarry Wentland static const struct timing_generator_funcs dce80_tg_funcs = { 1194562236bSHarry Wentland .validate_timing = dce110_tg_validate_timing, 1204562236bSHarry Wentland .program_timing = program_timing, 1214562236bSHarry Wentland .enable_crtc = dce110_timing_generator_enable_crtc, 1224562236bSHarry Wentland .disable_crtc = dce110_timing_generator_disable_crtc, 1234562236bSHarry Wentland .is_counter_moving = dce110_timing_generator_is_counter_moving, 12472ada5f7SEric Cook .get_position = dce110_timing_generator_get_position, 1254562236bSHarry Wentland .get_frame_count = dce110_timing_generator_get_vblank_counter, 1264562236bSHarry Wentland .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, 1274562236bSHarry Wentland .set_early_control = dce110_timing_generator_set_early_control, 1284562236bSHarry Wentland .wait_for_state = dce110_tg_wait_for_state, 1294562236bSHarry Wentland .set_blank = dce110_tg_set_blank, 1304562236bSHarry Wentland .is_blanked = dce110_tg_is_blanked, 1314562236bSHarry Wentland .set_colors = dce110_tg_set_colors, 1324562236bSHarry Wentland .set_overscan_blank_color = 1334562236bSHarry Wentland dce110_timing_generator_set_overscan_color_black, 1344562236bSHarry Wentland .set_blank_color = dce110_timing_generator_program_blank_color, 1354562236bSHarry Wentland .disable_vga = dce110_timing_generator_disable_vga, 1364562236bSHarry Wentland .did_triggered_reset_occur = 1374562236bSHarry Wentland dce110_timing_generator_did_triggered_reset_occur, 1384562236bSHarry Wentland .setup_global_swap_lock = 1394562236bSHarry Wentland dce110_timing_generator_setup_global_swap_lock, 1404562236bSHarry Wentland .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, 1414562236bSHarry Wentland .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, 1424562236bSHarry Wentland .tear_down_global_swap_lock = 1434562236bSHarry Wentland dce110_timing_generator_tear_down_global_swap_lock, 14426ada804SJordan Lazare .set_drr = dce110_timing_generator_set_drr, 14526ada804SJordan Lazare .set_static_screen_control = 14626ada804SJordan Lazare dce110_timing_generator_set_static_screen_control, 14726ada804SJordan Lazare .set_test_pattern = dce110_timing_generator_set_test_pattern, 148667e1498SAndrey Grodzovsky .arm_vert_intr = dce110_arm_vert_intr, 1494562236bSHarry Wentland 1504562236bSHarry Wentland /* DCE8.0 overrides */ 1514562236bSHarry Wentland .enable_advanced_request = 1524562236bSHarry Wentland dce80_timing_generator_enable_advanced_request, 1534562236bSHarry Wentland }; 1544562236bSHarry Wentland 15599913a17SDave Airlie void dce80_timing_generator_construct( 1564562236bSHarry Wentland struct dce110_timing_generator *tg110, 1574562236bSHarry Wentland struct dc_context *ctx, 1584562236bSHarry Wentland uint32_t instance, 1594562236bSHarry Wentland const struct dce110_timing_generator_offsets *offsets) 1604562236bSHarry Wentland { 1614562236bSHarry Wentland tg110->controller_id = CONTROLLER_ID_D0 + instance; 1624562236bSHarry Wentland tg110->base.inst = instance; 1634562236bSHarry Wentland tg110->offsets = *offsets; 1644562236bSHarry Wentland tg110->derived_offsets = reg_offsets[instance]; 1654562236bSHarry Wentland 1664562236bSHarry Wentland tg110->base.funcs = &dce80_tg_funcs; 1674562236bSHarry Wentland 1684562236bSHarry Wentland tg110->base.ctx = ctx; 1694562236bSHarry Wentland tg110->base.bp = ctx->dc_bios; 1704562236bSHarry Wentland 1714562236bSHarry Wentland tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; 1724562236bSHarry Wentland tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; 1734562236bSHarry Wentland 1744562236bSHarry Wentland tg110->min_h_blank = 56; 1754562236bSHarry Wentland tg110->min_h_front_porch = 4; 1764562236bSHarry Wentland tg110->min_h_back_porch = 4; 1774562236bSHarry Wentland } 1784562236bSHarry Wentland 1794562236bSHarry Wentland void dce80_timing_generator_enable_advanced_request( 1804562236bSHarry Wentland struct timing_generator *tg, 1814562236bSHarry Wentland bool enable, 1824562236bSHarry Wentland const struct dc_crtc_timing *timing) 1834562236bSHarry Wentland { 1844562236bSHarry Wentland struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); 1854562236bSHarry Wentland uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); 1864562236bSHarry Wentland uint32_t value = dm_read_reg(tg->ctx, addr); 1874562236bSHarry Wentland 1884562236bSHarry Wentland if (enable) { 1894562236bSHarry Wentland set_reg_field_value( 1904562236bSHarry Wentland value, 1914562236bSHarry Wentland 0, 1924562236bSHarry Wentland CRTC_START_LINE_CONTROL, 1934562236bSHarry Wentland CRTC_LEGACY_REQUESTOR_EN); 1944562236bSHarry Wentland } else { 1954562236bSHarry Wentland set_reg_field_value( 1964562236bSHarry Wentland value, 1974562236bSHarry Wentland 1, 1984562236bSHarry Wentland CRTC_START_LINE_CONTROL, 1994562236bSHarry Wentland CRTC_LEGACY_REQUESTOR_EN); 2004562236bSHarry Wentland } 2014562236bSHarry Wentland 2024562236bSHarry Wentland if ((timing->v_sync_width + timing->v_front_porch) <= 3) { 2034562236bSHarry Wentland set_reg_field_value( 2044562236bSHarry Wentland value, 2054562236bSHarry Wentland 3, 2064562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2074562236bSHarry Wentland CRTC_ADVANCED_START_LINE_POSITION); 2084562236bSHarry Wentland set_reg_field_value( 2094562236bSHarry Wentland value, 2104562236bSHarry Wentland 0, 2114562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2124562236bSHarry Wentland CRTC_PREFETCH_EN); 2134562236bSHarry Wentland } else { 2144562236bSHarry Wentland set_reg_field_value( 2154562236bSHarry Wentland value, 2164562236bSHarry Wentland 4, 2174562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2184562236bSHarry Wentland CRTC_ADVANCED_START_LINE_POSITION); 2194562236bSHarry Wentland set_reg_field_value( 2204562236bSHarry Wentland value, 2214562236bSHarry Wentland 1, 2224562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2234562236bSHarry Wentland CRTC_PREFETCH_EN); 2244562236bSHarry Wentland } 2254562236bSHarry Wentland 2264562236bSHarry Wentland set_reg_field_value( 2274562236bSHarry Wentland value, 2284562236bSHarry Wentland 1, 2294562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2304562236bSHarry Wentland CRTC_PROGRESSIVE_START_LINE_EARLY); 2314562236bSHarry Wentland 2324562236bSHarry Wentland set_reg_field_value( 2334562236bSHarry Wentland value, 2344562236bSHarry Wentland 1, 2354562236bSHarry Wentland CRTC_START_LINE_CONTROL, 2364562236bSHarry Wentland CRTC_INTERLACE_START_LINE_EARLY); 2374562236bSHarry Wentland 2384562236bSHarry Wentland dm_write_reg(tg->ctx, addr, value); 2394562236bSHarry Wentland } 240