1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 /* TODO remove this include */ 57 58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 59 #include "gmc/gmc_7_1_d.h" 60 #include "gmc/gmc_7_1_sh_mask.h" 61 #endif 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 72 #endif 73 74 75 #ifndef mmBIOS_SCRATCH_2 76 #define mmBIOS_SCRATCH_2 0x05CB 77 #define mmBIOS_SCRATCH_6 0x05CF 78 #endif 79 80 #ifndef mmDP_DPHY_FAST_TRAINING 81 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 82 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 83 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 84 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 85 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 86 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 87 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 88 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 89 #endif 90 91 92 #ifndef mmHPD_DC_HPD_CONTROL 93 #define mmHPD_DC_HPD_CONTROL 0x189A 94 #define mmHPD0_DC_HPD_CONTROL 0x189A 95 #define mmHPD1_DC_HPD_CONTROL 0x18A2 96 #define mmHPD2_DC_HPD_CONTROL 0x18AA 97 #define mmHPD3_DC_HPD_CONTROL 0x18B2 98 #define mmHPD4_DC_HPD_CONTROL 0x18BA 99 #define mmHPD5_DC_HPD_CONTROL 0x18C2 100 #endif 101 102 #define DCE11_DIG_FE_CNTL 0x4a00 103 #define DCE11_DIG_BE_CNTL 0x4a47 104 #define DCE11_DP_SEC 0x4ac3 105 106 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 107 { 108 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 109 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 110 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 111 - mmDPG_WATERMARK_MASK_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 115 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 116 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 117 - mmDPG_WATERMARK_MASK_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 122 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 123 - mmDPG_WATERMARK_MASK_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 128 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 129 - mmDPG_WATERMARK_MASK_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 135 - mmDPG_WATERMARK_MASK_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 141 - mmDPG_WATERMARK_MASK_CONTROL), 142 } 143 }; 144 145 /* set register offset */ 146 #define SR(reg_name)\ 147 .reg_name = mm ## reg_name 148 149 /* set register offset with instance */ 150 #define SRI(reg_name, block, id)\ 151 .reg_name = mm ## block ## id ## _ ## reg_name 152 153 154 static const struct dce_disp_clk_registers disp_clk_regs = { 155 CLK_COMMON_REG_LIST_DCE_BASE() 156 }; 157 158 static const struct dce_disp_clk_shift disp_clk_shift = { 159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 160 }; 161 162 static const struct dce_disp_clk_mask disp_clk_mask = { 163 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 164 }; 165 166 #define ipp_regs(id)\ 167 [id] = {\ 168 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 169 } 170 171 static const struct dce_ipp_registers ipp_regs[] = { 172 ipp_regs(0), 173 ipp_regs(1), 174 ipp_regs(2), 175 ipp_regs(3), 176 ipp_regs(4), 177 ipp_regs(5) 178 }; 179 180 static const struct dce_ipp_shift ipp_shift = { 181 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 182 }; 183 184 static const struct dce_ipp_mask ipp_mask = { 185 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 186 }; 187 188 #define transform_regs(id)\ 189 [id] = {\ 190 XFM_COMMON_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_transform_registers xfm_regs[] = { 194 transform_regs(0), 195 transform_regs(1), 196 transform_regs(2), 197 transform_regs(3), 198 transform_regs(4), 199 transform_regs(5) 200 }; 201 202 static const struct dce_transform_shift xfm_shift = { 203 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 204 }; 205 206 static const struct dce_transform_mask xfm_mask = { 207 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 208 }; 209 210 #define aux_regs(id)\ 211 [id] = {\ 212 AUX_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 216 aux_regs(0), 217 aux_regs(1), 218 aux_regs(2), 219 aux_regs(3), 220 aux_regs(4), 221 aux_regs(5) 222 }; 223 224 #define hpd_regs(id)\ 225 [id] = {\ 226 HPD_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 230 hpd_regs(0), 231 hpd_regs(1), 232 hpd_regs(2), 233 hpd_regs(3), 234 hpd_regs(4), 235 hpd_regs(5) 236 }; 237 238 #define link_regs(id)\ 239 [id] = {\ 240 LE_DCE80_REG_LIST(id)\ 241 } 242 243 static const struct dce110_link_enc_registers link_enc_regs[] = { 244 link_regs(0), 245 link_regs(1), 246 link_regs(2), 247 link_regs(3), 248 link_regs(4), 249 link_regs(5), 250 link_regs(6), 251 }; 252 253 #define stream_enc_regs(id)\ 254 [id] = {\ 255 SE_COMMON_REG_LIST_DCE_BASE(id),\ 256 .AFMT_CNTL = 0,\ 257 } 258 259 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 260 stream_enc_regs(0), 261 stream_enc_regs(1), 262 stream_enc_regs(2), 263 stream_enc_regs(3), 264 stream_enc_regs(4), 265 stream_enc_regs(5), 266 stream_enc_regs(6) 267 }; 268 269 static const struct dce_stream_encoder_shift se_shift = { 270 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 271 }; 272 273 static const struct dce_stream_encoder_mask se_mask = { 274 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 275 }; 276 277 #define opp_regs(id)\ 278 [id] = {\ 279 OPP_DCE_80_REG_LIST(id),\ 280 } 281 282 static const struct dce_opp_registers opp_regs[] = { 283 opp_regs(0), 284 opp_regs(1), 285 opp_regs(2), 286 opp_regs(3), 287 opp_regs(4), 288 opp_regs(5) 289 }; 290 291 static const struct dce_opp_shift opp_shift = { 292 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 293 }; 294 295 static const struct dce_opp_mask opp_mask = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 297 }; 298 299 #define audio_regs(id)\ 300 [id] = {\ 301 AUD_COMMON_REG_LIST(id)\ 302 } 303 304 static const struct dce_audio_registers audio_regs[] = { 305 audio_regs(0), 306 audio_regs(1), 307 audio_regs(2), 308 audio_regs(3), 309 audio_regs(4), 310 audio_regs(5), 311 audio_regs(6), 312 }; 313 314 static const struct dce_audio_shift audio_shift = { 315 AUD_COMMON_MASK_SH_LIST(__SHIFT) 316 }; 317 318 static const struct dce_aduio_mask audio_mask = { 319 AUD_COMMON_MASK_SH_LIST(_MASK) 320 }; 321 322 #define clk_src_regs(id)\ 323 [id] = {\ 324 CS_COMMON_REG_LIST_DCE_80(id),\ 325 } 326 327 328 static const struct dce110_clk_src_regs clk_src_regs[] = { 329 clk_src_regs(0), 330 clk_src_regs(1), 331 clk_src_regs(2) 332 }; 333 334 static const struct dce110_clk_src_shift cs_shift = { 335 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 336 }; 337 338 static const struct dce110_clk_src_mask cs_mask = { 339 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 340 }; 341 342 static const struct bios_registers bios_regs = { 343 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 344 }; 345 346 static const struct resource_caps res_cap = { 347 .num_timing_generator = 6, 348 .num_audio = 6, 349 .num_stream_encoder = 6, 350 .num_pll = 3, 351 }; 352 353 static const struct resource_caps res_cap_81 = { 354 .num_timing_generator = 4, 355 .num_audio = 7, 356 .num_stream_encoder = 7, 357 .num_pll = 3, 358 }; 359 360 static const struct resource_caps res_cap_83 = { 361 .num_timing_generator = 2, 362 .num_audio = 6, 363 .num_stream_encoder = 6, 364 .num_pll = 2, 365 }; 366 367 #define CTX ctx 368 #define REG(reg) mm ## reg 369 370 #ifndef mmCC_DC_HDMI_STRAPS 371 #define mmCC_DC_HDMI_STRAPS 0x1918 372 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 373 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 374 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 375 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 376 #endif 377 378 static void read_dce_straps( 379 struct dc_context *ctx, 380 struct resource_straps *straps) 381 { 382 REG_GET_2(CC_DC_HDMI_STRAPS, 383 HDMI_DISABLE, &straps->hdmi_disable, 384 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 385 386 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 387 } 388 389 static struct audio *create_audio( 390 struct dc_context *ctx, unsigned int inst) 391 { 392 return dce_audio_create(ctx, inst, 393 &audio_regs[inst], &audio_shift, &audio_mask); 394 } 395 396 static struct timing_generator *dce80_timing_generator_create( 397 struct dc_context *ctx, 398 uint32_t instance, 399 const struct dce110_timing_generator_offsets *offsets) 400 { 401 struct dce110_timing_generator *tg110 = 402 dm_alloc(sizeof(struct dce110_timing_generator)); 403 404 if (!tg110) 405 return NULL; 406 407 if (dce80_timing_generator_construct(tg110, ctx, instance, offsets)) 408 return &tg110->base; 409 410 BREAK_TO_DEBUGGER(); 411 dm_free(tg110); 412 return NULL; 413 } 414 415 static struct output_pixel_processor *dce80_opp_create( 416 struct dc_context *ctx, 417 uint32_t inst) 418 { 419 struct dce110_opp *opp = 420 dm_alloc(sizeof(struct dce110_opp)); 421 422 if (!opp) 423 return NULL; 424 425 if (dce110_opp_construct(opp, 426 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 427 return &opp->base; 428 429 BREAK_TO_DEBUGGER(); 430 dm_free(opp); 431 return NULL; 432 } 433 434 static struct stream_encoder *dce80_stream_encoder_create( 435 enum engine_id eng_id, 436 struct dc_context *ctx) 437 { 438 struct dce110_stream_encoder *enc110 = 439 dm_alloc(sizeof(struct dce110_stream_encoder)); 440 441 if (!enc110) 442 return NULL; 443 444 if (dce110_stream_encoder_construct( 445 enc110, ctx, ctx->dc_bios, eng_id, 446 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 447 return &enc110->base; 448 449 BREAK_TO_DEBUGGER(); 450 dm_free(enc110); 451 return NULL; 452 } 453 454 #define SRII(reg_name, block, id)\ 455 .reg_name[id] = mm ## block ## id ## _ ## reg_name 456 457 static const struct dce_hwseq_registers hwseq_reg = { 458 HWSEQ_DCE8_REG_LIST() 459 }; 460 461 static const struct dce_hwseq_shift hwseq_shift = { 462 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 463 }; 464 465 static const struct dce_hwseq_mask hwseq_mask = { 466 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 467 }; 468 469 static struct dce_hwseq *dce80_hwseq_create( 470 struct dc_context *ctx) 471 { 472 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); 473 474 if (hws) { 475 hws->ctx = ctx; 476 hws->regs = &hwseq_reg; 477 hws->shifts = &hwseq_shift; 478 hws->masks = &hwseq_mask; 479 } 480 return hws; 481 } 482 483 static const struct resource_create_funcs res_create_funcs = { 484 .read_dce_straps = read_dce_straps, 485 .create_audio = create_audio, 486 .create_stream_encoder = dce80_stream_encoder_create, 487 .create_hwseq = dce80_hwseq_create, 488 }; 489 490 #define mi_inst_regs(id) { \ 491 MI_DCE8_REG_LIST(id), \ 492 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 493 } 494 static const struct dce_mem_input_registers mi_regs[] = { 495 mi_inst_regs(0), 496 mi_inst_regs(1), 497 mi_inst_regs(2), 498 mi_inst_regs(3), 499 mi_inst_regs(4), 500 mi_inst_regs(5), 501 }; 502 503 static const struct dce_mem_input_shift mi_shifts = { 504 MI_DCE8_MASK_SH_LIST(__SHIFT), 505 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 506 }; 507 508 static const struct dce_mem_input_mask mi_masks = { 509 MI_DCE8_MASK_SH_LIST(_MASK), 510 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 511 }; 512 513 static struct mem_input *dce80_mem_input_create( 514 struct dc_context *ctx, 515 uint32_t inst) 516 { 517 struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); 518 519 if (!dce_mi) { 520 BREAK_TO_DEBUGGER(); 521 return NULL; 522 } 523 524 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 525 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 526 return &dce_mi->base; 527 } 528 529 static void dce80_transform_destroy(struct transform **xfm) 530 { 531 dm_free(TO_DCE_TRANSFORM(*xfm)); 532 *xfm = NULL; 533 } 534 535 static struct transform *dce80_transform_create( 536 struct dc_context *ctx, 537 uint32_t inst) 538 { 539 struct dce_transform *transform = 540 dm_alloc(sizeof(struct dce_transform)); 541 542 if (!transform) 543 return NULL; 544 545 if (dce_transform_construct(transform, ctx, inst, 546 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 547 transform->prescaler_on = false; 548 return &transform->base; 549 } 550 551 BREAK_TO_DEBUGGER(); 552 dm_free(transform); 553 return NULL; 554 } 555 556 static const struct encoder_feature_support link_enc_feature = { 557 .max_hdmi_deep_color = COLOR_DEPTH_121212, 558 .max_hdmi_pixel_clock = 297000, 559 .flags.bits.IS_HBR2_CAPABLE = true, 560 .flags.bits.IS_TPS3_CAPABLE = true, 561 .flags.bits.IS_YCBCR_CAPABLE = true 562 }; 563 564 struct link_encoder *dce80_link_encoder_create( 565 const struct encoder_init_data *enc_init_data) 566 { 567 struct dce110_link_encoder *enc110 = 568 dm_alloc(sizeof(struct dce110_link_encoder)); 569 570 if (!enc110) 571 return NULL; 572 573 if (dce110_link_encoder_construct( 574 enc110, 575 enc_init_data, 576 &link_enc_feature, 577 &link_enc_regs[enc_init_data->transmitter], 578 &link_enc_aux_regs[enc_init_data->channel - 1], 579 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 580 581 return &enc110->base; 582 } 583 584 BREAK_TO_DEBUGGER(); 585 dm_free(enc110); 586 return NULL; 587 } 588 589 struct clock_source *dce80_clock_source_create( 590 struct dc_context *ctx, 591 struct dc_bios *bios, 592 enum clock_source_id id, 593 const struct dce110_clk_src_regs *regs, 594 bool dp_clk_src) 595 { 596 struct dce110_clk_src *clk_src = 597 dm_alloc(sizeof(struct dce110_clk_src)); 598 599 if (!clk_src) 600 return NULL; 601 602 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 603 regs, &cs_shift, &cs_mask)) { 604 clk_src->base.dp_clk_src = dp_clk_src; 605 return &clk_src->base; 606 } 607 608 BREAK_TO_DEBUGGER(); 609 return NULL; 610 } 611 612 void dce80_clock_source_destroy(struct clock_source **clk_src) 613 { 614 dm_free(TO_DCE110_CLK_SRC(*clk_src)); 615 *clk_src = NULL; 616 } 617 618 static struct input_pixel_processor *dce80_ipp_create( 619 struct dc_context *ctx, uint32_t inst) 620 { 621 struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); 622 623 if (!ipp) { 624 BREAK_TO_DEBUGGER(); 625 return NULL; 626 } 627 628 dce_ipp_construct(ipp, ctx, inst, 629 &ipp_regs[inst], &ipp_shift, &ipp_mask); 630 return &ipp->base; 631 } 632 633 static void destruct(struct dce110_resource_pool *pool) 634 { 635 unsigned int i; 636 637 for (i = 0; i < pool->base.pipe_count; i++) { 638 if (pool->base.opps[i] != NULL) 639 dce110_opp_destroy(&pool->base.opps[i]); 640 641 if (pool->base.transforms[i] != NULL) 642 dce80_transform_destroy(&pool->base.transforms[i]); 643 644 if (pool->base.ipps[i] != NULL) 645 dce_ipp_destroy(&pool->base.ipps[i]); 646 647 if (pool->base.mis[i] != NULL) { 648 dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); 649 pool->base.mis[i] = NULL; 650 } 651 652 if (pool->base.timing_generators[i] != NULL) { 653 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 654 pool->base.timing_generators[i] = NULL; 655 } 656 } 657 658 for (i = 0; i < pool->base.stream_enc_count; i++) { 659 if (pool->base.stream_enc[i] != NULL) 660 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 661 } 662 663 for (i = 0; i < pool->base.clk_src_count; i++) { 664 if (pool->base.clock_sources[i] != NULL) { 665 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 666 } 667 } 668 669 if (pool->base.dp_clock_source != NULL) 670 dce80_clock_source_destroy(&pool->base.dp_clock_source); 671 672 for (i = 0; i < pool->base.audio_count; i++) { 673 if (pool->base.audios[i] != NULL) { 674 dce_aud_destroy(&pool->base.audios[i]); 675 } 676 } 677 678 if (pool->base.display_clock != NULL) 679 dce_disp_clk_destroy(&pool->base.display_clock); 680 681 if (pool->base.irqs != NULL) { 682 dal_irq_service_destroy(&pool->base.irqs); 683 } 684 } 685 686 static enum dc_status build_mapped_resource( 687 const struct dc *dc, 688 struct validate_context *context, 689 struct validate_context *old_context) 690 { 691 enum dc_status status = DC_OK; 692 uint8_t i, j; 693 694 for (i = 0; i < context->stream_count; i++) { 695 struct dc_stream_state *stream = context->streams[i]; 696 697 if (old_context && resource_is_stream_unchanged(old_context, stream)) 698 continue; 699 700 for (j = 0; j < MAX_PIPES; j++) { 701 struct pipe_ctx *pipe_ctx = 702 &context->res_ctx.pipe_ctx[j]; 703 704 if (context->res_ctx.pipe_ctx[j].stream != stream) 705 continue; 706 707 status = dce110_resource_build_pipe_hw_param(pipe_ctx); 708 709 if (status != DC_OK) 710 return status; 711 712 resource_build_info_frame(pipe_ctx); 713 714 /* do not need to validate non root pipes */ 715 break; 716 } 717 } 718 719 return DC_OK; 720 } 721 722 bool dce80_validate_bandwidth( 723 struct dc *dc, 724 struct validate_context *context) 725 { 726 /* TODO implement when needed but for now hardcode max value*/ 727 context->bw.dce.dispclk_khz = 681000; 728 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 729 730 return true; 731 } 732 733 static bool dce80_validate_surface_sets( 734 const struct dc_validation_set set[], 735 int set_count) 736 { 737 int i; 738 739 for (i = 0; i < set_count; i++) { 740 if (set[i].plane_count == 0) 741 continue; 742 743 if (set[i].plane_count > 1) 744 return false; 745 746 if (set[i].plane_states[0]->format 747 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 748 return false; 749 } 750 751 return true; 752 } 753 754 enum dc_status dce80_validate_with_context( 755 struct dc *dc, 756 const struct dc_validation_set set[], 757 int set_count, 758 struct validate_context *context, 759 struct validate_context *old_context) 760 { 761 struct dc_context *dc_ctx = dc->ctx; 762 enum dc_status result = DC_ERROR_UNEXPECTED; 763 int i; 764 765 if (!dce80_validate_surface_sets(set, set_count)) 766 return DC_FAIL_SURFACE_VALIDATE; 767 768 for (i = 0; i < set_count; i++) { 769 context->streams[i] = set[i].stream; 770 dc_stream_retain(context->streams[i]); 771 context->stream_count++; 772 } 773 774 result = resource_map_pool_resources(dc, context, old_context); 775 776 if (result == DC_OK) 777 result = resource_map_clock_resources(dc, context, old_context); 778 779 if (!resource_validate_attach_surfaces(set, set_count, 780 old_context, context, dc->res_pool)) { 781 DC_ERROR("Failed to attach surface to stream!\n"); 782 return DC_FAIL_ATTACH_SURFACES; 783 } 784 785 if (result == DC_OK) 786 result = build_mapped_resource(dc, context, old_context); 787 788 if (result == DC_OK) 789 result = resource_build_scaling_params_for_context(dc, context); 790 791 if (result == DC_OK) 792 result = dce80_validate_bandwidth(dc, context); 793 794 return result; 795 } 796 797 enum dc_status dce80_validate_guaranteed( 798 struct dc *dc, 799 struct dc_stream_state *dc_stream, 800 struct validate_context *context) 801 { 802 enum dc_status result = DC_ERROR_UNEXPECTED; 803 804 context->streams[0] = dc_stream; 805 dc_stream_retain(context->streams[0]); 806 context->stream_count++; 807 808 result = resource_map_pool_resources(dc, context, NULL); 809 810 if (result == DC_OK) 811 result = resource_map_clock_resources(dc, context, NULL); 812 813 if (result == DC_OK) 814 result = build_mapped_resource(dc, context, NULL); 815 816 if (result == DC_OK) { 817 validate_guaranteed_copy_streams( 818 context, dc->caps.max_streams); 819 result = resource_build_scaling_params_for_context(dc, context); 820 } 821 822 if (result == DC_OK) 823 result = dce80_validate_bandwidth(dc, context); 824 825 return result; 826 } 827 828 static void dce80_destroy_resource_pool(struct resource_pool **pool) 829 { 830 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 831 832 destruct(dce110_pool); 833 dm_free(dce110_pool); 834 *pool = NULL; 835 } 836 837 static const struct resource_funcs dce80_res_pool_funcs = { 838 .destroy = dce80_destroy_resource_pool, 839 .link_enc_create = dce80_link_encoder_create, 840 .validate_with_context = dce80_validate_with_context, 841 .validate_guaranteed = dce80_validate_guaranteed, 842 .validate_bandwidth = dce80_validate_bandwidth, 843 .validate_plane = dce100_validate_plane 844 }; 845 846 static bool dce80_construct( 847 uint8_t num_virtual_links, 848 struct dc *dc, 849 struct dce110_resource_pool *pool) 850 { 851 unsigned int i; 852 struct dc_context *ctx = dc->ctx; 853 struct dc_firmware_info info; 854 struct dc_bios *bp; 855 struct dm_pp_static_clock_info static_clk_info = {0}; 856 857 ctx->dc_bios->regs = &bios_regs; 858 859 pool->base.res_cap = &res_cap; 860 pool->base.funcs = &dce80_res_pool_funcs; 861 862 863 /************************************************* 864 * Resource + asic cap harcoding * 865 *************************************************/ 866 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 867 pool->base.pipe_count = res_cap.num_timing_generator; 868 dc->caps.max_downscale_ratio = 200; 869 dc->caps.i2c_speed_in_khz = 40; 870 dc->caps.max_cursor_size = 128; 871 872 /************************************************* 873 * Create resources * 874 *************************************************/ 875 876 bp = ctx->dc_bios; 877 878 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 879 info.external_clock_source_frequency_for_dp != 0) { 880 pool->base.dp_clock_source = 881 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 882 883 pool->base.clock_sources[0] = 884 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 885 pool->base.clock_sources[1] = 886 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 887 pool->base.clock_sources[2] = 888 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 889 pool->base.clk_src_count = 3; 890 891 } else { 892 pool->base.dp_clock_source = 893 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 894 895 pool->base.clock_sources[0] = 896 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 897 pool->base.clock_sources[1] = 898 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 899 pool->base.clk_src_count = 2; 900 } 901 902 if (pool->base.dp_clock_source == NULL) { 903 dm_error("DC: failed to create dp clock source!\n"); 904 BREAK_TO_DEBUGGER(); 905 goto res_create_fail; 906 } 907 908 for (i = 0; i < pool->base.clk_src_count; i++) { 909 if (pool->base.clock_sources[i] == NULL) { 910 dm_error("DC: failed to create clock sources!\n"); 911 BREAK_TO_DEBUGGER(); 912 goto res_create_fail; 913 } 914 } 915 916 pool->base.display_clock = dce_disp_clk_create(ctx, 917 &disp_clk_regs, 918 &disp_clk_shift, 919 &disp_clk_mask); 920 if (pool->base.display_clock == NULL) { 921 dm_error("DC: failed to create display clock!\n"); 922 BREAK_TO_DEBUGGER(); 923 goto res_create_fail; 924 } 925 926 927 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 928 pool->base.display_clock->max_clks_state = 929 static_clk_info.max_clocks_state; 930 931 { 932 struct irq_service_init_data init_data; 933 init_data.ctx = dc->ctx; 934 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 935 if (!pool->base.irqs) 936 goto res_create_fail; 937 } 938 939 for (i = 0; i < pool->base.pipe_count; i++) { 940 pool->base.timing_generators[i] = dce80_timing_generator_create( 941 ctx, i, &dce80_tg_offsets[i]); 942 if (pool->base.timing_generators[i] == NULL) { 943 BREAK_TO_DEBUGGER(); 944 dm_error("DC: failed to create tg!\n"); 945 goto res_create_fail; 946 } 947 948 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 949 if (pool->base.mis[i] == NULL) { 950 BREAK_TO_DEBUGGER(); 951 dm_error("DC: failed to create memory input!\n"); 952 goto res_create_fail; 953 } 954 955 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 956 if (pool->base.ipps[i] == NULL) { 957 BREAK_TO_DEBUGGER(); 958 dm_error("DC: failed to create input pixel processor!\n"); 959 goto res_create_fail; 960 } 961 962 pool->base.transforms[i] = dce80_transform_create(ctx, i); 963 if (pool->base.transforms[i] == NULL) { 964 BREAK_TO_DEBUGGER(); 965 dm_error("DC: failed to create transform!\n"); 966 goto res_create_fail; 967 } 968 969 pool->base.opps[i] = dce80_opp_create(ctx, i); 970 if (pool->base.opps[i] == NULL) { 971 BREAK_TO_DEBUGGER(); 972 dm_error("DC: failed to create output pixel processor!\n"); 973 goto res_create_fail; 974 } 975 } 976 977 dc->caps.max_planes = pool->base.pipe_count; 978 979 if (!resource_construct(num_virtual_links, dc, &pool->base, 980 &res_create_funcs)) 981 goto res_create_fail; 982 983 /* Create hardware sequencer */ 984 if (!dce80_hw_sequencer_construct(dc)) 985 goto res_create_fail; 986 987 return true; 988 989 res_create_fail: 990 destruct(pool); 991 return false; 992 } 993 994 struct resource_pool *dce80_create_resource_pool( 995 uint8_t num_virtual_links, 996 struct dc *dc) 997 { 998 struct dce110_resource_pool *pool = 999 dm_alloc(sizeof(struct dce110_resource_pool)); 1000 1001 if (!pool) 1002 return NULL; 1003 1004 if (dce80_construct(num_virtual_links, dc, pool)) 1005 return &pool->base; 1006 1007 BREAK_TO_DEBUGGER(); 1008 return NULL; 1009 } 1010 1011 static bool dce81_construct( 1012 uint8_t num_virtual_links, 1013 struct dc *dc, 1014 struct dce110_resource_pool *pool) 1015 { 1016 unsigned int i; 1017 struct dc_context *ctx = dc->ctx; 1018 struct dc_firmware_info info; 1019 struct dc_bios *bp; 1020 struct dm_pp_static_clock_info static_clk_info = {0}; 1021 1022 ctx->dc_bios->regs = &bios_regs; 1023 1024 pool->base.res_cap = &res_cap_81; 1025 pool->base.funcs = &dce80_res_pool_funcs; 1026 1027 1028 /************************************************* 1029 * Resource + asic cap harcoding * 1030 *************************************************/ 1031 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1032 pool->base.pipe_count = res_cap_81.num_timing_generator; 1033 dc->caps.max_downscale_ratio = 200; 1034 dc->caps.i2c_speed_in_khz = 40; 1035 dc->caps.max_cursor_size = 128; 1036 1037 /************************************************* 1038 * Create resources * 1039 *************************************************/ 1040 1041 bp = ctx->dc_bios; 1042 1043 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1044 info.external_clock_source_frequency_for_dp != 0) { 1045 pool->base.dp_clock_source = 1046 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1047 1048 pool->base.clock_sources[0] = 1049 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1050 pool->base.clock_sources[1] = 1051 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1052 pool->base.clock_sources[2] = 1053 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1054 pool->base.clk_src_count = 3; 1055 1056 } else { 1057 pool->base.dp_clock_source = 1058 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1059 1060 pool->base.clock_sources[0] = 1061 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1062 pool->base.clock_sources[1] = 1063 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1064 pool->base.clk_src_count = 2; 1065 } 1066 1067 if (pool->base.dp_clock_source == NULL) { 1068 dm_error("DC: failed to create dp clock source!\n"); 1069 BREAK_TO_DEBUGGER(); 1070 goto res_create_fail; 1071 } 1072 1073 for (i = 0; i < pool->base.clk_src_count; i++) { 1074 if (pool->base.clock_sources[i] == NULL) { 1075 dm_error("DC: failed to create clock sources!\n"); 1076 BREAK_TO_DEBUGGER(); 1077 goto res_create_fail; 1078 } 1079 } 1080 1081 pool->base.display_clock = dce_disp_clk_create(ctx, 1082 &disp_clk_regs, 1083 &disp_clk_shift, 1084 &disp_clk_mask); 1085 if (pool->base.display_clock == NULL) { 1086 dm_error("DC: failed to create display clock!\n"); 1087 BREAK_TO_DEBUGGER(); 1088 goto res_create_fail; 1089 } 1090 1091 1092 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1093 pool->base.display_clock->max_clks_state = 1094 static_clk_info.max_clocks_state; 1095 1096 { 1097 struct irq_service_init_data init_data; 1098 init_data.ctx = dc->ctx; 1099 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1100 if (!pool->base.irqs) 1101 goto res_create_fail; 1102 } 1103 1104 for (i = 0; i < pool->base.pipe_count; i++) { 1105 pool->base.timing_generators[i] = dce80_timing_generator_create( 1106 ctx, i, &dce80_tg_offsets[i]); 1107 if (pool->base.timing_generators[i] == NULL) { 1108 BREAK_TO_DEBUGGER(); 1109 dm_error("DC: failed to create tg!\n"); 1110 goto res_create_fail; 1111 } 1112 1113 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1114 if (pool->base.mis[i] == NULL) { 1115 BREAK_TO_DEBUGGER(); 1116 dm_error("DC: failed to create memory input!\n"); 1117 goto res_create_fail; 1118 } 1119 1120 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1121 if (pool->base.ipps[i] == NULL) { 1122 BREAK_TO_DEBUGGER(); 1123 dm_error("DC: failed to create input pixel processor!\n"); 1124 goto res_create_fail; 1125 } 1126 1127 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1128 if (pool->base.transforms[i] == NULL) { 1129 BREAK_TO_DEBUGGER(); 1130 dm_error("DC: failed to create transform!\n"); 1131 goto res_create_fail; 1132 } 1133 1134 pool->base.opps[i] = dce80_opp_create(ctx, i); 1135 if (pool->base.opps[i] == NULL) { 1136 BREAK_TO_DEBUGGER(); 1137 dm_error("DC: failed to create output pixel processor!\n"); 1138 goto res_create_fail; 1139 } 1140 } 1141 1142 dc->caps.max_planes = pool->base.pipe_count; 1143 1144 if (!resource_construct(num_virtual_links, dc, &pool->base, 1145 &res_create_funcs)) 1146 goto res_create_fail; 1147 1148 /* Create hardware sequencer */ 1149 if (!dce80_hw_sequencer_construct(dc)) 1150 goto res_create_fail; 1151 1152 return true; 1153 1154 res_create_fail: 1155 destruct(pool); 1156 return false; 1157 } 1158 1159 struct resource_pool *dce81_create_resource_pool( 1160 uint8_t num_virtual_links, 1161 struct dc *dc) 1162 { 1163 struct dce110_resource_pool *pool = 1164 dm_alloc(sizeof(struct dce110_resource_pool)); 1165 1166 if (!pool) 1167 return NULL; 1168 1169 if (dce81_construct(num_virtual_links, dc, pool)) 1170 return &pool->base; 1171 1172 BREAK_TO_DEBUGGER(); 1173 return NULL; 1174 } 1175 1176 static bool dce83_construct( 1177 uint8_t num_virtual_links, 1178 struct dc *dc, 1179 struct dce110_resource_pool *pool) 1180 { 1181 unsigned int i; 1182 struct dc_context *ctx = dc->ctx; 1183 struct dc_firmware_info info; 1184 struct dc_bios *bp; 1185 struct dm_pp_static_clock_info static_clk_info = {0}; 1186 1187 ctx->dc_bios->regs = &bios_regs; 1188 1189 pool->base.res_cap = &res_cap_83; 1190 pool->base.funcs = &dce80_res_pool_funcs; 1191 1192 1193 /************************************************* 1194 * Resource + asic cap harcoding * 1195 *************************************************/ 1196 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1197 pool->base.pipe_count = res_cap_83.num_timing_generator; 1198 dc->caps.max_downscale_ratio = 200; 1199 dc->caps.i2c_speed_in_khz = 40; 1200 dc->caps.max_cursor_size = 128; 1201 1202 /************************************************* 1203 * Create resources * 1204 *************************************************/ 1205 1206 bp = ctx->dc_bios; 1207 1208 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1209 info.external_clock_source_frequency_for_dp != 0) { 1210 pool->base.dp_clock_source = 1211 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1212 1213 pool->base.clock_sources[0] = 1214 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1215 pool->base.clock_sources[1] = 1216 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1217 pool->base.clk_src_count = 2; 1218 1219 } else { 1220 pool->base.dp_clock_source = 1221 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1222 1223 pool->base.clock_sources[0] = 1224 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1225 pool->base.clk_src_count = 1; 1226 } 1227 1228 if (pool->base.dp_clock_source == NULL) { 1229 dm_error("DC: failed to create dp clock source!\n"); 1230 BREAK_TO_DEBUGGER(); 1231 goto res_create_fail; 1232 } 1233 1234 for (i = 0; i < pool->base.clk_src_count; i++) { 1235 if (pool->base.clock_sources[i] == NULL) { 1236 dm_error("DC: failed to create clock sources!\n"); 1237 BREAK_TO_DEBUGGER(); 1238 goto res_create_fail; 1239 } 1240 } 1241 1242 pool->base.display_clock = dce_disp_clk_create(ctx, 1243 &disp_clk_regs, 1244 &disp_clk_shift, 1245 &disp_clk_mask); 1246 if (pool->base.display_clock == NULL) { 1247 dm_error("DC: failed to create display clock!\n"); 1248 BREAK_TO_DEBUGGER(); 1249 goto res_create_fail; 1250 } 1251 1252 1253 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1254 pool->base.display_clock->max_clks_state = 1255 static_clk_info.max_clocks_state; 1256 1257 { 1258 struct irq_service_init_data init_data; 1259 init_data.ctx = dc->ctx; 1260 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1261 if (!pool->base.irqs) 1262 goto res_create_fail; 1263 } 1264 1265 for (i = 0; i < pool->base.pipe_count; i++) { 1266 pool->base.timing_generators[i] = dce80_timing_generator_create( 1267 ctx, i, &dce80_tg_offsets[i]); 1268 if (pool->base.timing_generators[i] == NULL) { 1269 BREAK_TO_DEBUGGER(); 1270 dm_error("DC: failed to create tg!\n"); 1271 goto res_create_fail; 1272 } 1273 1274 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1275 if (pool->base.mis[i] == NULL) { 1276 BREAK_TO_DEBUGGER(); 1277 dm_error("DC: failed to create memory input!\n"); 1278 goto res_create_fail; 1279 } 1280 1281 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1282 if (pool->base.ipps[i] == NULL) { 1283 BREAK_TO_DEBUGGER(); 1284 dm_error("DC: failed to create input pixel processor!\n"); 1285 goto res_create_fail; 1286 } 1287 1288 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1289 if (pool->base.transforms[i] == NULL) { 1290 BREAK_TO_DEBUGGER(); 1291 dm_error("DC: failed to create transform!\n"); 1292 goto res_create_fail; 1293 } 1294 1295 pool->base.opps[i] = dce80_opp_create(ctx, i); 1296 if (pool->base.opps[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error("DC: failed to create output pixel processor!\n"); 1299 goto res_create_fail; 1300 } 1301 } 1302 1303 dc->caps.max_planes = pool->base.pipe_count; 1304 1305 if (!resource_construct(num_virtual_links, dc, &pool->base, 1306 &res_create_funcs)) 1307 goto res_create_fail; 1308 1309 /* Create hardware sequencer */ 1310 if (!dce80_hw_sequencer_construct(dc)) 1311 goto res_create_fail; 1312 1313 return true; 1314 1315 res_create_fail: 1316 destruct(pool); 1317 return false; 1318 } 1319 1320 struct resource_pool *dce83_create_resource_pool( 1321 uint8_t num_virtual_links, 1322 struct dc *dc) 1323 { 1324 struct dce110_resource_pool *pool = 1325 dm_alloc(sizeof(struct dce110_resource_pool)); 1326 1327 if (!pool) 1328 return NULL; 1329 1330 if (dce83_construct(num_virtual_links, dc, pool)) 1331 return &pool->base; 1332 1333 BREAK_TO_DEBUGGER(); 1334 return NULL; 1335 } 1336