1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 #include "dce/dce_i2c.h" 60 /* TODO remove this include */ 61 62 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 63 #include "gmc/gmc_7_1_d.h" 64 #include "gmc/gmc_7_1_sh_mask.h" 65 #endif 66 67 #ifndef mmDP_DPHY_INTERNAL_CTRL 68 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_6 0x05CF 82 #endif 83 84 #ifndef mmDP_DPHY_FAST_TRAINING 85 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 88 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 89 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 90 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 91 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 92 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 93 #endif 94 95 96 #ifndef mmHPD_DC_HPD_CONTROL 97 #define mmHPD_DC_HPD_CONTROL 0x189A 98 #define mmHPD0_DC_HPD_CONTROL 0x189A 99 #define mmHPD1_DC_HPD_CONTROL 0x18A2 100 #define mmHPD2_DC_HPD_CONTROL 0x18AA 101 #define mmHPD3_DC_HPD_CONTROL 0x18B2 102 #define mmHPD4_DC_HPD_CONTROL 0x18BA 103 #define mmHPD5_DC_HPD_CONTROL 0x18C2 104 #endif 105 106 #define DCE11_DIG_FE_CNTL 0x4a00 107 #define DCE11_DIG_BE_CNTL 0x4a47 108 #define DCE11_DP_SEC 0x4ac3 109 110 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 111 { 112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 114 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 115 - mmDPG_WATERMARK_MASK_CONTROL), 116 }, 117 { 118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 120 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 121 - mmDPG_WATERMARK_MASK_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 127 - mmDPG_WATERMARK_MASK_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 133 - mmDPG_WATERMARK_MASK_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 138 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 139 - mmDPG_WATERMARK_MASK_CONTROL), 140 }, 141 { 142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 144 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 145 - mmDPG_WATERMARK_MASK_CONTROL), 146 } 147 }; 148 149 /* set register offset */ 150 #define SR(reg_name)\ 151 .reg_name = mm ## reg_name 152 153 /* set register offset with instance */ 154 #define SRI(reg_name, block, id)\ 155 .reg_name = mm ## block ## id ## _ ## reg_name 156 157 158 static const struct dccg_registers disp_clk_regs = { 159 CLK_COMMON_REG_LIST_DCE_BASE() 160 }; 161 162 static const struct dccg_shift disp_clk_shift = { 163 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 164 }; 165 166 static const struct dccg_mask disp_clk_mask = { 167 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 168 }; 169 170 #define ipp_regs(id)\ 171 [id] = {\ 172 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 173 } 174 175 static const struct dce_ipp_registers ipp_regs[] = { 176 ipp_regs(0), 177 ipp_regs(1), 178 ipp_regs(2), 179 ipp_regs(3), 180 ipp_regs(4), 181 ipp_regs(5) 182 }; 183 184 static const struct dce_ipp_shift ipp_shift = { 185 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 186 }; 187 188 static const struct dce_ipp_mask ipp_mask = { 189 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 190 }; 191 192 #define transform_regs(id)\ 193 [id] = {\ 194 XFM_COMMON_REG_LIST_DCE80(id)\ 195 } 196 197 static const struct dce_transform_registers xfm_regs[] = { 198 transform_regs(0), 199 transform_regs(1), 200 transform_regs(2), 201 transform_regs(3), 202 transform_regs(4), 203 transform_regs(5) 204 }; 205 206 static const struct dce_transform_shift xfm_shift = { 207 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 208 }; 209 210 static const struct dce_transform_mask xfm_mask = { 211 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 212 }; 213 214 #define aux_regs(id)\ 215 [id] = {\ 216 AUX_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 220 aux_regs(0), 221 aux_regs(1), 222 aux_regs(2), 223 aux_regs(3), 224 aux_regs(4), 225 aux_regs(5) 226 }; 227 228 #define hpd_regs(id)\ 229 [id] = {\ 230 HPD_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 234 hpd_regs(0), 235 hpd_regs(1), 236 hpd_regs(2), 237 hpd_regs(3), 238 hpd_regs(4), 239 hpd_regs(5) 240 }; 241 242 #define link_regs(id)\ 243 [id] = {\ 244 LE_DCE80_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_registers link_enc_regs[] = { 248 link_regs(0), 249 link_regs(1), 250 link_regs(2), 251 link_regs(3), 252 link_regs(4), 253 link_regs(5), 254 link_regs(6), 255 }; 256 257 #define stream_enc_regs(id)\ 258 [id] = {\ 259 SE_COMMON_REG_LIST_DCE_BASE(id),\ 260 .AFMT_CNTL = 0,\ 261 } 262 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 264 stream_enc_regs(0), 265 stream_enc_regs(1), 266 stream_enc_regs(2), 267 stream_enc_regs(3), 268 stream_enc_regs(4), 269 stream_enc_regs(5), 270 stream_enc_regs(6) 271 }; 272 273 static const struct dce_stream_encoder_shift se_shift = { 274 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 275 }; 276 277 static const struct dce_stream_encoder_mask se_mask = { 278 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 279 }; 280 281 #define opp_regs(id)\ 282 [id] = {\ 283 OPP_DCE_80_REG_LIST(id),\ 284 } 285 286 static const struct dce_opp_registers opp_regs[] = { 287 opp_regs(0), 288 opp_regs(1), 289 opp_regs(2), 290 opp_regs(3), 291 opp_regs(4), 292 opp_regs(5) 293 }; 294 295 static const struct dce_opp_shift opp_shift = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 297 }; 298 299 static const struct dce_opp_mask opp_mask = { 300 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 301 }; 302 303 #define aux_engine_regs(id)\ 304 [id] = {\ 305 AUX_COMMON_REG_LIST(id), \ 306 .AUX_RESET_MASK = 0 \ 307 } 308 309 static const struct dce110_aux_registers aux_engine_regs[] = { 310 aux_engine_regs(0), 311 aux_engine_regs(1), 312 aux_engine_regs(2), 313 aux_engine_regs(3), 314 aux_engine_regs(4), 315 aux_engine_regs(5) 316 }; 317 318 #define audio_regs(id)\ 319 [id] = {\ 320 AUD_COMMON_REG_LIST(id)\ 321 } 322 323 static const struct dce_audio_registers audio_regs[] = { 324 audio_regs(0), 325 audio_regs(1), 326 audio_regs(2), 327 audio_regs(3), 328 audio_regs(4), 329 audio_regs(5), 330 audio_regs(6), 331 }; 332 333 static const struct dce_audio_shift audio_shift = { 334 AUD_COMMON_MASK_SH_LIST(__SHIFT) 335 }; 336 337 static const struct dce_aduio_mask audio_mask = { 338 AUD_COMMON_MASK_SH_LIST(_MASK) 339 }; 340 341 #define clk_src_regs(id)\ 342 [id] = {\ 343 CS_COMMON_REG_LIST_DCE_80(id),\ 344 } 345 346 347 static const struct dce110_clk_src_regs clk_src_regs[] = { 348 clk_src_regs(0), 349 clk_src_regs(1), 350 clk_src_regs(2) 351 }; 352 353 static const struct dce110_clk_src_shift cs_shift = { 354 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 355 }; 356 357 static const struct dce110_clk_src_mask cs_mask = { 358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 359 }; 360 361 static const struct bios_registers bios_regs = { 362 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 363 }; 364 365 static const struct resource_caps res_cap = { 366 .num_timing_generator = 6, 367 .num_audio = 6, 368 .num_stream_encoder = 6, 369 .num_pll = 3, 370 .num_ddc = 6, 371 }; 372 373 static const struct resource_caps res_cap_81 = { 374 .num_timing_generator = 4, 375 .num_audio = 7, 376 .num_stream_encoder = 7, 377 .num_pll = 3, 378 .num_ddc = 6, 379 }; 380 381 static const struct resource_caps res_cap_83 = { 382 .num_timing_generator = 2, 383 .num_audio = 6, 384 .num_stream_encoder = 6, 385 .num_pll = 2, 386 .num_ddc = 2, 387 }; 388 389 static const struct dce_dmcu_registers dmcu_regs = { 390 DMCU_DCE80_REG_LIST() 391 }; 392 393 static const struct dce_dmcu_shift dmcu_shift = { 394 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 395 }; 396 397 static const struct dce_dmcu_mask dmcu_mask = { 398 DMCU_MASK_SH_LIST_DCE80(_MASK) 399 }; 400 static const struct dce_abm_registers abm_regs = { 401 ABM_DCE110_COMMON_REG_LIST() 402 }; 403 404 static const struct dce_abm_shift abm_shift = { 405 ABM_MASK_SH_LIST_DCE110(__SHIFT) 406 }; 407 408 static const struct dce_abm_mask abm_mask = { 409 ABM_MASK_SH_LIST_DCE110(_MASK) 410 }; 411 412 #define CTX ctx 413 #define REG(reg) mm ## reg 414 415 #ifndef mmCC_DC_HDMI_STRAPS 416 #define mmCC_DC_HDMI_STRAPS 0x1918 417 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 418 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 419 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 420 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 421 #endif 422 423 static void read_dce_straps( 424 struct dc_context *ctx, 425 struct resource_straps *straps) 426 { 427 REG_GET_2(CC_DC_HDMI_STRAPS, 428 HDMI_DISABLE, &straps->hdmi_disable, 429 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 430 431 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 432 } 433 434 static struct audio *create_audio( 435 struct dc_context *ctx, unsigned int inst) 436 { 437 return dce_audio_create(ctx, inst, 438 &audio_regs[inst], &audio_shift, &audio_mask); 439 } 440 441 static struct timing_generator *dce80_timing_generator_create( 442 struct dc_context *ctx, 443 uint32_t instance, 444 const struct dce110_timing_generator_offsets *offsets) 445 { 446 struct dce110_timing_generator *tg110 = 447 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 448 449 if (!tg110) 450 return NULL; 451 452 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 453 return &tg110->base; 454 } 455 456 static struct output_pixel_processor *dce80_opp_create( 457 struct dc_context *ctx, 458 uint32_t inst) 459 { 460 struct dce110_opp *opp = 461 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 462 463 if (!opp) 464 return NULL; 465 466 dce110_opp_construct(opp, 467 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 468 return &opp->base; 469 } 470 471 struct aux_engine *dce80_aux_engine_create( 472 struct dc_context *ctx, 473 uint32_t inst) 474 { 475 struct aux_engine_dce110 *aux_engine = 476 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 477 478 if (!aux_engine) 479 return NULL; 480 481 dce110_aux_engine_construct(aux_engine, ctx, inst, 482 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 483 &aux_engine_regs[inst]); 484 485 return &aux_engine->base; 486 } 487 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 488 489 static const struct dce_i2c_registers i2c_hw_regs[] = { 490 i2c_inst_regs(1), 491 i2c_inst_regs(2), 492 i2c_inst_regs(3), 493 i2c_inst_regs(4), 494 i2c_inst_regs(5), 495 i2c_inst_regs(6), 496 }; 497 498 static const struct dce_i2c_shift i2c_shifts = { 499 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 500 }; 501 502 static const struct dce_i2c_mask i2c_masks = { 503 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 504 }; 505 506 struct dce_i2c_hw *dce80_i2c_hw_create( 507 struct dc_context *ctx, 508 uint32_t inst) 509 { 510 struct dce_i2c_hw *dce_i2c_hw = 511 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 512 513 if (!dce_i2c_hw) 514 return NULL; 515 516 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 517 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 518 519 return dce_i2c_hw; 520 } 521 522 struct dce_i2c_sw *dce80_i2c_sw_create( 523 struct dc_context *ctx) 524 { 525 struct dce_i2c_sw *dce_i2c_sw = 526 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 527 528 if (!dce_i2c_sw) 529 return NULL; 530 531 dce_i2c_sw_construct(dce_i2c_sw, ctx); 532 533 return dce_i2c_sw; 534 } 535 static struct stream_encoder *dce80_stream_encoder_create( 536 enum engine_id eng_id, 537 struct dc_context *ctx) 538 { 539 struct dce110_stream_encoder *enc110 = 540 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 541 542 if (!enc110) 543 return NULL; 544 545 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 546 &stream_enc_regs[eng_id], 547 &se_shift, &se_mask); 548 return &enc110->base; 549 } 550 551 #define SRII(reg_name, block, id)\ 552 .reg_name[id] = mm ## block ## id ## _ ## reg_name 553 554 static const struct dce_hwseq_registers hwseq_reg = { 555 HWSEQ_DCE8_REG_LIST() 556 }; 557 558 static const struct dce_hwseq_shift hwseq_shift = { 559 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 560 }; 561 562 static const struct dce_hwseq_mask hwseq_mask = { 563 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 564 }; 565 566 static struct dce_hwseq *dce80_hwseq_create( 567 struct dc_context *ctx) 568 { 569 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 570 571 if (hws) { 572 hws->ctx = ctx; 573 hws->regs = &hwseq_reg; 574 hws->shifts = &hwseq_shift; 575 hws->masks = &hwseq_mask; 576 } 577 return hws; 578 } 579 580 static const struct resource_create_funcs res_create_funcs = { 581 .read_dce_straps = read_dce_straps, 582 .create_audio = create_audio, 583 .create_stream_encoder = dce80_stream_encoder_create, 584 .create_hwseq = dce80_hwseq_create, 585 }; 586 587 #define mi_inst_regs(id) { \ 588 MI_DCE8_REG_LIST(id), \ 589 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 590 } 591 static const struct dce_mem_input_registers mi_regs[] = { 592 mi_inst_regs(0), 593 mi_inst_regs(1), 594 mi_inst_regs(2), 595 mi_inst_regs(3), 596 mi_inst_regs(4), 597 mi_inst_regs(5), 598 }; 599 600 static const struct dce_mem_input_shift mi_shifts = { 601 MI_DCE8_MASK_SH_LIST(__SHIFT), 602 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 603 }; 604 605 static const struct dce_mem_input_mask mi_masks = { 606 MI_DCE8_MASK_SH_LIST(_MASK), 607 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 608 }; 609 610 static struct mem_input *dce80_mem_input_create( 611 struct dc_context *ctx, 612 uint32_t inst) 613 { 614 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 615 GFP_KERNEL); 616 617 if (!dce_mi) { 618 BREAK_TO_DEBUGGER(); 619 return NULL; 620 } 621 622 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 623 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 624 return &dce_mi->base; 625 } 626 627 static void dce80_transform_destroy(struct transform **xfm) 628 { 629 kfree(TO_DCE_TRANSFORM(*xfm)); 630 *xfm = NULL; 631 } 632 633 static struct transform *dce80_transform_create( 634 struct dc_context *ctx, 635 uint32_t inst) 636 { 637 struct dce_transform *transform = 638 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 639 640 if (!transform) 641 return NULL; 642 643 dce_transform_construct(transform, ctx, inst, 644 &xfm_regs[inst], &xfm_shift, &xfm_mask); 645 transform->prescaler_on = false; 646 return &transform->base; 647 } 648 649 static const struct encoder_feature_support link_enc_feature = { 650 .max_hdmi_deep_color = COLOR_DEPTH_121212, 651 .max_hdmi_pixel_clock = 297000, 652 .flags.bits.IS_HBR2_CAPABLE = true, 653 .flags.bits.IS_TPS3_CAPABLE = true 654 }; 655 656 struct link_encoder *dce80_link_encoder_create( 657 const struct encoder_init_data *enc_init_data) 658 { 659 struct dce110_link_encoder *enc110 = 660 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 661 662 if (!enc110) 663 return NULL; 664 665 dce110_link_encoder_construct(enc110, 666 enc_init_data, 667 &link_enc_feature, 668 &link_enc_regs[enc_init_data->transmitter], 669 &link_enc_aux_regs[enc_init_data->channel - 1], 670 &link_enc_hpd_regs[enc_init_data->hpd_source]); 671 return &enc110->base; 672 } 673 674 struct clock_source *dce80_clock_source_create( 675 struct dc_context *ctx, 676 struct dc_bios *bios, 677 enum clock_source_id id, 678 const struct dce110_clk_src_regs *regs, 679 bool dp_clk_src) 680 { 681 struct dce110_clk_src *clk_src = 682 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 683 684 if (!clk_src) 685 return NULL; 686 687 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 688 regs, &cs_shift, &cs_mask)) { 689 clk_src->base.dp_clk_src = dp_clk_src; 690 return &clk_src->base; 691 } 692 693 BREAK_TO_DEBUGGER(); 694 return NULL; 695 } 696 697 void dce80_clock_source_destroy(struct clock_source **clk_src) 698 { 699 kfree(TO_DCE110_CLK_SRC(*clk_src)); 700 *clk_src = NULL; 701 } 702 703 static struct input_pixel_processor *dce80_ipp_create( 704 struct dc_context *ctx, uint32_t inst) 705 { 706 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 707 708 if (!ipp) { 709 BREAK_TO_DEBUGGER(); 710 return NULL; 711 } 712 713 dce_ipp_construct(ipp, ctx, inst, 714 &ipp_regs[inst], &ipp_shift, &ipp_mask); 715 return &ipp->base; 716 } 717 718 static void destruct(struct dce110_resource_pool *pool) 719 { 720 unsigned int i; 721 722 for (i = 0; i < pool->base.pipe_count; i++) { 723 if (pool->base.opps[i] != NULL) 724 dce110_opp_destroy(&pool->base.opps[i]); 725 726 if (pool->base.transforms[i] != NULL) 727 dce80_transform_destroy(&pool->base.transforms[i]); 728 729 if (pool->base.ipps[i] != NULL) 730 dce_ipp_destroy(&pool->base.ipps[i]); 731 732 if (pool->base.mis[i] != NULL) { 733 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 734 pool->base.mis[i] = NULL; 735 } 736 737 if (pool->base.timing_generators[i] != NULL) { 738 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 739 pool->base.timing_generators[i] = NULL; 740 } 741 } 742 743 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 744 if (pool->base.engines[i] != NULL) 745 dce110_engine_destroy(&pool->base.engines[i]); 746 if (pool->base.hw_i2cs[i] != NULL) { 747 kfree(pool->base.hw_i2cs[i]); 748 pool->base.hw_i2cs[i] = NULL; 749 } 750 if (pool->base.sw_i2cs[i] != NULL) { 751 kfree(pool->base.sw_i2cs[i]); 752 pool->base.sw_i2cs[i] = NULL; 753 } 754 } 755 756 for (i = 0; i < pool->base.stream_enc_count; i++) { 757 if (pool->base.stream_enc[i] != NULL) 758 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 759 } 760 761 for (i = 0; i < pool->base.clk_src_count; i++) { 762 if (pool->base.clock_sources[i] != NULL) { 763 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 764 } 765 } 766 767 if (pool->base.abm != NULL) 768 dce_abm_destroy(&pool->base.abm); 769 770 if (pool->base.dmcu != NULL) 771 dce_dmcu_destroy(&pool->base.dmcu); 772 773 if (pool->base.dp_clock_source != NULL) 774 dce80_clock_source_destroy(&pool->base.dp_clock_source); 775 776 for (i = 0; i < pool->base.audio_count; i++) { 777 if (pool->base.audios[i] != NULL) { 778 dce_aud_destroy(&pool->base.audios[i]); 779 } 780 } 781 782 if (pool->base.dccg != NULL) 783 dce_dccg_destroy(&pool->base.dccg); 784 785 if (pool->base.irqs != NULL) { 786 dal_irq_service_destroy(&pool->base.irqs); 787 } 788 } 789 790 bool dce80_validate_bandwidth( 791 struct dc *dc, 792 struct dc_state *context) 793 { 794 /* TODO implement when needed but for now hardcode max value*/ 795 context->bw.dce.dispclk_khz = 681000; 796 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 797 798 return true; 799 } 800 801 static bool dce80_validate_surface_sets( 802 struct dc_state *context) 803 { 804 int i; 805 806 for (i = 0; i < context->stream_count; i++) { 807 if (context->stream_status[i].plane_count == 0) 808 continue; 809 810 if (context->stream_status[i].plane_count > 1) 811 return false; 812 813 if (context->stream_status[i].plane_states[0]->format 814 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 815 return false; 816 } 817 818 return true; 819 } 820 821 enum dc_status dce80_validate_global( 822 struct dc *dc, 823 struct dc_state *context) 824 { 825 if (!dce80_validate_surface_sets(context)) 826 return DC_FAIL_SURFACE_VALIDATE; 827 828 return DC_OK; 829 } 830 831 static void dce80_destroy_resource_pool(struct resource_pool **pool) 832 { 833 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 834 835 destruct(dce110_pool); 836 kfree(dce110_pool); 837 *pool = NULL; 838 } 839 840 static const struct resource_funcs dce80_res_pool_funcs = { 841 .destroy = dce80_destroy_resource_pool, 842 .link_enc_create = dce80_link_encoder_create, 843 .validate_bandwidth = dce80_validate_bandwidth, 844 .validate_plane = dce100_validate_plane, 845 .add_stream_to_ctx = dce100_add_stream_to_ctx, 846 .validate_global = dce80_validate_global 847 }; 848 849 static bool dce80_construct( 850 uint8_t num_virtual_links, 851 struct dc *dc, 852 struct dce110_resource_pool *pool) 853 { 854 unsigned int i; 855 struct dc_context *ctx = dc->ctx; 856 struct dc_firmware_info info; 857 struct dc_bios *bp; 858 struct dm_pp_static_clock_info static_clk_info = {0}; 859 860 ctx->dc_bios->regs = &bios_regs; 861 862 pool->base.res_cap = &res_cap; 863 pool->base.funcs = &dce80_res_pool_funcs; 864 865 866 /************************************************* 867 * Resource + asic cap harcoding * 868 *************************************************/ 869 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 870 pool->base.pipe_count = res_cap.num_timing_generator; 871 pool->base.timing_generator_count = res_cap.num_timing_generator; 872 dc->caps.max_downscale_ratio = 200; 873 dc->caps.i2c_speed_in_khz = 40; 874 dc->caps.max_cursor_size = 128; 875 dc->caps.dual_link_dvi = true; 876 877 /************************************************* 878 * Create resources * 879 *************************************************/ 880 881 bp = ctx->dc_bios; 882 883 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 884 info.external_clock_source_frequency_for_dp != 0) { 885 pool->base.dp_clock_source = 886 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 887 888 pool->base.clock_sources[0] = 889 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 890 pool->base.clock_sources[1] = 891 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 892 pool->base.clock_sources[2] = 893 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 894 pool->base.clk_src_count = 3; 895 896 } else { 897 pool->base.dp_clock_source = 898 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 899 900 pool->base.clock_sources[0] = 901 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 902 pool->base.clock_sources[1] = 903 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 904 pool->base.clk_src_count = 2; 905 } 906 907 if (pool->base.dp_clock_source == NULL) { 908 dm_error("DC: failed to create dp clock source!\n"); 909 BREAK_TO_DEBUGGER(); 910 goto res_create_fail; 911 } 912 913 for (i = 0; i < pool->base.clk_src_count; i++) { 914 if (pool->base.clock_sources[i] == NULL) { 915 dm_error("DC: failed to create clock sources!\n"); 916 BREAK_TO_DEBUGGER(); 917 goto res_create_fail; 918 } 919 } 920 921 pool->base.dccg = dce_dccg_create(ctx, 922 &disp_clk_regs, 923 &disp_clk_shift, 924 &disp_clk_mask); 925 if (pool->base.dccg == NULL) { 926 dm_error("DC: failed to create display clock!\n"); 927 BREAK_TO_DEBUGGER(); 928 goto res_create_fail; 929 } 930 931 pool->base.dmcu = dce_dmcu_create(ctx, 932 &dmcu_regs, 933 &dmcu_shift, 934 &dmcu_mask); 935 if (pool->base.dmcu == NULL) { 936 dm_error("DC: failed to create dmcu!\n"); 937 BREAK_TO_DEBUGGER(); 938 goto res_create_fail; 939 } 940 941 pool->base.abm = dce_abm_create(ctx, 942 &abm_regs, 943 &abm_shift, 944 &abm_mask); 945 if (pool->base.abm == NULL) { 946 dm_error("DC: failed to create abm!\n"); 947 BREAK_TO_DEBUGGER(); 948 goto res_create_fail; 949 } 950 951 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 952 pool->base.dccg->max_clks_state = 953 static_clk_info.max_clocks_state; 954 955 { 956 struct irq_service_init_data init_data; 957 init_data.ctx = dc->ctx; 958 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 959 if (!pool->base.irqs) 960 goto res_create_fail; 961 } 962 963 for (i = 0; i < pool->base.pipe_count; i++) { 964 pool->base.timing_generators[i] = dce80_timing_generator_create( 965 ctx, i, &dce80_tg_offsets[i]); 966 if (pool->base.timing_generators[i] == NULL) { 967 BREAK_TO_DEBUGGER(); 968 dm_error("DC: failed to create tg!\n"); 969 goto res_create_fail; 970 } 971 972 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 973 if (pool->base.mis[i] == NULL) { 974 BREAK_TO_DEBUGGER(); 975 dm_error("DC: failed to create memory input!\n"); 976 goto res_create_fail; 977 } 978 979 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 980 if (pool->base.ipps[i] == NULL) { 981 BREAK_TO_DEBUGGER(); 982 dm_error("DC: failed to create input pixel processor!\n"); 983 goto res_create_fail; 984 } 985 986 pool->base.transforms[i] = dce80_transform_create(ctx, i); 987 if (pool->base.transforms[i] == NULL) { 988 BREAK_TO_DEBUGGER(); 989 dm_error("DC: failed to create transform!\n"); 990 goto res_create_fail; 991 } 992 993 pool->base.opps[i] = dce80_opp_create(ctx, i); 994 if (pool->base.opps[i] == NULL) { 995 BREAK_TO_DEBUGGER(); 996 dm_error("DC: failed to create output pixel processor!\n"); 997 goto res_create_fail; 998 } 999 } 1000 1001 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1002 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1003 if (pool->base.engines[i] == NULL) { 1004 BREAK_TO_DEBUGGER(); 1005 dm_error( 1006 "DC:failed to create aux engine!!\n"); 1007 goto res_create_fail; 1008 } 1009 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1010 if (pool->base.hw_i2cs[i] == NULL) { 1011 BREAK_TO_DEBUGGER(); 1012 dm_error( 1013 "DC:failed to create i2c engine!!\n"); 1014 goto res_create_fail; 1015 } 1016 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1017 if (pool->base.sw_i2cs[i] == NULL) { 1018 BREAK_TO_DEBUGGER(); 1019 dm_error( 1020 "DC:failed to create sw i2c!!\n"); 1021 goto res_create_fail; 1022 } 1023 } 1024 1025 dc->caps.max_planes = pool->base.pipe_count; 1026 dc->caps.disable_dp_clk_share = true; 1027 1028 if (!resource_construct(num_virtual_links, dc, &pool->base, 1029 &res_create_funcs)) 1030 goto res_create_fail; 1031 1032 /* Create hardware sequencer */ 1033 dce80_hw_sequencer_construct(dc); 1034 1035 return true; 1036 1037 res_create_fail: 1038 destruct(pool); 1039 return false; 1040 } 1041 1042 struct resource_pool *dce80_create_resource_pool( 1043 uint8_t num_virtual_links, 1044 struct dc *dc) 1045 { 1046 struct dce110_resource_pool *pool = 1047 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1048 1049 if (!pool) 1050 return NULL; 1051 1052 if (dce80_construct(num_virtual_links, dc, pool)) 1053 return &pool->base; 1054 1055 BREAK_TO_DEBUGGER(); 1056 return NULL; 1057 } 1058 1059 static bool dce81_construct( 1060 uint8_t num_virtual_links, 1061 struct dc *dc, 1062 struct dce110_resource_pool *pool) 1063 { 1064 unsigned int i; 1065 struct dc_context *ctx = dc->ctx; 1066 struct dc_firmware_info info; 1067 struct dc_bios *bp; 1068 struct dm_pp_static_clock_info static_clk_info = {0}; 1069 1070 ctx->dc_bios->regs = &bios_regs; 1071 1072 pool->base.res_cap = &res_cap_81; 1073 pool->base.funcs = &dce80_res_pool_funcs; 1074 1075 1076 /************************************************* 1077 * Resource + asic cap harcoding * 1078 *************************************************/ 1079 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1080 pool->base.pipe_count = res_cap_81.num_timing_generator; 1081 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1082 dc->caps.max_downscale_ratio = 200; 1083 dc->caps.i2c_speed_in_khz = 40; 1084 dc->caps.max_cursor_size = 128; 1085 dc->caps.is_apu = true; 1086 1087 /************************************************* 1088 * Create resources * 1089 *************************************************/ 1090 1091 bp = ctx->dc_bios; 1092 1093 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1094 info.external_clock_source_frequency_for_dp != 0) { 1095 pool->base.dp_clock_source = 1096 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1097 1098 pool->base.clock_sources[0] = 1099 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1100 pool->base.clock_sources[1] = 1101 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1102 pool->base.clock_sources[2] = 1103 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1104 pool->base.clk_src_count = 3; 1105 1106 } else { 1107 pool->base.dp_clock_source = 1108 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1109 1110 pool->base.clock_sources[0] = 1111 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1112 pool->base.clock_sources[1] = 1113 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1114 pool->base.clk_src_count = 2; 1115 } 1116 1117 if (pool->base.dp_clock_source == NULL) { 1118 dm_error("DC: failed to create dp clock source!\n"); 1119 BREAK_TO_DEBUGGER(); 1120 goto res_create_fail; 1121 } 1122 1123 for (i = 0; i < pool->base.clk_src_count; i++) { 1124 if (pool->base.clock_sources[i] == NULL) { 1125 dm_error("DC: failed to create clock sources!\n"); 1126 BREAK_TO_DEBUGGER(); 1127 goto res_create_fail; 1128 } 1129 } 1130 1131 pool->base.dccg = dce_dccg_create(ctx, 1132 &disp_clk_regs, 1133 &disp_clk_shift, 1134 &disp_clk_mask); 1135 if (pool->base.dccg == NULL) { 1136 dm_error("DC: failed to create display clock!\n"); 1137 BREAK_TO_DEBUGGER(); 1138 goto res_create_fail; 1139 } 1140 1141 pool->base.dmcu = dce_dmcu_create(ctx, 1142 &dmcu_regs, 1143 &dmcu_shift, 1144 &dmcu_mask); 1145 if (pool->base.dmcu == NULL) { 1146 dm_error("DC: failed to create dmcu!\n"); 1147 BREAK_TO_DEBUGGER(); 1148 goto res_create_fail; 1149 } 1150 1151 pool->base.abm = dce_abm_create(ctx, 1152 &abm_regs, 1153 &abm_shift, 1154 &abm_mask); 1155 if (pool->base.abm == NULL) { 1156 dm_error("DC: failed to create abm!\n"); 1157 BREAK_TO_DEBUGGER(); 1158 goto res_create_fail; 1159 } 1160 1161 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1162 pool->base.dccg->max_clks_state = 1163 static_clk_info.max_clocks_state; 1164 1165 { 1166 struct irq_service_init_data init_data; 1167 init_data.ctx = dc->ctx; 1168 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1169 if (!pool->base.irqs) 1170 goto res_create_fail; 1171 } 1172 1173 for (i = 0; i < pool->base.pipe_count; i++) { 1174 pool->base.timing_generators[i] = dce80_timing_generator_create( 1175 ctx, i, &dce80_tg_offsets[i]); 1176 if (pool->base.timing_generators[i] == NULL) { 1177 BREAK_TO_DEBUGGER(); 1178 dm_error("DC: failed to create tg!\n"); 1179 goto res_create_fail; 1180 } 1181 1182 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1183 if (pool->base.mis[i] == NULL) { 1184 BREAK_TO_DEBUGGER(); 1185 dm_error("DC: failed to create memory input!\n"); 1186 goto res_create_fail; 1187 } 1188 1189 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1190 if (pool->base.ipps[i] == NULL) { 1191 BREAK_TO_DEBUGGER(); 1192 dm_error("DC: failed to create input pixel processor!\n"); 1193 goto res_create_fail; 1194 } 1195 1196 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1197 if (pool->base.transforms[i] == NULL) { 1198 BREAK_TO_DEBUGGER(); 1199 dm_error("DC: failed to create transform!\n"); 1200 goto res_create_fail; 1201 } 1202 1203 pool->base.opps[i] = dce80_opp_create(ctx, i); 1204 if (pool->base.opps[i] == NULL) { 1205 BREAK_TO_DEBUGGER(); 1206 dm_error("DC: failed to create output pixel processor!\n"); 1207 goto res_create_fail; 1208 } 1209 } 1210 1211 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1212 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1213 if (pool->base.engines[i] == NULL) { 1214 BREAK_TO_DEBUGGER(); 1215 dm_error( 1216 "DC:failed to create aux engine!!\n"); 1217 goto res_create_fail; 1218 } 1219 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1220 if (pool->base.hw_i2cs[i] == NULL) { 1221 BREAK_TO_DEBUGGER(); 1222 dm_error( 1223 "DC:failed to create i2c engine!!\n"); 1224 goto res_create_fail; 1225 } 1226 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1227 if (pool->base.sw_i2cs[i] == NULL) { 1228 BREAK_TO_DEBUGGER(); 1229 dm_error( 1230 "DC:failed to create sw i2c!!\n"); 1231 goto res_create_fail; 1232 } 1233 } 1234 1235 dc->caps.max_planes = pool->base.pipe_count; 1236 dc->caps.disable_dp_clk_share = true; 1237 1238 if (!resource_construct(num_virtual_links, dc, &pool->base, 1239 &res_create_funcs)) 1240 goto res_create_fail; 1241 1242 /* Create hardware sequencer */ 1243 dce80_hw_sequencer_construct(dc); 1244 1245 return true; 1246 1247 res_create_fail: 1248 destruct(pool); 1249 return false; 1250 } 1251 1252 struct resource_pool *dce81_create_resource_pool( 1253 uint8_t num_virtual_links, 1254 struct dc *dc) 1255 { 1256 struct dce110_resource_pool *pool = 1257 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1258 1259 if (!pool) 1260 return NULL; 1261 1262 if (dce81_construct(num_virtual_links, dc, pool)) 1263 return &pool->base; 1264 1265 BREAK_TO_DEBUGGER(); 1266 return NULL; 1267 } 1268 1269 static bool dce83_construct( 1270 uint8_t num_virtual_links, 1271 struct dc *dc, 1272 struct dce110_resource_pool *pool) 1273 { 1274 unsigned int i; 1275 struct dc_context *ctx = dc->ctx; 1276 struct dc_firmware_info info; 1277 struct dc_bios *bp; 1278 struct dm_pp_static_clock_info static_clk_info = {0}; 1279 1280 ctx->dc_bios->regs = &bios_regs; 1281 1282 pool->base.res_cap = &res_cap_83; 1283 pool->base.funcs = &dce80_res_pool_funcs; 1284 1285 1286 /************************************************* 1287 * Resource + asic cap harcoding * 1288 *************************************************/ 1289 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1290 pool->base.pipe_count = res_cap_83.num_timing_generator; 1291 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1292 dc->caps.max_downscale_ratio = 200; 1293 dc->caps.i2c_speed_in_khz = 40; 1294 dc->caps.max_cursor_size = 128; 1295 dc->caps.is_apu = true; 1296 1297 /************************************************* 1298 * Create resources * 1299 *************************************************/ 1300 1301 bp = ctx->dc_bios; 1302 1303 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1304 info.external_clock_source_frequency_for_dp != 0) { 1305 pool->base.dp_clock_source = 1306 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1307 1308 pool->base.clock_sources[0] = 1309 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1310 pool->base.clock_sources[1] = 1311 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1312 pool->base.clk_src_count = 2; 1313 1314 } else { 1315 pool->base.dp_clock_source = 1316 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1317 1318 pool->base.clock_sources[0] = 1319 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1320 pool->base.clk_src_count = 1; 1321 } 1322 1323 if (pool->base.dp_clock_source == NULL) { 1324 dm_error("DC: failed to create dp clock source!\n"); 1325 BREAK_TO_DEBUGGER(); 1326 goto res_create_fail; 1327 } 1328 1329 for (i = 0; i < pool->base.clk_src_count; i++) { 1330 if (pool->base.clock_sources[i] == NULL) { 1331 dm_error("DC: failed to create clock sources!\n"); 1332 BREAK_TO_DEBUGGER(); 1333 goto res_create_fail; 1334 } 1335 } 1336 1337 pool->base.dccg = dce_dccg_create(ctx, 1338 &disp_clk_regs, 1339 &disp_clk_shift, 1340 &disp_clk_mask); 1341 if (pool->base.dccg == NULL) { 1342 dm_error("DC: failed to create display clock!\n"); 1343 BREAK_TO_DEBUGGER(); 1344 goto res_create_fail; 1345 } 1346 1347 pool->base.dmcu = dce_dmcu_create(ctx, 1348 &dmcu_regs, 1349 &dmcu_shift, 1350 &dmcu_mask); 1351 if (pool->base.dmcu == NULL) { 1352 dm_error("DC: failed to create dmcu!\n"); 1353 BREAK_TO_DEBUGGER(); 1354 goto res_create_fail; 1355 } 1356 1357 pool->base.abm = dce_abm_create(ctx, 1358 &abm_regs, 1359 &abm_shift, 1360 &abm_mask); 1361 if (pool->base.abm == NULL) { 1362 dm_error("DC: failed to create abm!\n"); 1363 BREAK_TO_DEBUGGER(); 1364 goto res_create_fail; 1365 } 1366 1367 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1368 pool->base.dccg->max_clks_state = 1369 static_clk_info.max_clocks_state; 1370 1371 { 1372 struct irq_service_init_data init_data; 1373 init_data.ctx = dc->ctx; 1374 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1375 if (!pool->base.irqs) 1376 goto res_create_fail; 1377 } 1378 1379 for (i = 0; i < pool->base.pipe_count; i++) { 1380 pool->base.timing_generators[i] = dce80_timing_generator_create( 1381 ctx, i, &dce80_tg_offsets[i]); 1382 if (pool->base.timing_generators[i] == NULL) { 1383 BREAK_TO_DEBUGGER(); 1384 dm_error("DC: failed to create tg!\n"); 1385 goto res_create_fail; 1386 } 1387 1388 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1389 if (pool->base.mis[i] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error("DC: failed to create memory input!\n"); 1392 goto res_create_fail; 1393 } 1394 1395 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1396 if (pool->base.ipps[i] == NULL) { 1397 BREAK_TO_DEBUGGER(); 1398 dm_error("DC: failed to create input pixel processor!\n"); 1399 goto res_create_fail; 1400 } 1401 1402 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1403 if (pool->base.transforms[i] == NULL) { 1404 BREAK_TO_DEBUGGER(); 1405 dm_error("DC: failed to create transform!\n"); 1406 goto res_create_fail; 1407 } 1408 1409 pool->base.opps[i] = dce80_opp_create(ctx, i); 1410 if (pool->base.opps[i] == NULL) { 1411 BREAK_TO_DEBUGGER(); 1412 dm_error("DC: failed to create output pixel processor!\n"); 1413 goto res_create_fail; 1414 } 1415 } 1416 1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1418 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1419 if (pool->base.engines[i] == NULL) { 1420 BREAK_TO_DEBUGGER(); 1421 dm_error( 1422 "DC:failed to create aux engine!!\n"); 1423 goto res_create_fail; 1424 } 1425 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1426 if (pool->base.hw_i2cs[i] == NULL) { 1427 BREAK_TO_DEBUGGER(); 1428 dm_error( 1429 "DC:failed to create i2c engine!!\n"); 1430 goto res_create_fail; 1431 } 1432 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1433 if (pool->base.sw_i2cs[i] == NULL) { 1434 BREAK_TO_DEBUGGER(); 1435 dm_error( 1436 "DC:failed to create sw i2c!!\n"); 1437 goto res_create_fail; 1438 } 1439 } 1440 1441 dc->caps.max_planes = pool->base.pipe_count; 1442 dc->caps.disable_dp_clk_share = true; 1443 1444 if (!resource_construct(num_virtual_links, dc, &pool->base, 1445 &res_create_funcs)) 1446 goto res_create_fail; 1447 1448 /* Create hardware sequencer */ 1449 dce80_hw_sequencer_construct(dc); 1450 1451 return true; 1452 1453 res_create_fail: 1454 destruct(pool); 1455 return false; 1456 } 1457 1458 struct resource_pool *dce83_create_resource_pool( 1459 uint8_t num_virtual_links, 1460 struct dc *dc) 1461 { 1462 struct dce110_resource_pool *pool = 1463 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1464 1465 if (!pool) 1466 return NULL; 1467 1468 if (dce83_construct(num_virtual_links, dc, pool)) 1469 return &pool->base; 1470 1471 BREAK_TO_DEBUGGER(); 1472 return NULL; 1473 } 1474