1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_clk_mgr.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce/dce_link_encoder.h" 43 #include "dce/dce_stream_encoder.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_audio.h" 49 #include "dce/dce_hwseq.h" 50 #include "dce80/dce80_hw_sequencer.h" 51 #include "dce100/dce100_resource.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_i2c.h" 59 /* TODO remove this include */ 60 61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 62 #include "gmc/gmc_7_1_d.h" 63 #include "gmc/gmc_7_1_sh_mask.h" 64 #endif 65 66 #ifndef mmDP_DPHY_INTERNAL_CTRL 67 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 75 #endif 76 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_3 0x05CC 81 #define mmBIOS_SCRATCH_6 0x05CF 82 #endif 83 84 #ifndef mmDP_DPHY_FAST_TRAINING 85 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 88 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 89 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 90 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 91 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 92 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 93 #endif 94 95 96 #ifndef mmHPD_DC_HPD_CONTROL 97 #define mmHPD_DC_HPD_CONTROL 0x189A 98 #define mmHPD0_DC_HPD_CONTROL 0x189A 99 #define mmHPD1_DC_HPD_CONTROL 0x18A2 100 #define mmHPD2_DC_HPD_CONTROL 0x18AA 101 #define mmHPD3_DC_HPD_CONTROL 0x18B2 102 #define mmHPD4_DC_HPD_CONTROL 0x18BA 103 #define mmHPD5_DC_HPD_CONTROL 0x18C2 104 #endif 105 106 #define DCE11_DIG_FE_CNTL 0x4a00 107 #define DCE11_DIG_BE_CNTL 0x4a47 108 #define DCE11_DP_SEC 0x4ac3 109 110 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 111 { 112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 114 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 115 - mmDPG_WATERMARK_MASK_CONTROL), 116 }, 117 { 118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 120 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 121 - mmDPG_WATERMARK_MASK_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 127 - mmDPG_WATERMARK_MASK_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 133 - mmDPG_WATERMARK_MASK_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 138 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 139 - mmDPG_WATERMARK_MASK_CONTROL), 140 }, 141 { 142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 144 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 145 - mmDPG_WATERMARK_MASK_CONTROL), 146 } 147 }; 148 149 /* set register offset */ 150 #define SR(reg_name)\ 151 .reg_name = mm ## reg_name 152 153 /* set register offset with instance */ 154 #define SRI(reg_name, block, id)\ 155 .reg_name = mm ## block ## id ## _ ## reg_name 156 157 158 static const struct clk_mgr_registers disp_clk_regs = { 159 CLK_COMMON_REG_LIST_DCE_BASE() 160 }; 161 162 static const struct clk_mgr_shift disp_clk_shift = { 163 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 164 }; 165 166 static const struct clk_mgr_mask disp_clk_mask = { 167 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 168 }; 169 170 #define ipp_regs(id)\ 171 [id] = {\ 172 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 173 } 174 175 static const struct dce_ipp_registers ipp_regs[] = { 176 ipp_regs(0), 177 ipp_regs(1), 178 ipp_regs(2), 179 ipp_regs(3), 180 ipp_regs(4), 181 ipp_regs(5) 182 }; 183 184 static const struct dce_ipp_shift ipp_shift = { 185 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 186 }; 187 188 static const struct dce_ipp_mask ipp_mask = { 189 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 190 }; 191 192 #define transform_regs(id)\ 193 [id] = {\ 194 XFM_COMMON_REG_LIST_DCE80(id)\ 195 } 196 197 static const struct dce_transform_registers xfm_regs[] = { 198 transform_regs(0), 199 transform_regs(1), 200 transform_regs(2), 201 transform_regs(3), 202 transform_regs(4), 203 transform_regs(5) 204 }; 205 206 static const struct dce_transform_shift xfm_shift = { 207 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 208 }; 209 210 static const struct dce_transform_mask xfm_mask = { 211 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 212 }; 213 214 #define aux_regs(id)\ 215 [id] = {\ 216 AUX_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 220 aux_regs(0), 221 aux_regs(1), 222 aux_regs(2), 223 aux_regs(3), 224 aux_regs(4), 225 aux_regs(5) 226 }; 227 228 #define hpd_regs(id)\ 229 [id] = {\ 230 HPD_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 234 hpd_regs(0), 235 hpd_regs(1), 236 hpd_regs(2), 237 hpd_regs(3), 238 hpd_regs(4), 239 hpd_regs(5) 240 }; 241 242 #define link_regs(id)\ 243 [id] = {\ 244 LE_DCE80_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_registers link_enc_regs[] = { 248 link_regs(0), 249 link_regs(1), 250 link_regs(2), 251 link_regs(3), 252 link_regs(4), 253 link_regs(5), 254 link_regs(6), 255 }; 256 257 #define stream_enc_regs(id)\ 258 [id] = {\ 259 SE_COMMON_REG_LIST_DCE_BASE(id),\ 260 .AFMT_CNTL = 0,\ 261 } 262 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 264 stream_enc_regs(0), 265 stream_enc_regs(1), 266 stream_enc_regs(2), 267 stream_enc_regs(3), 268 stream_enc_regs(4), 269 stream_enc_regs(5), 270 stream_enc_regs(6) 271 }; 272 273 static const struct dce_stream_encoder_shift se_shift = { 274 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 275 }; 276 277 static const struct dce_stream_encoder_mask se_mask = { 278 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 279 }; 280 281 #define opp_regs(id)\ 282 [id] = {\ 283 OPP_DCE_80_REG_LIST(id),\ 284 } 285 286 static const struct dce_opp_registers opp_regs[] = { 287 opp_regs(0), 288 opp_regs(1), 289 opp_regs(2), 290 opp_regs(3), 291 opp_regs(4), 292 opp_regs(5) 293 }; 294 295 static const struct dce_opp_shift opp_shift = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 297 }; 298 299 static const struct dce_opp_mask opp_mask = { 300 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 301 }; 302 303 #define aux_engine_regs(id)\ 304 [id] = {\ 305 AUX_COMMON_REG_LIST(id), \ 306 .AUX_RESET_MASK = 0 \ 307 } 308 309 static const struct dce110_aux_registers aux_engine_regs[] = { 310 aux_engine_regs(0), 311 aux_engine_regs(1), 312 aux_engine_regs(2), 313 aux_engine_regs(3), 314 aux_engine_regs(4), 315 aux_engine_regs(5) 316 }; 317 318 #define audio_regs(id)\ 319 [id] = {\ 320 AUD_COMMON_REG_LIST(id)\ 321 } 322 323 static const struct dce_audio_registers audio_regs[] = { 324 audio_regs(0), 325 audio_regs(1), 326 audio_regs(2), 327 audio_regs(3), 328 audio_regs(4), 329 audio_regs(5), 330 audio_regs(6), 331 }; 332 333 static const struct dce_audio_shift audio_shift = { 334 AUD_COMMON_MASK_SH_LIST(__SHIFT) 335 }; 336 337 static const struct dce_aduio_mask audio_mask = { 338 AUD_COMMON_MASK_SH_LIST(_MASK) 339 }; 340 341 #define clk_src_regs(id)\ 342 [id] = {\ 343 CS_COMMON_REG_LIST_DCE_80(id),\ 344 } 345 346 347 static const struct dce110_clk_src_regs clk_src_regs[] = { 348 clk_src_regs(0), 349 clk_src_regs(1), 350 clk_src_regs(2) 351 }; 352 353 static const struct dce110_clk_src_shift cs_shift = { 354 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 355 }; 356 357 static const struct dce110_clk_src_mask cs_mask = { 358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 359 }; 360 361 static const struct bios_registers bios_regs = { 362 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 363 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 364 }; 365 366 static const struct resource_caps res_cap = { 367 .num_timing_generator = 6, 368 .num_audio = 6, 369 .num_stream_encoder = 6, 370 .num_pll = 3, 371 .num_ddc = 6, 372 }; 373 374 static const struct resource_caps res_cap_81 = { 375 .num_timing_generator = 4, 376 .num_audio = 7, 377 .num_stream_encoder = 7, 378 .num_pll = 3, 379 .num_ddc = 6, 380 }; 381 382 static const struct resource_caps res_cap_83 = { 383 .num_timing_generator = 2, 384 .num_audio = 6, 385 .num_stream_encoder = 6, 386 .num_pll = 2, 387 .num_ddc = 2, 388 }; 389 390 static const struct dc_plane_cap plane_cap = { 391 .type = DC_PLANE_TYPE_DCE_RGB, 392 .supports_argb8888 = true, 393 }; 394 395 static const struct dce_dmcu_registers dmcu_regs = { 396 DMCU_DCE80_REG_LIST() 397 }; 398 399 static const struct dce_dmcu_shift dmcu_shift = { 400 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 401 }; 402 403 static const struct dce_dmcu_mask dmcu_mask = { 404 DMCU_MASK_SH_LIST_DCE80(_MASK) 405 }; 406 static const struct dce_abm_registers abm_regs = { 407 ABM_DCE110_COMMON_REG_LIST() 408 }; 409 410 static const struct dce_abm_shift abm_shift = { 411 ABM_MASK_SH_LIST_DCE110(__SHIFT) 412 }; 413 414 static const struct dce_abm_mask abm_mask = { 415 ABM_MASK_SH_LIST_DCE110(_MASK) 416 }; 417 418 #define CTX ctx 419 #define REG(reg) mm ## reg 420 421 #ifndef mmCC_DC_HDMI_STRAPS 422 #define mmCC_DC_HDMI_STRAPS 0x1918 423 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 424 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 425 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 426 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 427 #endif 428 429 static void read_dce_straps( 430 struct dc_context *ctx, 431 struct resource_straps *straps) 432 { 433 REG_GET_2(CC_DC_HDMI_STRAPS, 434 HDMI_DISABLE, &straps->hdmi_disable, 435 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 436 437 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 438 } 439 440 static struct audio *create_audio( 441 struct dc_context *ctx, unsigned int inst) 442 { 443 return dce_audio_create(ctx, inst, 444 &audio_regs[inst], &audio_shift, &audio_mask); 445 } 446 447 static struct timing_generator *dce80_timing_generator_create( 448 struct dc_context *ctx, 449 uint32_t instance, 450 const struct dce110_timing_generator_offsets *offsets) 451 { 452 struct dce110_timing_generator *tg110 = 453 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 454 455 if (!tg110) 456 return NULL; 457 458 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 459 return &tg110->base; 460 } 461 462 static struct output_pixel_processor *dce80_opp_create( 463 struct dc_context *ctx, 464 uint32_t inst) 465 { 466 struct dce110_opp *opp = 467 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 468 469 if (!opp) 470 return NULL; 471 472 dce110_opp_construct(opp, 473 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 474 return &opp->base; 475 } 476 477 struct dce_aux *dce80_aux_engine_create( 478 struct dc_context *ctx, 479 uint32_t inst) 480 { 481 struct aux_engine_dce110 *aux_engine = 482 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 483 484 if (!aux_engine) 485 return NULL; 486 487 dce110_aux_engine_construct(aux_engine, ctx, inst, 488 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 489 &aux_engine_regs[inst]); 490 491 return &aux_engine->base; 492 } 493 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 494 495 static const struct dce_i2c_registers i2c_hw_regs[] = { 496 i2c_inst_regs(1), 497 i2c_inst_regs(2), 498 i2c_inst_regs(3), 499 i2c_inst_regs(4), 500 i2c_inst_regs(5), 501 i2c_inst_regs(6), 502 }; 503 504 static const struct dce_i2c_shift i2c_shifts = { 505 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 506 }; 507 508 static const struct dce_i2c_mask i2c_masks = { 509 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 510 }; 511 512 struct dce_i2c_hw *dce80_i2c_hw_create( 513 struct dc_context *ctx, 514 uint32_t inst) 515 { 516 struct dce_i2c_hw *dce_i2c_hw = 517 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 518 519 if (!dce_i2c_hw) 520 return NULL; 521 522 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 523 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 524 525 return dce_i2c_hw; 526 } 527 528 struct dce_i2c_sw *dce80_i2c_sw_create( 529 struct dc_context *ctx) 530 { 531 struct dce_i2c_sw *dce_i2c_sw = 532 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 533 534 if (!dce_i2c_sw) 535 return NULL; 536 537 dce_i2c_sw_construct(dce_i2c_sw, ctx); 538 539 return dce_i2c_sw; 540 } 541 static struct stream_encoder *dce80_stream_encoder_create( 542 enum engine_id eng_id, 543 struct dc_context *ctx) 544 { 545 struct dce110_stream_encoder *enc110 = 546 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 547 548 if (!enc110) 549 return NULL; 550 551 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 552 &stream_enc_regs[eng_id], 553 &se_shift, &se_mask); 554 return &enc110->base; 555 } 556 557 #define SRII(reg_name, block, id)\ 558 .reg_name[id] = mm ## block ## id ## _ ## reg_name 559 560 static const struct dce_hwseq_registers hwseq_reg = { 561 HWSEQ_DCE8_REG_LIST() 562 }; 563 564 static const struct dce_hwseq_shift hwseq_shift = { 565 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 566 }; 567 568 static const struct dce_hwseq_mask hwseq_mask = { 569 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 570 }; 571 572 static struct dce_hwseq *dce80_hwseq_create( 573 struct dc_context *ctx) 574 { 575 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 576 577 if (hws) { 578 hws->ctx = ctx; 579 hws->regs = &hwseq_reg; 580 hws->shifts = &hwseq_shift; 581 hws->masks = &hwseq_mask; 582 } 583 return hws; 584 } 585 586 static const struct resource_create_funcs res_create_funcs = { 587 .read_dce_straps = read_dce_straps, 588 .create_audio = create_audio, 589 .create_stream_encoder = dce80_stream_encoder_create, 590 .create_hwseq = dce80_hwseq_create, 591 }; 592 593 #define mi_inst_regs(id) { \ 594 MI_DCE8_REG_LIST(id), \ 595 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 596 } 597 static const struct dce_mem_input_registers mi_regs[] = { 598 mi_inst_regs(0), 599 mi_inst_regs(1), 600 mi_inst_regs(2), 601 mi_inst_regs(3), 602 mi_inst_regs(4), 603 mi_inst_regs(5), 604 }; 605 606 static const struct dce_mem_input_shift mi_shifts = { 607 MI_DCE8_MASK_SH_LIST(__SHIFT), 608 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 609 }; 610 611 static const struct dce_mem_input_mask mi_masks = { 612 MI_DCE8_MASK_SH_LIST(_MASK), 613 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 614 }; 615 616 static struct mem_input *dce80_mem_input_create( 617 struct dc_context *ctx, 618 uint32_t inst) 619 { 620 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 621 GFP_KERNEL); 622 623 if (!dce_mi) { 624 BREAK_TO_DEBUGGER(); 625 return NULL; 626 } 627 628 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 629 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 630 return &dce_mi->base; 631 } 632 633 static void dce80_transform_destroy(struct transform **xfm) 634 { 635 kfree(TO_DCE_TRANSFORM(*xfm)); 636 *xfm = NULL; 637 } 638 639 static struct transform *dce80_transform_create( 640 struct dc_context *ctx, 641 uint32_t inst) 642 { 643 struct dce_transform *transform = 644 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 645 646 if (!transform) 647 return NULL; 648 649 dce_transform_construct(transform, ctx, inst, 650 &xfm_regs[inst], &xfm_shift, &xfm_mask); 651 transform->prescaler_on = false; 652 return &transform->base; 653 } 654 655 static const struct encoder_feature_support link_enc_feature = { 656 .max_hdmi_deep_color = COLOR_DEPTH_121212, 657 .max_hdmi_pixel_clock = 297000, 658 .flags.bits.IS_HBR2_CAPABLE = true, 659 .flags.bits.IS_TPS3_CAPABLE = true 660 }; 661 662 struct link_encoder *dce80_link_encoder_create( 663 const struct encoder_init_data *enc_init_data) 664 { 665 struct dce110_link_encoder *enc110 = 666 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 667 668 if (!enc110) 669 return NULL; 670 671 dce110_link_encoder_construct(enc110, 672 enc_init_data, 673 &link_enc_feature, 674 &link_enc_regs[enc_init_data->transmitter], 675 &link_enc_aux_regs[enc_init_data->channel - 1], 676 &link_enc_hpd_regs[enc_init_data->hpd_source]); 677 return &enc110->base; 678 } 679 680 struct clock_source *dce80_clock_source_create( 681 struct dc_context *ctx, 682 struct dc_bios *bios, 683 enum clock_source_id id, 684 const struct dce110_clk_src_regs *regs, 685 bool dp_clk_src) 686 { 687 struct dce110_clk_src *clk_src = 688 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 689 690 if (!clk_src) 691 return NULL; 692 693 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 694 regs, &cs_shift, &cs_mask)) { 695 clk_src->base.dp_clk_src = dp_clk_src; 696 return &clk_src->base; 697 } 698 699 BREAK_TO_DEBUGGER(); 700 return NULL; 701 } 702 703 void dce80_clock_source_destroy(struct clock_source **clk_src) 704 { 705 kfree(TO_DCE110_CLK_SRC(*clk_src)); 706 *clk_src = NULL; 707 } 708 709 static struct input_pixel_processor *dce80_ipp_create( 710 struct dc_context *ctx, uint32_t inst) 711 { 712 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 713 714 if (!ipp) { 715 BREAK_TO_DEBUGGER(); 716 return NULL; 717 } 718 719 dce_ipp_construct(ipp, ctx, inst, 720 &ipp_regs[inst], &ipp_shift, &ipp_mask); 721 return &ipp->base; 722 } 723 724 static void destruct(struct dce110_resource_pool *pool) 725 { 726 unsigned int i; 727 728 for (i = 0; i < pool->base.pipe_count; i++) { 729 if (pool->base.opps[i] != NULL) 730 dce110_opp_destroy(&pool->base.opps[i]); 731 732 if (pool->base.transforms[i] != NULL) 733 dce80_transform_destroy(&pool->base.transforms[i]); 734 735 if (pool->base.ipps[i] != NULL) 736 dce_ipp_destroy(&pool->base.ipps[i]); 737 738 if (pool->base.mis[i] != NULL) { 739 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 740 pool->base.mis[i] = NULL; 741 } 742 743 if (pool->base.timing_generators[i] != NULL) { 744 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 745 pool->base.timing_generators[i] = NULL; 746 } 747 } 748 749 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 750 if (pool->base.engines[i] != NULL) 751 dce110_engine_destroy(&pool->base.engines[i]); 752 if (pool->base.hw_i2cs[i] != NULL) { 753 kfree(pool->base.hw_i2cs[i]); 754 pool->base.hw_i2cs[i] = NULL; 755 } 756 if (pool->base.sw_i2cs[i] != NULL) { 757 kfree(pool->base.sw_i2cs[i]); 758 pool->base.sw_i2cs[i] = NULL; 759 } 760 } 761 762 for (i = 0; i < pool->base.stream_enc_count; i++) { 763 if (pool->base.stream_enc[i] != NULL) 764 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 765 } 766 767 for (i = 0; i < pool->base.clk_src_count; i++) { 768 if (pool->base.clock_sources[i] != NULL) { 769 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 770 } 771 } 772 773 if (pool->base.abm != NULL) 774 dce_abm_destroy(&pool->base.abm); 775 776 if (pool->base.dmcu != NULL) 777 dce_dmcu_destroy(&pool->base.dmcu); 778 779 if (pool->base.dp_clock_source != NULL) 780 dce80_clock_source_destroy(&pool->base.dp_clock_source); 781 782 for (i = 0; i < pool->base.audio_count; i++) { 783 if (pool->base.audios[i] != NULL) { 784 dce_aud_destroy(&pool->base.audios[i]); 785 } 786 } 787 788 if (pool->base.clk_mgr != NULL) 789 dce_clk_mgr_destroy(&pool->base.clk_mgr); 790 791 if (pool->base.irqs != NULL) { 792 dal_irq_service_destroy(&pool->base.irqs); 793 } 794 } 795 796 bool dce80_validate_bandwidth( 797 struct dc *dc, 798 struct dc_state *context) 799 { 800 int i; 801 bool at_least_one_pipe = false; 802 803 for (i = 0; i < dc->res_pool->pipe_count; i++) { 804 if (context->res_ctx.pipe_ctx[i].stream) 805 at_least_one_pipe = true; 806 } 807 808 if (at_least_one_pipe) { 809 /* TODO implement when needed but for now hardcode max value*/ 810 context->bw.dce.dispclk_khz = 681000; 811 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 812 } else { 813 context->bw.dce.dispclk_khz = 0; 814 context->bw.dce.yclk_khz = 0; 815 } 816 817 return true; 818 } 819 820 static bool dce80_validate_surface_sets( 821 struct dc_state *context) 822 { 823 int i; 824 825 for (i = 0; i < context->stream_count; i++) { 826 if (context->stream_status[i].plane_count == 0) 827 continue; 828 829 if (context->stream_status[i].plane_count > 1) 830 return false; 831 832 if (context->stream_status[i].plane_states[0]->format 833 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 834 return false; 835 } 836 837 return true; 838 } 839 840 enum dc_status dce80_validate_global( 841 struct dc *dc, 842 struct dc_state *context) 843 { 844 if (!dce80_validate_surface_sets(context)) 845 return DC_FAIL_SURFACE_VALIDATE; 846 847 return DC_OK; 848 } 849 850 static void dce80_destroy_resource_pool(struct resource_pool **pool) 851 { 852 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 853 854 destruct(dce110_pool); 855 kfree(dce110_pool); 856 *pool = NULL; 857 } 858 859 static const struct resource_funcs dce80_res_pool_funcs = { 860 .destroy = dce80_destroy_resource_pool, 861 .link_enc_create = dce80_link_encoder_create, 862 .validate_bandwidth = dce80_validate_bandwidth, 863 .validate_plane = dce100_validate_plane, 864 .add_stream_to_ctx = dce100_add_stream_to_ctx, 865 .validate_global = dce80_validate_global 866 }; 867 868 static bool dce80_construct( 869 uint8_t num_virtual_links, 870 struct dc *dc, 871 struct dce110_resource_pool *pool) 872 { 873 unsigned int i; 874 struct dc_context *ctx = dc->ctx; 875 struct dc_firmware_info info; 876 struct dc_bios *bp; 877 878 ctx->dc_bios->regs = &bios_regs; 879 880 pool->base.res_cap = &res_cap; 881 pool->base.funcs = &dce80_res_pool_funcs; 882 883 884 /************************************************* 885 * Resource + asic cap harcoding * 886 *************************************************/ 887 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 888 pool->base.pipe_count = res_cap.num_timing_generator; 889 pool->base.timing_generator_count = res_cap.num_timing_generator; 890 dc->caps.max_downscale_ratio = 200; 891 dc->caps.i2c_speed_in_khz = 40; 892 dc->caps.max_cursor_size = 128; 893 dc->caps.dual_link_dvi = true; 894 895 /************************************************* 896 * Create resources * 897 *************************************************/ 898 899 bp = ctx->dc_bios; 900 901 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 902 info.external_clock_source_frequency_for_dp != 0) { 903 pool->base.dp_clock_source = 904 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 905 906 pool->base.clock_sources[0] = 907 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 908 pool->base.clock_sources[1] = 909 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 910 pool->base.clock_sources[2] = 911 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 912 pool->base.clk_src_count = 3; 913 914 } else { 915 pool->base.dp_clock_source = 916 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 917 918 pool->base.clock_sources[0] = 919 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 920 pool->base.clock_sources[1] = 921 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 922 pool->base.clk_src_count = 2; 923 } 924 925 if (pool->base.dp_clock_source == NULL) { 926 dm_error("DC: failed to create dp clock source!\n"); 927 BREAK_TO_DEBUGGER(); 928 goto res_create_fail; 929 } 930 931 for (i = 0; i < pool->base.clk_src_count; i++) { 932 if (pool->base.clock_sources[i] == NULL) { 933 dm_error("DC: failed to create clock sources!\n"); 934 BREAK_TO_DEBUGGER(); 935 goto res_create_fail; 936 } 937 } 938 939 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 940 &disp_clk_regs, 941 &disp_clk_shift, 942 &disp_clk_mask); 943 if (pool->base.clk_mgr == NULL) { 944 dm_error("DC: failed to create display clock!\n"); 945 BREAK_TO_DEBUGGER(); 946 goto res_create_fail; 947 } 948 949 pool->base.dmcu = dce_dmcu_create(ctx, 950 &dmcu_regs, 951 &dmcu_shift, 952 &dmcu_mask); 953 if (pool->base.dmcu == NULL) { 954 dm_error("DC: failed to create dmcu!\n"); 955 BREAK_TO_DEBUGGER(); 956 goto res_create_fail; 957 } 958 959 pool->base.abm = dce_abm_create(ctx, 960 &abm_regs, 961 &abm_shift, 962 &abm_mask); 963 if (pool->base.abm == NULL) { 964 dm_error("DC: failed to create abm!\n"); 965 BREAK_TO_DEBUGGER(); 966 goto res_create_fail; 967 } 968 969 { 970 struct irq_service_init_data init_data; 971 init_data.ctx = dc->ctx; 972 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 973 if (!pool->base.irqs) 974 goto res_create_fail; 975 } 976 977 for (i = 0; i < pool->base.pipe_count; i++) { 978 pool->base.timing_generators[i] = dce80_timing_generator_create( 979 ctx, i, &dce80_tg_offsets[i]); 980 if (pool->base.timing_generators[i] == NULL) { 981 BREAK_TO_DEBUGGER(); 982 dm_error("DC: failed to create tg!\n"); 983 goto res_create_fail; 984 } 985 986 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 987 if (pool->base.mis[i] == NULL) { 988 BREAK_TO_DEBUGGER(); 989 dm_error("DC: failed to create memory input!\n"); 990 goto res_create_fail; 991 } 992 993 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 994 if (pool->base.ipps[i] == NULL) { 995 BREAK_TO_DEBUGGER(); 996 dm_error("DC: failed to create input pixel processor!\n"); 997 goto res_create_fail; 998 } 999 1000 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1001 if (pool->base.transforms[i] == NULL) { 1002 BREAK_TO_DEBUGGER(); 1003 dm_error("DC: failed to create transform!\n"); 1004 goto res_create_fail; 1005 } 1006 1007 pool->base.opps[i] = dce80_opp_create(ctx, i); 1008 if (pool->base.opps[i] == NULL) { 1009 BREAK_TO_DEBUGGER(); 1010 dm_error("DC: failed to create output pixel processor!\n"); 1011 goto res_create_fail; 1012 } 1013 } 1014 1015 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1016 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1017 if (pool->base.engines[i] == NULL) { 1018 BREAK_TO_DEBUGGER(); 1019 dm_error( 1020 "DC:failed to create aux engine!!\n"); 1021 goto res_create_fail; 1022 } 1023 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1024 if (pool->base.hw_i2cs[i] == NULL) { 1025 BREAK_TO_DEBUGGER(); 1026 dm_error( 1027 "DC:failed to create i2c engine!!\n"); 1028 goto res_create_fail; 1029 } 1030 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1031 if (pool->base.sw_i2cs[i] == NULL) { 1032 BREAK_TO_DEBUGGER(); 1033 dm_error( 1034 "DC:failed to create sw i2c!!\n"); 1035 goto res_create_fail; 1036 } 1037 } 1038 1039 dc->caps.max_planes = pool->base.pipe_count; 1040 1041 for (i = 0; i < dc->caps.max_planes; ++i) 1042 dc->caps.planes[i] = plane_cap; 1043 1044 dc->caps.disable_dp_clk_share = true; 1045 1046 if (!resource_construct(num_virtual_links, dc, &pool->base, 1047 &res_create_funcs)) 1048 goto res_create_fail; 1049 1050 /* Create hardware sequencer */ 1051 dce80_hw_sequencer_construct(dc); 1052 1053 return true; 1054 1055 res_create_fail: 1056 destruct(pool); 1057 return false; 1058 } 1059 1060 struct resource_pool *dce80_create_resource_pool( 1061 uint8_t num_virtual_links, 1062 struct dc *dc) 1063 { 1064 struct dce110_resource_pool *pool = 1065 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1066 1067 if (!pool) 1068 return NULL; 1069 1070 if (dce80_construct(num_virtual_links, dc, pool)) 1071 return &pool->base; 1072 1073 BREAK_TO_DEBUGGER(); 1074 return NULL; 1075 } 1076 1077 static bool dce81_construct( 1078 uint8_t num_virtual_links, 1079 struct dc *dc, 1080 struct dce110_resource_pool *pool) 1081 { 1082 unsigned int i; 1083 struct dc_context *ctx = dc->ctx; 1084 struct dc_firmware_info info; 1085 struct dc_bios *bp; 1086 1087 ctx->dc_bios->regs = &bios_regs; 1088 1089 pool->base.res_cap = &res_cap_81; 1090 pool->base.funcs = &dce80_res_pool_funcs; 1091 1092 1093 /************************************************* 1094 * Resource + asic cap harcoding * 1095 *************************************************/ 1096 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1097 pool->base.pipe_count = res_cap_81.num_timing_generator; 1098 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1099 dc->caps.max_downscale_ratio = 200; 1100 dc->caps.i2c_speed_in_khz = 40; 1101 dc->caps.max_cursor_size = 128; 1102 dc->caps.is_apu = true; 1103 1104 /************************************************* 1105 * Create resources * 1106 *************************************************/ 1107 1108 bp = ctx->dc_bios; 1109 1110 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1111 info.external_clock_source_frequency_for_dp != 0) { 1112 pool->base.dp_clock_source = 1113 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1114 1115 pool->base.clock_sources[0] = 1116 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1117 pool->base.clock_sources[1] = 1118 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1119 pool->base.clock_sources[2] = 1120 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1121 pool->base.clk_src_count = 3; 1122 1123 } else { 1124 pool->base.dp_clock_source = 1125 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1126 1127 pool->base.clock_sources[0] = 1128 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1129 pool->base.clock_sources[1] = 1130 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1131 pool->base.clk_src_count = 2; 1132 } 1133 1134 if (pool->base.dp_clock_source == NULL) { 1135 dm_error("DC: failed to create dp clock source!\n"); 1136 BREAK_TO_DEBUGGER(); 1137 goto res_create_fail; 1138 } 1139 1140 for (i = 0; i < pool->base.clk_src_count; i++) { 1141 if (pool->base.clock_sources[i] == NULL) { 1142 dm_error("DC: failed to create clock sources!\n"); 1143 BREAK_TO_DEBUGGER(); 1144 goto res_create_fail; 1145 } 1146 } 1147 1148 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 1149 &disp_clk_regs, 1150 &disp_clk_shift, 1151 &disp_clk_mask); 1152 if (pool->base.clk_mgr == NULL) { 1153 dm_error("DC: failed to create display clock!\n"); 1154 BREAK_TO_DEBUGGER(); 1155 goto res_create_fail; 1156 } 1157 1158 pool->base.dmcu = dce_dmcu_create(ctx, 1159 &dmcu_regs, 1160 &dmcu_shift, 1161 &dmcu_mask); 1162 if (pool->base.dmcu == NULL) { 1163 dm_error("DC: failed to create dmcu!\n"); 1164 BREAK_TO_DEBUGGER(); 1165 goto res_create_fail; 1166 } 1167 1168 pool->base.abm = dce_abm_create(ctx, 1169 &abm_regs, 1170 &abm_shift, 1171 &abm_mask); 1172 if (pool->base.abm == NULL) { 1173 dm_error("DC: failed to create abm!\n"); 1174 BREAK_TO_DEBUGGER(); 1175 goto res_create_fail; 1176 } 1177 1178 { 1179 struct irq_service_init_data init_data; 1180 init_data.ctx = dc->ctx; 1181 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1182 if (!pool->base.irqs) 1183 goto res_create_fail; 1184 } 1185 1186 for (i = 0; i < pool->base.pipe_count; i++) { 1187 pool->base.timing_generators[i] = dce80_timing_generator_create( 1188 ctx, i, &dce80_tg_offsets[i]); 1189 if (pool->base.timing_generators[i] == NULL) { 1190 BREAK_TO_DEBUGGER(); 1191 dm_error("DC: failed to create tg!\n"); 1192 goto res_create_fail; 1193 } 1194 1195 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1196 if (pool->base.mis[i] == NULL) { 1197 BREAK_TO_DEBUGGER(); 1198 dm_error("DC: failed to create memory input!\n"); 1199 goto res_create_fail; 1200 } 1201 1202 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1203 if (pool->base.ipps[i] == NULL) { 1204 BREAK_TO_DEBUGGER(); 1205 dm_error("DC: failed to create input pixel processor!\n"); 1206 goto res_create_fail; 1207 } 1208 1209 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1210 if (pool->base.transforms[i] == NULL) { 1211 BREAK_TO_DEBUGGER(); 1212 dm_error("DC: failed to create transform!\n"); 1213 goto res_create_fail; 1214 } 1215 1216 pool->base.opps[i] = dce80_opp_create(ctx, i); 1217 if (pool->base.opps[i] == NULL) { 1218 BREAK_TO_DEBUGGER(); 1219 dm_error("DC: failed to create output pixel processor!\n"); 1220 goto res_create_fail; 1221 } 1222 } 1223 1224 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1225 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1226 if (pool->base.engines[i] == NULL) { 1227 BREAK_TO_DEBUGGER(); 1228 dm_error( 1229 "DC:failed to create aux engine!!\n"); 1230 goto res_create_fail; 1231 } 1232 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1233 if (pool->base.hw_i2cs[i] == NULL) { 1234 BREAK_TO_DEBUGGER(); 1235 dm_error( 1236 "DC:failed to create i2c engine!!\n"); 1237 goto res_create_fail; 1238 } 1239 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1240 if (pool->base.sw_i2cs[i] == NULL) { 1241 BREAK_TO_DEBUGGER(); 1242 dm_error( 1243 "DC:failed to create sw i2c!!\n"); 1244 goto res_create_fail; 1245 } 1246 } 1247 1248 dc->caps.max_planes = pool->base.pipe_count; 1249 1250 for (i = 0; i < dc->caps.max_planes; ++i) 1251 dc->caps.planes[i] = plane_cap; 1252 1253 dc->caps.disable_dp_clk_share = true; 1254 1255 if (!resource_construct(num_virtual_links, dc, &pool->base, 1256 &res_create_funcs)) 1257 goto res_create_fail; 1258 1259 /* Create hardware sequencer */ 1260 dce80_hw_sequencer_construct(dc); 1261 1262 return true; 1263 1264 res_create_fail: 1265 destruct(pool); 1266 return false; 1267 } 1268 1269 struct resource_pool *dce81_create_resource_pool( 1270 uint8_t num_virtual_links, 1271 struct dc *dc) 1272 { 1273 struct dce110_resource_pool *pool = 1274 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1275 1276 if (!pool) 1277 return NULL; 1278 1279 if (dce81_construct(num_virtual_links, dc, pool)) 1280 return &pool->base; 1281 1282 BREAK_TO_DEBUGGER(); 1283 return NULL; 1284 } 1285 1286 static bool dce83_construct( 1287 uint8_t num_virtual_links, 1288 struct dc *dc, 1289 struct dce110_resource_pool *pool) 1290 { 1291 unsigned int i; 1292 struct dc_context *ctx = dc->ctx; 1293 struct dc_firmware_info info; 1294 struct dc_bios *bp; 1295 1296 ctx->dc_bios->regs = &bios_regs; 1297 1298 pool->base.res_cap = &res_cap_83; 1299 pool->base.funcs = &dce80_res_pool_funcs; 1300 1301 1302 /************************************************* 1303 * Resource + asic cap harcoding * 1304 *************************************************/ 1305 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1306 pool->base.pipe_count = res_cap_83.num_timing_generator; 1307 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1308 dc->caps.max_downscale_ratio = 200; 1309 dc->caps.i2c_speed_in_khz = 40; 1310 dc->caps.max_cursor_size = 128; 1311 dc->caps.is_apu = true; 1312 1313 /************************************************* 1314 * Create resources * 1315 *************************************************/ 1316 1317 bp = ctx->dc_bios; 1318 1319 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1320 info.external_clock_source_frequency_for_dp != 0) { 1321 pool->base.dp_clock_source = 1322 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1323 1324 pool->base.clock_sources[0] = 1325 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1326 pool->base.clock_sources[1] = 1327 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1328 pool->base.clk_src_count = 2; 1329 1330 } else { 1331 pool->base.dp_clock_source = 1332 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1333 1334 pool->base.clock_sources[0] = 1335 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1336 pool->base.clk_src_count = 1; 1337 } 1338 1339 if (pool->base.dp_clock_source == NULL) { 1340 dm_error("DC: failed to create dp clock source!\n"); 1341 BREAK_TO_DEBUGGER(); 1342 goto res_create_fail; 1343 } 1344 1345 for (i = 0; i < pool->base.clk_src_count; i++) { 1346 if (pool->base.clock_sources[i] == NULL) { 1347 dm_error("DC: failed to create clock sources!\n"); 1348 BREAK_TO_DEBUGGER(); 1349 goto res_create_fail; 1350 } 1351 } 1352 1353 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 1354 &disp_clk_regs, 1355 &disp_clk_shift, 1356 &disp_clk_mask); 1357 if (pool->base.clk_mgr == NULL) { 1358 dm_error("DC: failed to create display clock!\n"); 1359 BREAK_TO_DEBUGGER(); 1360 goto res_create_fail; 1361 } 1362 1363 pool->base.dmcu = dce_dmcu_create(ctx, 1364 &dmcu_regs, 1365 &dmcu_shift, 1366 &dmcu_mask); 1367 if (pool->base.dmcu == NULL) { 1368 dm_error("DC: failed to create dmcu!\n"); 1369 BREAK_TO_DEBUGGER(); 1370 goto res_create_fail; 1371 } 1372 1373 pool->base.abm = dce_abm_create(ctx, 1374 &abm_regs, 1375 &abm_shift, 1376 &abm_mask); 1377 if (pool->base.abm == NULL) { 1378 dm_error("DC: failed to create abm!\n"); 1379 BREAK_TO_DEBUGGER(); 1380 goto res_create_fail; 1381 } 1382 1383 { 1384 struct irq_service_init_data init_data; 1385 init_data.ctx = dc->ctx; 1386 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1387 if (!pool->base.irqs) 1388 goto res_create_fail; 1389 } 1390 1391 for (i = 0; i < pool->base.pipe_count; i++) { 1392 pool->base.timing_generators[i] = dce80_timing_generator_create( 1393 ctx, i, &dce80_tg_offsets[i]); 1394 if (pool->base.timing_generators[i] == NULL) { 1395 BREAK_TO_DEBUGGER(); 1396 dm_error("DC: failed to create tg!\n"); 1397 goto res_create_fail; 1398 } 1399 1400 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1401 if (pool->base.mis[i] == NULL) { 1402 BREAK_TO_DEBUGGER(); 1403 dm_error("DC: failed to create memory input!\n"); 1404 goto res_create_fail; 1405 } 1406 1407 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1408 if (pool->base.ipps[i] == NULL) { 1409 BREAK_TO_DEBUGGER(); 1410 dm_error("DC: failed to create input pixel processor!\n"); 1411 goto res_create_fail; 1412 } 1413 1414 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1415 if (pool->base.transforms[i] == NULL) { 1416 BREAK_TO_DEBUGGER(); 1417 dm_error("DC: failed to create transform!\n"); 1418 goto res_create_fail; 1419 } 1420 1421 pool->base.opps[i] = dce80_opp_create(ctx, i); 1422 if (pool->base.opps[i] == NULL) { 1423 BREAK_TO_DEBUGGER(); 1424 dm_error("DC: failed to create output pixel processor!\n"); 1425 goto res_create_fail; 1426 } 1427 } 1428 1429 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1430 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1431 if (pool->base.engines[i] == NULL) { 1432 BREAK_TO_DEBUGGER(); 1433 dm_error( 1434 "DC:failed to create aux engine!!\n"); 1435 goto res_create_fail; 1436 } 1437 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1438 if (pool->base.hw_i2cs[i] == NULL) { 1439 BREAK_TO_DEBUGGER(); 1440 dm_error( 1441 "DC:failed to create i2c engine!!\n"); 1442 goto res_create_fail; 1443 } 1444 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1445 if (pool->base.sw_i2cs[i] == NULL) { 1446 BREAK_TO_DEBUGGER(); 1447 dm_error( 1448 "DC:failed to create sw i2c!!\n"); 1449 goto res_create_fail; 1450 } 1451 } 1452 1453 dc->caps.max_planes = pool->base.pipe_count; 1454 1455 for (i = 0; i < dc->caps.max_planes; ++i) 1456 dc->caps.planes[i] = plane_cap; 1457 1458 dc->caps.disable_dp_clk_share = true; 1459 1460 if (!resource_construct(num_virtual_links, dc, &pool->base, 1461 &res_create_funcs)) 1462 goto res_create_fail; 1463 1464 /* Create hardware sequencer */ 1465 dce80_hw_sequencer_construct(dc); 1466 1467 return true; 1468 1469 res_create_fail: 1470 destruct(pool); 1471 return false; 1472 } 1473 1474 struct resource_pool *dce83_create_resource_pool( 1475 uint8_t num_virtual_links, 1476 struct dc *dc) 1477 { 1478 struct dce110_resource_pool *pool = 1479 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1480 1481 if (!pool) 1482 return NULL; 1483 1484 if (dce83_construct(num_virtual_links, dc, pool)) 1485 return &pool->base; 1486 1487 BREAK_TO_DEBUGGER(); 1488 return NULL; 1489 } 1490