1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_abm.h" 58 /* TODO remove this include */ 59 60 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 61 #include "gmc/gmc_7_1_d.h" 62 #include "gmc/gmc_7_1_sh_mask.h" 63 #endif 64 65 #ifndef mmDP_DPHY_INTERNAL_CTRL 66 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 74 #endif 75 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_6 0x05CF 80 #endif 81 82 #ifndef mmDP_DPHY_FAST_TRAINING 83 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 84 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 85 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 86 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 87 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 88 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 89 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 90 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 91 #endif 92 93 94 #ifndef mmHPD_DC_HPD_CONTROL 95 #define mmHPD_DC_HPD_CONTROL 0x189A 96 #define mmHPD0_DC_HPD_CONTROL 0x189A 97 #define mmHPD1_DC_HPD_CONTROL 0x18A2 98 #define mmHPD2_DC_HPD_CONTROL 0x18AA 99 #define mmHPD3_DC_HPD_CONTROL 0x18B2 100 #define mmHPD4_DC_HPD_CONTROL 0x18BA 101 #define mmHPD5_DC_HPD_CONTROL 0x18C2 102 #endif 103 104 #define DCE11_DIG_FE_CNTL 0x4a00 105 #define DCE11_DIG_BE_CNTL 0x4a47 106 #define DCE11_DP_SEC 0x4ac3 107 108 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 109 { 110 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 111 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 112 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 113 - mmDPG_WATERMARK_MASK_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 118 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 119 - mmDPG_WATERMARK_MASK_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 124 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 125 - mmDPG_WATERMARK_MASK_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 130 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 131 - mmDPG_WATERMARK_MASK_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 137 - mmDPG_WATERMARK_MASK_CONTROL), 138 }, 139 { 140 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 141 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 142 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 143 - mmDPG_WATERMARK_MASK_CONTROL), 144 } 145 }; 146 147 /* set register offset */ 148 #define SR(reg_name)\ 149 .reg_name = mm ## reg_name 150 151 /* set register offset with instance */ 152 #define SRI(reg_name, block, id)\ 153 .reg_name = mm ## block ## id ## _ ## reg_name 154 155 156 static const struct dccg_registers disp_clk_regs = { 157 CLK_COMMON_REG_LIST_DCE_BASE() 158 }; 159 160 static const struct dccg_shift disp_clk_shift = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 162 }; 163 164 static const struct dccg_mask disp_clk_mask = { 165 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 166 }; 167 168 #define ipp_regs(id)\ 169 [id] = {\ 170 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 171 } 172 173 static const struct dce_ipp_registers ipp_regs[] = { 174 ipp_regs(0), 175 ipp_regs(1), 176 ipp_regs(2), 177 ipp_regs(3), 178 ipp_regs(4), 179 ipp_regs(5) 180 }; 181 182 static const struct dce_ipp_shift ipp_shift = { 183 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 184 }; 185 186 static const struct dce_ipp_mask ipp_mask = { 187 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 188 }; 189 190 #define transform_regs(id)\ 191 [id] = {\ 192 XFM_COMMON_REG_LIST_DCE80(id)\ 193 } 194 195 static const struct dce_transform_registers xfm_regs[] = { 196 transform_regs(0), 197 transform_regs(1), 198 transform_regs(2), 199 transform_regs(3), 200 transform_regs(4), 201 transform_regs(5) 202 }; 203 204 static const struct dce_transform_shift xfm_shift = { 205 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 206 }; 207 208 static const struct dce_transform_mask xfm_mask = { 209 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 210 }; 211 212 #define aux_regs(id)\ 213 [id] = {\ 214 AUX_REG_LIST(id)\ 215 } 216 217 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 218 aux_regs(0), 219 aux_regs(1), 220 aux_regs(2), 221 aux_regs(3), 222 aux_regs(4), 223 aux_regs(5) 224 }; 225 226 #define hpd_regs(id)\ 227 [id] = {\ 228 HPD_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 232 hpd_regs(0), 233 hpd_regs(1), 234 hpd_regs(2), 235 hpd_regs(3), 236 hpd_regs(4), 237 hpd_regs(5) 238 }; 239 240 #define link_regs(id)\ 241 [id] = {\ 242 LE_DCE80_REG_LIST(id)\ 243 } 244 245 static const struct dce110_link_enc_registers link_enc_regs[] = { 246 link_regs(0), 247 link_regs(1), 248 link_regs(2), 249 link_regs(3), 250 link_regs(4), 251 link_regs(5), 252 link_regs(6), 253 }; 254 255 #define stream_enc_regs(id)\ 256 [id] = {\ 257 SE_COMMON_REG_LIST_DCE_BASE(id),\ 258 .AFMT_CNTL = 0,\ 259 } 260 261 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 262 stream_enc_regs(0), 263 stream_enc_regs(1), 264 stream_enc_regs(2), 265 stream_enc_regs(3), 266 stream_enc_regs(4), 267 stream_enc_regs(5), 268 stream_enc_regs(6) 269 }; 270 271 static const struct dce_stream_encoder_shift se_shift = { 272 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 273 }; 274 275 static const struct dce_stream_encoder_mask se_mask = { 276 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 277 }; 278 279 #define opp_regs(id)\ 280 [id] = {\ 281 OPP_DCE_80_REG_LIST(id),\ 282 } 283 284 static const struct dce_opp_registers opp_regs[] = { 285 opp_regs(0), 286 opp_regs(1), 287 opp_regs(2), 288 opp_regs(3), 289 opp_regs(4), 290 opp_regs(5) 291 }; 292 293 static const struct dce_opp_shift opp_shift = { 294 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 295 }; 296 297 static const struct dce_opp_mask opp_mask = { 298 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 299 }; 300 301 #define audio_regs(id)\ 302 [id] = {\ 303 AUD_COMMON_REG_LIST(id)\ 304 } 305 306 static const struct dce_audio_registers audio_regs[] = { 307 audio_regs(0), 308 audio_regs(1), 309 audio_regs(2), 310 audio_regs(3), 311 audio_regs(4), 312 audio_regs(5), 313 audio_regs(6), 314 }; 315 316 static const struct dce_audio_shift audio_shift = { 317 AUD_COMMON_MASK_SH_LIST(__SHIFT) 318 }; 319 320 static const struct dce_aduio_mask audio_mask = { 321 AUD_COMMON_MASK_SH_LIST(_MASK) 322 }; 323 324 #define clk_src_regs(id)\ 325 [id] = {\ 326 CS_COMMON_REG_LIST_DCE_80(id),\ 327 } 328 329 330 static const struct dce110_clk_src_regs clk_src_regs[] = { 331 clk_src_regs(0), 332 clk_src_regs(1), 333 clk_src_regs(2) 334 }; 335 336 static const struct dce110_clk_src_shift cs_shift = { 337 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 338 }; 339 340 static const struct dce110_clk_src_mask cs_mask = { 341 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 342 }; 343 344 static const struct bios_registers bios_regs = { 345 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 346 }; 347 348 static const struct resource_caps res_cap = { 349 .num_timing_generator = 6, 350 .num_audio = 6, 351 .num_stream_encoder = 6, 352 .num_pll = 3, 353 }; 354 355 static const struct resource_caps res_cap_81 = { 356 .num_timing_generator = 4, 357 .num_audio = 7, 358 .num_stream_encoder = 7, 359 .num_pll = 3, 360 }; 361 362 static const struct resource_caps res_cap_83 = { 363 .num_timing_generator = 2, 364 .num_audio = 6, 365 .num_stream_encoder = 6, 366 .num_pll = 2, 367 }; 368 369 static const struct dce_dmcu_registers dmcu_regs = { 370 DMCU_DCE80_REG_LIST() 371 }; 372 373 static const struct dce_dmcu_shift dmcu_shift = { 374 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 375 }; 376 377 static const struct dce_dmcu_mask dmcu_mask = { 378 DMCU_MASK_SH_LIST_DCE80(_MASK) 379 }; 380 static const struct dce_abm_registers abm_regs = { 381 ABM_DCE110_COMMON_REG_LIST() 382 }; 383 384 static const struct dce_abm_shift abm_shift = { 385 ABM_MASK_SH_LIST_DCE110(__SHIFT) 386 }; 387 388 static const struct dce_abm_mask abm_mask = { 389 ABM_MASK_SH_LIST_DCE110(_MASK) 390 }; 391 392 #define CTX ctx 393 #define REG(reg) mm ## reg 394 395 #ifndef mmCC_DC_HDMI_STRAPS 396 #define mmCC_DC_HDMI_STRAPS 0x1918 397 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 398 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 399 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 400 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 401 #endif 402 403 static void read_dce_straps( 404 struct dc_context *ctx, 405 struct resource_straps *straps) 406 { 407 REG_GET_2(CC_DC_HDMI_STRAPS, 408 HDMI_DISABLE, &straps->hdmi_disable, 409 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 410 411 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 412 } 413 414 static struct audio *create_audio( 415 struct dc_context *ctx, unsigned int inst) 416 { 417 return dce_audio_create(ctx, inst, 418 &audio_regs[inst], &audio_shift, &audio_mask); 419 } 420 421 static struct timing_generator *dce80_timing_generator_create( 422 struct dc_context *ctx, 423 uint32_t instance, 424 const struct dce110_timing_generator_offsets *offsets) 425 { 426 struct dce110_timing_generator *tg110 = 427 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 428 429 if (!tg110) 430 return NULL; 431 432 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 433 return &tg110->base; 434 } 435 436 static struct output_pixel_processor *dce80_opp_create( 437 struct dc_context *ctx, 438 uint32_t inst) 439 { 440 struct dce110_opp *opp = 441 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 442 443 if (!opp) 444 return NULL; 445 446 dce110_opp_construct(opp, 447 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 448 return &opp->base; 449 } 450 451 static struct stream_encoder *dce80_stream_encoder_create( 452 enum engine_id eng_id, 453 struct dc_context *ctx) 454 { 455 struct dce110_stream_encoder *enc110 = 456 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 457 458 if (!enc110) 459 return NULL; 460 461 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 462 &stream_enc_regs[eng_id], 463 &se_shift, &se_mask); 464 return &enc110->base; 465 } 466 467 #define SRII(reg_name, block, id)\ 468 .reg_name[id] = mm ## block ## id ## _ ## reg_name 469 470 static const struct dce_hwseq_registers hwseq_reg = { 471 HWSEQ_DCE8_REG_LIST() 472 }; 473 474 static const struct dce_hwseq_shift hwseq_shift = { 475 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 476 }; 477 478 static const struct dce_hwseq_mask hwseq_mask = { 479 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 480 }; 481 482 static struct dce_hwseq *dce80_hwseq_create( 483 struct dc_context *ctx) 484 { 485 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 486 487 if (hws) { 488 hws->ctx = ctx; 489 hws->regs = &hwseq_reg; 490 hws->shifts = &hwseq_shift; 491 hws->masks = &hwseq_mask; 492 } 493 return hws; 494 } 495 496 static const struct resource_create_funcs res_create_funcs = { 497 .read_dce_straps = read_dce_straps, 498 .create_audio = create_audio, 499 .create_stream_encoder = dce80_stream_encoder_create, 500 .create_hwseq = dce80_hwseq_create, 501 }; 502 503 #define mi_inst_regs(id) { \ 504 MI_DCE8_REG_LIST(id), \ 505 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 506 } 507 static const struct dce_mem_input_registers mi_regs[] = { 508 mi_inst_regs(0), 509 mi_inst_regs(1), 510 mi_inst_regs(2), 511 mi_inst_regs(3), 512 mi_inst_regs(4), 513 mi_inst_regs(5), 514 }; 515 516 static const struct dce_mem_input_shift mi_shifts = { 517 MI_DCE8_MASK_SH_LIST(__SHIFT), 518 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 519 }; 520 521 static const struct dce_mem_input_mask mi_masks = { 522 MI_DCE8_MASK_SH_LIST(_MASK), 523 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 524 }; 525 526 static struct mem_input *dce80_mem_input_create( 527 struct dc_context *ctx, 528 uint32_t inst) 529 { 530 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 531 GFP_KERNEL); 532 533 if (!dce_mi) { 534 BREAK_TO_DEBUGGER(); 535 return NULL; 536 } 537 538 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 539 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 540 return &dce_mi->base; 541 } 542 543 static void dce80_transform_destroy(struct transform **xfm) 544 { 545 kfree(TO_DCE_TRANSFORM(*xfm)); 546 *xfm = NULL; 547 } 548 549 static struct transform *dce80_transform_create( 550 struct dc_context *ctx, 551 uint32_t inst) 552 { 553 struct dce_transform *transform = 554 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 555 556 if (!transform) 557 return NULL; 558 559 dce_transform_construct(transform, ctx, inst, 560 &xfm_regs[inst], &xfm_shift, &xfm_mask); 561 transform->prescaler_on = false; 562 return &transform->base; 563 } 564 565 static const struct encoder_feature_support link_enc_feature = { 566 .max_hdmi_deep_color = COLOR_DEPTH_121212, 567 .max_hdmi_pixel_clock = 297000, 568 .flags.bits.IS_HBR2_CAPABLE = true, 569 .flags.bits.IS_TPS3_CAPABLE = true, 570 .flags.bits.IS_YCBCR_CAPABLE = true 571 }; 572 573 struct link_encoder *dce80_link_encoder_create( 574 const struct encoder_init_data *enc_init_data) 575 { 576 struct dce110_link_encoder *enc110 = 577 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 578 579 if (!enc110) 580 return NULL; 581 582 dce110_link_encoder_construct(enc110, 583 enc_init_data, 584 &link_enc_feature, 585 &link_enc_regs[enc_init_data->transmitter], 586 &link_enc_aux_regs[enc_init_data->channel - 1], 587 &link_enc_hpd_regs[enc_init_data->hpd_source]); 588 return &enc110->base; 589 } 590 591 struct clock_source *dce80_clock_source_create( 592 struct dc_context *ctx, 593 struct dc_bios *bios, 594 enum clock_source_id id, 595 const struct dce110_clk_src_regs *regs, 596 bool dp_clk_src) 597 { 598 struct dce110_clk_src *clk_src = 599 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 600 601 if (!clk_src) 602 return NULL; 603 604 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 605 regs, &cs_shift, &cs_mask)) { 606 clk_src->base.dp_clk_src = dp_clk_src; 607 return &clk_src->base; 608 } 609 610 BREAK_TO_DEBUGGER(); 611 return NULL; 612 } 613 614 void dce80_clock_source_destroy(struct clock_source **clk_src) 615 { 616 kfree(TO_DCE110_CLK_SRC(*clk_src)); 617 *clk_src = NULL; 618 } 619 620 static struct input_pixel_processor *dce80_ipp_create( 621 struct dc_context *ctx, uint32_t inst) 622 { 623 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 624 625 if (!ipp) { 626 BREAK_TO_DEBUGGER(); 627 return NULL; 628 } 629 630 dce_ipp_construct(ipp, ctx, inst, 631 &ipp_regs[inst], &ipp_shift, &ipp_mask); 632 return &ipp->base; 633 } 634 635 static void destruct(struct dce110_resource_pool *pool) 636 { 637 unsigned int i; 638 639 for (i = 0; i < pool->base.pipe_count; i++) { 640 if (pool->base.opps[i] != NULL) 641 dce110_opp_destroy(&pool->base.opps[i]); 642 643 if (pool->base.transforms[i] != NULL) 644 dce80_transform_destroy(&pool->base.transforms[i]); 645 646 if (pool->base.ipps[i] != NULL) 647 dce_ipp_destroy(&pool->base.ipps[i]); 648 649 if (pool->base.mis[i] != NULL) { 650 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 651 pool->base.mis[i] = NULL; 652 } 653 654 if (pool->base.timing_generators[i] != NULL) { 655 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 656 pool->base.timing_generators[i] = NULL; 657 } 658 } 659 660 for (i = 0; i < pool->base.stream_enc_count; i++) { 661 if (pool->base.stream_enc[i] != NULL) 662 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 663 } 664 665 for (i = 0; i < pool->base.clk_src_count; i++) { 666 if (pool->base.clock_sources[i] != NULL) { 667 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 668 } 669 } 670 671 if (pool->base.abm != NULL) 672 dce_abm_destroy(&pool->base.abm); 673 674 if (pool->base.dmcu != NULL) 675 dce_dmcu_destroy(&pool->base.dmcu); 676 677 if (pool->base.dp_clock_source != NULL) 678 dce80_clock_source_destroy(&pool->base.dp_clock_source); 679 680 for (i = 0; i < pool->base.audio_count; i++) { 681 if (pool->base.audios[i] != NULL) { 682 dce_aud_destroy(&pool->base.audios[i]); 683 } 684 } 685 686 if (pool->base.dccg != NULL) 687 dce_dccg_destroy(&pool->base.dccg); 688 689 if (pool->base.irqs != NULL) { 690 dal_irq_service_destroy(&pool->base.irqs); 691 } 692 } 693 694 bool dce80_validate_bandwidth( 695 struct dc *dc, 696 struct dc_state *context) 697 { 698 /* TODO implement when needed but for now hardcode max value*/ 699 context->bw.dce.dispclk_khz = 681000; 700 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 701 702 return true; 703 } 704 705 static bool dce80_validate_surface_sets( 706 struct dc_state *context) 707 { 708 int i; 709 710 for (i = 0; i < context->stream_count; i++) { 711 if (context->stream_status[i].plane_count == 0) 712 continue; 713 714 if (context->stream_status[i].plane_count > 1) 715 return false; 716 717 if (context->stream_status[i].plane_states[0]->format 718 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 719 return false; 720 } 721 722 return true; 723 } 724 725 enum dc_status dce80_validate_global( 726 struct dc *dc, 727 struct dc_state *context) 728 { 729 if (!dce80_validate_surface_sets(context)) 730 return DC_FAIL_SURFACE_VALIDATE; 731 732 return DC_OK; 733 } 734 735 static void dce80_destroy_resource_pool(struct resource_pool **pool) 736 { 737 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 738 739 destruct(dce110_pool); 740 kfree(dce110_pool); 741 *pool = NULL; 742 } 743 744 static const struct resource_funcs dce80_res_pool_funcs = { 745 .destroy = dce80_destroy_resource_pool, 746 .link_enc_create = dce80_link_encoder_create, 747 .validate_bandwidth = dce80_validate_bandwidth, 748 .validate_plane = dce100_validate_plane, 749 .add_stream_to_ctx = dce100_add_stream_to_ctx, 750 .validate_global = dce80_validate_global 751 }; 752 753 static bool dce80_construct( 754 uint8_t num_virtual_links, 755 struct dc *dc, 756 struct dce110_resource_pool *pool) 757 { 758 unsigned int i; 759 struct dc_context *ctx = dc->ctx; 760 struct dc_firmware_info info; 761 struct dc_bios *bp; 762 struct dm_pp_static_clock_info static_clk_info = {0}; 763 764 ctx->dc_bios->regs = &bios_regs; 765 766 pool->base.res_cap = &res_cap; 767 pool->base.funcs = &dce80_res_pool_funcs; 768 769 770 /************************************************* 771 * Resource + asic cap harcoding * 772 *************************************************/ 773 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 774 pool->base.pipe_count = res_cap.num_timing_generator; 775 pool->base.timing_generator_count = res_cap.num_timing_generator; 776 dc->caps.max_downscale_ratio = 200; 777 dc->caps.i2c_speed_in_khz = 40; 778 dc->caps.max_cursor_size = 128; 779 dc->caps.dual_link_dvi = true; 780 781 /************************************************* 782 * Create resources * 783 *************************************************/ 784 785 bp = ctx->dc_bios; 786 787 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 788 info.external_clock_source_frequency_for_dp != 0) { 789 pool->base.dp_clock_source = 790 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 791 792 pool->base.clock_sources[0] = 793 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 794 pool->base.clock_sources[1] = 795 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 796 pool->base.clock_sources[2] = 797 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 798 pool->base.clk_src_count = 3; 799 800 } else { 801 pool->base.dp_clock_source = 802 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 803 804 pool->base.clock_sources[0] = 805 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 806 pool->base.clock_sources[1] = 807 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 808 pool->base.clk_src_count = 2; 809 } 810 811 if (pool->base.dp_clock_source == NULL) { 812 dm_error("DC: failed to create dp clock source!\n"); 813 BREAK_TO_DEBUGGER(); 814 goto res_create_fail; 815 } 816 817 for (i = 0; i < pool->base.clk_src_count; i++) { 818 if (pool->base.clock_sources[i] == NULL) { 819 dm_error("DC: failed to create clock sources!\n"); 820 BREAK_TO_DEBUGGER(); 821 goto res_create_fail; 822 } 823 } 824 825 pool->base.dccg = dce_dccg_create(ctx, 826 &disp_clk_regs, 827 &disp_clk_shift, 828 &disp_clk_mask); 829 if (pool->base.dccg == NULL) { 830 dm_error("DC: failed to create display clock!\n"); 831 BREAK_TO_DEBUGGER(); 832 goto res_create_fail; 833 } 834 835 pool->base.dmcu = dce_dmcu_create(ctx, 836 &dmcu_regs, 837 &dmcu_shift, 838 &dmcu_mask); 839 if (pool->base.dmcu == NULL) { 840 dm_error("DC: failed to create dmcu!\n"); 841 BREAK_TO_DEBUGGER(); 842 goto res_create_fail; 843 } 844 845 pool->base.abm = dce_abm_create(ctx, 846 &abm_regs, 847 &abm_shift, 848 &abm_mask); 849 if (pool->base.abm == NULL) { 850 dm_error("DC: failed to create abm!\n"); 851 BREAK_TO_DEBUGGER(); 852 goto res_create_fail; 853 } 854 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 855 pool->base.dccg->max_clks_state = 856 static_clk_info.max_clocks_state; 857 858 { 859 struct irq_service_init_data init_data; 860 init_data.ctx = dc->ctx; 861 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 862 if (!pool->base.irqs) 863 goto res_create_fail; 864 } 865 866 for (i = 0; i < pool->base.pipe_count; i++) { 867 pool->base.timing_generators[i] = dce80_timing_generator_create( 868 ctx, i, &dce80_tg_offsets[i]); 869 if (pool->base.timing_generators[i] == NULL) { 870 BREAK_TO_DEBUGGER(); 871 dm_error("DC: failed to create tg!\n"); 872 goto res_create_fail; 873 } 874 875 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 876 if (pool->base.mis[i] == NULL) { 877 BREAK_TO_DEBUGGER(); 878 dm_error("DC: failed to create memory input!\n"); 879 goto res_create_fail; 880 } 881 882 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 883 if (pool->base.ipps[i] == NULL) { 884 BREAK_TO_DEBUGGER(); 885 dm_error("DC: failed to create input pixel processor!\n"); 886 goto res_create_fail; 887 } 888 889 pool->base.transforms[i] = dce80_transform_create(ctx, i); 890 if (pool->base.transforms[i] == NULL) { 891 BREAK_TO_DEBUGGER(); 892 dm_error("DC: failed to create transform!\n"); 893 goto res_create_fail; 894 } 895 896 pool->base.opps[i] = dce80_opp_create(ctx, i); 897 if (pool->base.opps[i] == NULL) { 898 BREAK_TO_DEBUGGER(); 899 dm_error("DC: failed to create output pixel processor!\n"); 900 goto res_create_fail; 901 } 902 } 903 904 dc->caps.max_planes = pool->base.pipe_count; 905 906 if (!resource_construct(num_virtual_links, dc, &pool->base, 907 &res_create_funcs)) 908 goto res_create_fail; 909 910 /* Create hardware sequencer */ 911 dce80_hw_sequencer_construct(dc); 912 913 return true; 914 915 res_create_fail: 916 destruct(pool); 917 return false; 918 } 919 920 struct resource_pool *dce80_create_resource_pool( 921 uint8_t num_virtual_links, 922 struct dc *dc) 923 { 924 struct dce110_resource_pool *pool = 925 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 926 927 if (!pool) 928 return NULL; 929 930 if (dce80_construct(num_virtual_links, dc, pool)) 931 return &pool->base; 932 933 BREAK_TO_DEBUGGER(); 934 return NULL; 935 } 936 937 static bool dce81_construct( 938 uint8_t num_virtual_links, 939 struct dc *dc, 940 struct dce110_resource_pool *pool) 941 { 942 unsigned int i; 943 struct dc_context *ctx = dc->ctx; 944 struct dc_firmware_info info; 945 struct dc_bios *bp; 946 struct dm_pp_static_clock_info static_clk_info = {0}; 947 948 ctx->dc_bios->regs = &bios_regs; 949 950 pool->base.res_cap = &res_cap_81; 951 pool->base.funcs = &dce80_res_pool_funcs; 952 953 954 /************************************************* 955 * Resource + asic cap harcoding * 956 *************************************************/ 957 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 958 pool->base.pipe_count = res_cap_81.num_timing_generator; 959 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 960 dc->caps.max_downscale_ratio = 200; 961 dc->caps.i2c_speed_in_khz = 40; 962 dc->caps.max_cursor_size = 128; 963 dc->caps.is_apu = true; 964 965 /************************************************* 966 * Create resources * 967 *************************************************/ 968 969 bp = ctx->dc_bios; 970 971 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 972 info.external_clock_source_frequency_for_dp != 0) { 973 pool->base.dp_clock_source = 974 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 975 976 pool->base.clock_sources[0] = 977 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 978 pool->base.clock_sources[1] = 979 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 980 pool->base.clock_sources[2] = 981 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 982 pool->base.clk_src_count = 3; 983 984 } else { 985 pool->base.dp_clock_source = 986 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 987 988 pool->base.clock_sources[0] = 989 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 990 pool->base.clock_sources[1] = 991 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 992 pool->base.clk_src_count = 2; 993 } 994 995 if (pool->base.dp_clock_source == NULL) { 996 dm_error("DC: failed to create dp clock source!\n"); 997 BREAK_TO_DEBUGGER(); 998 goto res_create_fail; 999 } 1000 1001 for (i = 0; i < pool->base.clk_src_count; i++) { 1002 if (pool->base.clock_sources[i] == NULL) { 1003 dm_error("DC: failed to create clock sources!\n"); 1004 BREAK_TO_DEBUGGER(); 1005 goto res_create_fail; 1006 } 1007 } 1008 1009 pool->base.dccg = dce_dccg_create(ctx, 1010 &disp_clk_regs, 1011 &disp_clk_shift, 1012 &disp_clk_mask); 1013 if (pool->base.dccg == NULL) { 1014 dm_error("DC: failed to create display clock!\n"); 1015 BREAK_TO_DEBUGGER(); 1016 goto res_create_fail; 1017 } 1018 1019 pool->base.dmcu = dce_dmcu_create(ctx, 1020 &dmcu_regs, 1021 &dmcu_shift, 1022 &dmcu_mask); 1023 if (pool->base.dmcu == NULL) { 1024 dm_error("DC: failed to create dmcu!\n"); 1025 BREAK_TO_DEBUGGER(); 1026 goto res_create_fail; 1027 } 1028 1029 pool->base.abm = dce_abm_create(ctx, 1030 &abm_regs, 1031 &abm_shift, 1032 &abm_mask); 1033 if (pool->base.abm == NULL) { 1034 dm_error("DC: failed to create abm!\n"); 1035 BREAK_TO_DEBUGGER(); 1036 goto res_create_fail; 1037 } 1038 1039 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1040 pool->base.dccg->max_clks_state = 1041 static_clk_info.max_clocks_state; 1042 1043 { 1044 struct irq_service_init_data init_data; 1045 init_data.ctx = dc->ctx; 1046 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1047 if (!pool->base.irqs) 1048 goto res_create_fail; 1049 } 1050 1051 for (i = 0; i < pool->base.pipe_count; i++) { 1052 pool->base.timing_generators[i] = dce80_timing_generator_create( 1053 ctx, i, &dce80_tg_offsets[i]); 1054 if (pool->base.timing_generators[i] == NULL) { 1055 BREAK_TO_DEBUGGER(); 1056 dm_error("DC: failed to create tg!\n"); 1057 goto res_create_fail; 1058 } 1059 1060 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1061 if (pool->base.mis[i] == NULL) { 1062 BREAK_TO_DEBUGGER(); 1063 dm_error("DC: failed to create memory input!\n"); 1064 goto res_create_fail; 1065 } 1066 1067 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1068 if (pool->base.ipps[i] == NULL) { 1069 BREAK_TO_DEBUGGER(); 1070 dm_error("DC: failed to create input pixel processor!\n"); 1071 goto res_create_fail; 1072 } 1073 1074 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1075 if (pool->base.transforms[i] == NULL) { 1076 BREAK_TO_DEBUGGER(); 1077 dm_error("DC: failed to create transform!\n"); 1078 goto res_create_fail; 1079 } 1080 1081 pool->base.opps[i] = dce80_opp_create(ctx, i); 1082 if (pool->base.opps[i] == NULL) { 1083 BREAK_TO_DEBUGGER(); 1084 dm_error("DC: failed to create output pixel processor!\n"); 1085 goto res_create_fail; 1086 } 1087 } 1088 1089 dc->caps.max_planes = pool->base.pipe_count; 1090 1091 if (!resource_construct(num_virtual_links, dc, &pool->base, 1092 &res_create_funcs)) 1093 goto res_create_fail; 1094 1095 /* Create hardware sequencer */ 1096 dce80_hw_sequencer_construct(dc); 1097 1098 return true; 1099 1100 res_create_fail: 1101 destruct(pool); 1102 return false; 1103 } 1104 1105 struct resource_pool *dce81_create_resource_pool( 1106 uint8_t num_virtual_links, 1107 struct dc *dc) 1108 { 1109 struct dce110_resource_pool *pool = 1110 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1111 1112 if (!pool) 1113 return NULL; 1114 1115 if (dce81_construct(num_virtual_links, dc, pool)) 1116 return &pool->base; 1117 1118 BREAK_TO_DEBUGGER(); 1119 return NULL; 1120 } 1121 1122 static bool dce83_construct( 1123 uint8_t num_virtual_links, 1124 struct dc *dc, 1125 struct dce110_resource_pool *pool) 1126 { 1127 unsigned int i; 1128 struct dc_context *ctx = dc->ctx; 1129 struct dc_firmware_info info; 1130 struct dc_bios *bp; 1131 struct dm_pp_static_clock_info static_clk_info = {0}; 1132 1133 ctx->dc_bios->regs = &bios_regs; 1134 1135 pool->base.res_cap = &res_cap_83; 1136 pool->base.funcs = &dce80_res_pool_funcs; 1137 1138 1139 /************************************************* 1140 * Resource + asic cap harcoding * 1141 *************************************************/ 1142 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1143 pool->base.pipe_count = res_cap_83.num_timing_generator; 1144 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1145 dc->caps.max_downscale_ratio = 200; 1146 dc->caps.i2c_speed_in_khz = 40; 1147 dc->caps.max_cursor_size = 128; 1148 dc->caps.is_apu = true; 1149 1150 /************************************************* 1151 * Create resources * 1152 *************************************************/ 1153 1154 bp = ctx->dc_bios; 1155 1156 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1157 info.external_clock_source_frequency_for_dp != 0) { 1158 pool->base.dp_clock_source = 1159 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1160 1161 pool->base.clock_sources[0] = 1162 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1163 pool->base.clock_sources[1] = 1164 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1165 pool->base.clk_src_count = 2; 1166 1167 } else { 1168 pool->base.dp_clock_source = 1169 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1170 1171 pool->base.clock_sources[0] = 1172 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1173 pool->base.clk_src_count = 1; 1174 } 1175 1176 if (pool->base.dp_clock_source == NULL) { 1177 dm_error("DC: failed to create dp clock source!\n"); 1178 BREAK_TO_DEBUGGER(); 1179 goto res_create_fail; 1180 } 1181 1182 for (i = 0; i < pool->base.clk_src_count; i++) { 1183 if (pool->base.clock_sources[i] == NULL) { 1184 dm_error("DC: failed to create clock sources!\n"); 1185 BREAK_TO_DEBUGGER(); 1186 goto res_create_fail; 1187 } 1188 } 1189 1190 pool->base.dccg = dce_dccg_create(ctx, 1191 &disp_clk_regs, 1192 &disp_clk_shift, 1193 &disp_clk_mask); 1194 if (pool->base.dccg == NULL) { 1195 dm_error("DC: failed to create display clock!\n"); 1196 BREAK_TO_DEBUGGER(); 1197 goto res_create_fail; 1198 } 1199 1200 pool->base.dmcu = dce_dmcu_create(ctx, 1201 &dmcu_regs, 1202 &dmcu_shift, 1203 &dmcu_mask); 1204 if (pool->base.dmcu == NULL) { 1205 dm_error("DC: failed to create dmcu!\n"); 1206 BREAK_TO_DEBUGGER(); 1207 goto res_create_fail; 1208 } 1209 1210 pool->base.abm = dce_abm_create(ctx, 1211 &abm_regs, 1212 &abm_shift, 1213 &abm_mask); 1214 if (pool->base.abm == NULL) { 1215 dm_error("DC: failed to create abm!\n"); 1216 BREAK_TO_DEBUGGER(); 1217 goto res_create_fail; 1218 } 1219 1220 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1221 pool->base.dccg->max_clks_state = 1222 static_clk_info.max_clocks_state; 1223 1224 { 1225 struct irq_service_init_data init_data; 1226 init_data.ctx = dc->ctx; 1227 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1228 if (!pool->base.irqs) 1229 goto res_create_fail; 1230 } 1231 1232 for (i = 0; i < pool->base.pipe_count; i++) { 1233 pool->base.timing_generators[i] = dce80_timing_generator_create( 1234 ctx, i, &dce80_tg_offsets[i]); 1235 if (pool->base.timing_generators[i] == NULL) { 1236 BREAK_TO_DEBUGGER(); 1237 dm_error("DC: failed to create tg!\n"); 1238 goto res_create_fail; 1239 } 1240 1241 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1242 if (pool->base.mis[i] == NULL) { 1243 BREAK_TO_DEBUGGER(); 1244 dm_error("DC: failed to create memory input!\n"); 1245 goto res_create_fail; 1246 } 1247 1248 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1249 if (pool->base.ipps[i] == NULL) { 1250 BREAK_TO_DEBUGGER(); 1251 dm_error("DC: failed to create input pixel processor!\n"); 1252 goto res_create_fail; 1253 } 1254 1255 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1256 if (pool->base.transforms[i] == NULL) { 1257 BREAK_TO_DEBUGGER(); 1258 dm_error("DC: failed to create transform!\n"); 1259 goto res_create_fail; 1260 } 1261 1262 pool->base.opps[i] = dce80_opp_create(ctx, i); 1263 if (pool->base.opps[i] == NULL) { 1264 BREAK_TO_DEBUGGER(); 1265 dm_error("DC: failed to create output pixel processor!\n"); 1266 goto res_create_fail; 1267 } 1268 } 1269 1270 dc->caps.max_planes = pool->base.pipe_count; 1271 1272 if (!resource_construct(num_virtual_links, dc, &pool->base, 1273 &res_create_funcs)) 1274 goto res_create_fail; 1275 1276 /* Create hardware sequencer */ 1277 dce80_hw_sequencer_construct(dc); 1278 1279 return true; 1280 1281 res_create_fail: 1282 destruct(pool); 1283 return false; 1284 } 1285 1286 struct resource_pool *dce83_create_resource_pool( 1287 uint8_t num_virtual_links, 1288 struct dc *dc) 1289 { 1290 struct dce110_resource_pool *pool = 1291 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1292 1293 if (!pool) 1294 return NULL; 1295 1296 if (dce83_construct(num_virtual_links, dc, pool)) 1297 return &pool->base; 1298 1299 BREAK_TO_DEBUGGER(); 1300 return NULL; 1301 } 1302