1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_8_0_d.h" 29 #include "dce/dce_8_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "include/irq_service_interface.h" 38 #include "irq/dce80/irq_service_dce80.h" 39 #include "dce110/dce110_timing_generator.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce80/dce80_timing_generator.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce/dce_link_encoder.h" 44 #include "dce/dce_stream_encoder.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_transform.h" 47 #include "dce/dce_opp.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 #include "dce/dce_i2c.h" 60 /* TODO remove this include */ 61 62 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 63 #include "gmc/gmc_7_1_d.h" 64 #include "gmc/gmc_7_1_sh_mask.h" 65 #endif 66 67 #ifndef mmDP_DPHY_INTERNAL_CTRL 68 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 94 #endif 95 96 97 #ifndef mmHPD_DC_HPD_CONTROL 98 #define mmHPD_DC_HPD_CONTROL 0x189A 99 #define mmHPD0_DC_HPD_CONTROL 0x189A 100 #define mmHPD1_DC_HPD_CONTROL 0x18A2 101 #define mmHPD2_DC_HPD_CONTROL 0x18AA 102 #define mmHPD3_DC_HPD_CONTROL 0x18B2 103 #define mmHPD4_DC_HPD_CONTROL 0x18BA 104 #define mmHPD5_DC_HPD_CONTROL 0x18C2 105 #endif 106 107 #define DCE11_DIG_FE_CNTL 0x4a00 108 #define DCE11_DIG_BE_CNTL 0x4a47 109 #define DCE11_DP_SEC 0x4ac3 110 111 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 115 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 116 - mmDPG_WATERMARK_MASK_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 122 - mmDPG_WATERMARK_MASK_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 128 - mmDPG_WATERMARK_MASK_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 134 - mmDPG_WATERMARK_MASK_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 139 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 140 - mmDPG_WATERMARK_MASK_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 146 - mmDPG_WATERMARK_MASK_CONTROL), 147 } 148 }; 149 150 /* set register offset */ 151 #define SR(reg_name)\ 152 .reg_name = mm ## reg_name 153 154 /* set register offset with instance */ 155 #define SRI(reg_name, block, id)\ 156 .reg_name = mm ## block ## id ## _ ## reg_name 157 158 #define ipp_regs(id)\ 159 [id] = {\ 160 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 161 } 162 163 static const struct dce_ipp_registers ipp_regs[] = { 164 ipp_regs(0), 165 ipp_regs(1), 166 ipp_regs(2), 167 ipp_regs(3), 168 ipp_regs(4), 169 ipp_regs(5) 170 }; 171 172 static const struct dce_ipp_shift ipp_shift = { 173 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 174 }; 175 176 static const struct dce_ipp_mask ipp_mask = { 177 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 178 }; 179 180 #define transform_regs(id)\ 181 [id] = {\ 182 XFM_COMMON_REG_LIST_DCE80(id)\ 183 } 184 185 static const struct dce_transform_registers xfm_regs[] = { 186 transform_regs(0), 187 transform_regs(1), 188 transform_regs(2), 189 transform_regs(3), 190 transform_regs(4), 191 transform_regs(5) 192 }; 193 194 static const struct dce_transform_shift xfm_shift = { 195 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 196 }; 197 198 static const struct dce_transform_mask xfm_mask = { 199 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 200 }; 201 202 #define aux_regs(id)\ 203 [id] = {\ 204 AUX_REG_LIST(id)\ 205 } 206 207 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 208 aux_regs(0), 209 aux_regs(1), 210 aux_regs(2), 211 aux_regs(3), 212 aux_regs(4), 213 aux_regs(5) 214 }; 215 216 #define hpd_regs(id)\ 217 [id] = {\ 218 HPD_REG_LIST(id)\ 219 } 220 221 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 222 hpd_regs(0), 223 hpd_regs(1), 224 hpd_regs(2), 225 hpd_regs(3), 226 hpd_regs(4), 227 hpd_regs(5) 228 }; 229 230 #define link_regs(id)\ 231 [id] = {\ 232 LE_DCE80_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_registers link_enc_regs[] = { 236 link_regs(0), 237 link_regs(1), 238 link_regs(2), 239 link_regs(3), 240 link_regs(4), 241 link_regs(5), 242 link_regs(6), 243 }; 244 245 #define stream_enc_regs(id)\ 246 [id] = {\ 247 SE_COMMON_REG_LIST_DCE_BASE(id),\ 248 .AFMT_CNTL = 0,\ 249 } 250 251 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 252 stream_enc_regs(0), 253 stream_enc_regs(1), 254 stream_enc_regs(2), 255 stream_enc_regs(3), 256 stream_enc_regs(4), 257 stream_enc_regs(5), 258 stream_enc_regs(6) 259 }; 260 261 static const struct dce_stream_encoder_shift se_shift = { 262 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 263 }; 264 265 static const struct dce_stream_encoder_mask se_mask = { 266 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 267 }; 268 269 #define opp_regs(id)\ 270 [id] = {\ 271 OPP_DCE_80_REG_LIST(id),\ 272 } 273 274 static const struct dce_opp_registers opp_regs[] = { 275 opp_regs(0), 276 opp_regs(1), 277 opp_regs(2), 278 opp_regs(3), 279 opp_regs(4), 280 opp_regs(5) 281 }; 282 283 static const struct dce_opp_shift opp_shift = { 284 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 285 }; 286 287 static const struct dce_opp_mask opp_mask = { 288 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 289 }; 290 291 #define aux_engine_regs(id)\ 292 [id] = {\ 293 AUX_COMMON_REG_LIST(id), \ 294 .AUX_RESET_MASK = 0 \ 295 } 296 297 static const struct dce110_aux_registers aux_engine_regs[] = { 298 aux_engine_regs(0), 299 aux_engine_regs(1), 300 aux_engine_regs(2), 301 aux_engine_regs(3), 302 aux_engine_regs(4), 303 aux_engine_regs(5) 304 }; 305 306 #define audio_regs(id)\ 307 [id] = {\ 308 AUD_COMMON_REG_LIST(id)\ 309 } 310 311 static const struct dce_audio_registers audio_regs[] = { 312 audio_regs(0), 313 audio_regs(1), 314 audio_regs(2), 315 audio_regs(3), 316 audio_regs(4), 317 audio_regs(5), 318 audio_regs(6), 319 }; 320 321 static const struct dce_audio_shift audio_shift = { 322 AUD_COMMON_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dce_audio_mask audio_mask = { 326 AUD_COMMON_MASK_SH_LIST(_MASK) 327 }; 328 329 #define clk_src_regs(id)\ 330 [id] = {\ 331 CS_COMMON_REG_LIST_DCE_80(id),\ 332 } 333 334 335 static const struct dce110_clk_src_regs clk_src_regs[] = { 336 clk_src_regs(0), 337 clk_src_regs(1), 338 clk_src_regs(2) 339 }; 340 341 static const struct dce110_clk_src_shift cs_shift = { 342 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 343 }; 344 345 static const struct dce110_clk_src_mask cs_mask = { 346 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 347 }; 348 349 static const struct bios_registers bios_regs = { 350 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 351 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 352 }; 353 354 static const struct resource_caps res_cap = { 355 .num_timing_generator = 6, 356 .num_audio = 6, 357 .num_stream_encoder = 6, 358 .num_pll = 3, 359 .num_ddc = 6, 360 }; 361 362 static const struct resource_caps res_cap_81 = { 363 .num_timing_generator = 4, 364 .num_audio = 7, 365 .num_stream_encoder = 7, 366 .num_pll = 3, 367 .num_ddc = 6, 368 }; 369 370 static const struct resource_caps res_cap_83 = { 371 .num_timing_generator = 2, 372 .num_audio = 6, 373 .num_stream_encoder = 6, 374 .num_pll = 2, 375 .num_ddc = 2, 376 }; 377 378 static const struct dc_plane_cap plane_cap = { 379 .type = DC_PLANE_TYPE_DCE_RGB, 380 381 .pixel_format_support = { 382 .argb8888 = true, 383 .nv12 = false, 384 .fp16 = false 385 }, 386 387 .max_upscale_factor = { 388 .argb8888 = 16000, 389 .nv12 = 1, 390 .fp16 = 1 391 }, 392 393 .max_downscale_factor = { 394 .argb8888 = 250, 395 .nv12 = 1, 396 .fp16 = 1 397 } 398 }; 399 400 static const struct dce_dmcu_registers dmcu_regs = { 401 DMCU_DCE80_REG_LIST() 402 }; 403 404 static const struct dce_dmcu_shift dmcu_shift = { 405 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 406 }; 407 408 static const struct dce_dmcu_mask dmcu_mask = { 409 DMCU_MASK_SH_LIST_DCE80(_MASK) 410 }; 411 static const struct dce_abm_registers abm_regs = { 412 ABM_DCE110_COMMON_REG_LIST() 413 }; 414 415 static const struct dce_abm_shift abm_shift = { 416 ABM_MASK_SH_LIST_DCE110(__SHIFT) 417 }; 418 419 static const struct dce_abm_mask abm_mask = { 420 ABM_MASK_SH_LIST_DCE110(_MASK) 421 }; 422 423 #define CTX ctx 424 #define REG(reg) mm ## reg 425 426 #ifndef mmCC_DC_HDMI_STRAPS 427 #define mmCC_DC_HDMI_STRAPS 0x1918 428 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 429 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 430 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 431 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 432 #endif 433 434 static void read_dce_straps( 435 struct dc_context *ctx, 436 struct resource_straps *straps) 437 { 438 REG_GET_2(CC_DC_HDMI_STRAPS, 439 HDMI_DISABLE, &straps->hdmi_disable, 440 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 441 442 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 443 } 444 445 static struct audio *create_audio( 446 struct dc_context *ctx, unsigned int inst) 447 { 448 return dce_audio_create(ctx, inst, 449 &audio_regs[inst], &audio_shift, &audio_mask); 450 } 451 452 static struct timing_generator *dce80_timing_generator_create( 453 struct dc_context *ctx, 454 uint32_t instance, 455 const struct dce110_timing_generator_offsets *offsets) 456 { 457 struct dce110_timing_generator *tg110 = 458 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 459 460 if (!tg110) 461 return NULL; 462 463 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 464 return &tg110->base; 465 } 466 467 static struct output_pixel_processor *dce80_opp_create( 468 struct dc_context *ctx, 469 uint32_t inst) 470 { 471 struct dce110_opp *opp = 472 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 473 474 if (!opp) 475 return NULL; 476 477 dce110_opp_construct(opp, 478 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 479 return &opp->base; 480 } 481 482 struct dce_aux *dce80_aux_engine_create( 483 struct dc_context *ctx, 484 uint32_t inst) 485 { 486 struct aux_engine_dce110 *aux_engine = 487 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 488 489 if (!aux_engine) 490 return NULL; 491 492 dce110_aux_engine_construct(aux_engine, ctx, inst, 493 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 494 &aux_engine_regs[inst]); 495 496 return &aux_engine->base; 497 } 498 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 499 500 static const struct dce_i2c_registers i2c_hw_regs[] = { 501 i2c_inst_regs(1), 502 i2c_inst_regs(2), 503 i2c_inst_regs(3), 504 i2c_inst_regs(4), 505 i2c_inst_regs(5), 506 i2c_inst_regs(6), 507 }; 508 509 static const struct dce_i2c_shift i2c_shifts = { 510 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 511 }; 512 513 static const struct dce_i2c_mask i2c_masks = { 514 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 515 }; 516 517 struct dce_i2c_hw *dce80_i2c_hw_create( 518 struct dc_context *ctx, 519 uint32_t inst) 520 { 521 struct dce_i2c_hw *dce_i2c_hw = 522 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 523 524 if (!dce_i2c_hw) 525 return NULL; 526 527 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 528 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 529 530 return dce_i2c_hw; 531 } 532 533 struct dce_i2c_sw *dce80_i2c_sw_create( 534 struct dc_context *ctx) 535 { 536 struct dce_i2c_sw *dce_i2c_sw = 537 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 538 539 if (!dce_i2c_sw) 540 return NULL; 541 542 dce_i2c_sw_construct(dce_i2c_sw, ctx); 543 544 return dce_i2c_sw; 545 } 546 static struct stream_encoder *dce80_stream_encoder_create( 547 enum engine_id eng_id, 548 struct dc_context *ctx) 549 { 550 struct dce110_stream_encoder *enc110 = 551 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 552 553 if (!enc110) 554 return NULL; 555 556 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 557 &stream_enc_regs[eng_id], 558 &se_shift, &se_mask); 559 return &enc110->base; 560 } 561 562 #define SRII(reg_name, block, id)\ 563 .reg_name[id] = mm ## block ## id ## _ ## reg_name 564 565 static const struct dce_hwseq_registers hwseq_reg = { 566 HWSEQ_DCE8_REG_LIST() 567 }; 568 569 static const struct dce_hwseq_shift hwseq_shift = { 570 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 571 }; 572 573 static const struct dce_hwseq_mask hwseq_mask = { 574 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 575 }; 576 577 static struct dce_hwseq *dce80_hwseq_create( 578 struct dc_context *ctx) 579 { 580 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 581 582 if (hws) { 583 hws->ctx = ctx; 584 hws->regs = &hwseq_reg; 585 hws->shifts = &hwseq_shift; 586 hws->masks = &hwseq_mask; 587 } 588 return hws; 589 } 590 591 static const struct resource_create_funcs res_create_funcs = { 592 .read_dce_straps = read_dce_straps, 593 .create_audio = create_audio, 594 .create_stream_encoder = dce80_stream_encoder_create, 595 .create_hwseq = dce80_hwseq_create, 596 }; 597 598 #define mi_inst_regs(id) { \ 599 MI_DCE8_REG_LIST(id), \ 600 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 601 } 602 static const struct dce_mem_input_registers mi_regs[] = { 603 mi_inst_regs(0), 604 mi_inst_regs(1), 605 mi_inst_regs(2), 606 mi_inst_regs(3), 607 mi_inst_regs(4), 608 mi_inst_regs(5), 609 }; 610 611 static const struct dce_mem_input_shift mi_shifts = { 612 MI_DCE8_MASK_SH_LIST(__SHIFT), 613 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 614 }; 615 616 static const struct dce_mem_input_mask mi_masks = { 617 MI_DCE8_MASK_SH_LIST(_MASK), 618 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 619 }; 620 621 static struct mem_input *dce80_mem_input_create( 622 struct dc_context *ctx, 623 uint32_t inst) 624 { 625 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 626 GFP_KERNEL); 627 628 if (!dce_mi) { 629 BREAK_TO_DEBUGGER(); 630 return NULL; 631 } 632 633 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 634 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 635 return &dce_mi->base; 636 } 637 638 static void dce80_transform_destroy(struct transform **xfm) 639 { 640 kfree(TO_DCE_TRANSFORM(*xfm)); 641 *xfm = NULL; 642 } 643 644 static struct transform *dce80_transform_create( 645 struct dc_context *ctx, 646 uint32_t inst) 647 { 648 struct dce_transform *transform = 649 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 650 651 if (!transform) 652 return NULL; 653 654 dce_transform_construct(transform, ctx, inst, 655 &xfm_regs[inst], &xfm_shift, &xfm_mask); 656 transform->prescaler_on = false; 657 return &transform->base; 658 } 659 660 static const struct encoder_feature_support link_enc_feature = { 661 .max_hdmi_deep_color = COLOR_DEPTH_121212, 662 .max_hdmi_pixel_clock = 297000, 663 .flags.bits.IS_HBR2_CAPABLE = true, 664 .flags.bits.IS_TPS3_CAPABLE = true 665 }; 666 667 struct link_encoder *dce80_link_encoder_create( 668 const struct encoder_init_data *enc_init_data) 669 { 670 struct dce110_link_encoder *enc110 = 671 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 672 673 if (!enc110) 674 return NULL; 675 676 dce110_link_encoder_construct(enc110, 677 enc_init_data, 678 &link_enc_feature, 679 &link_enc_regs[enc_init_data->transmitter], 680 &link_enc_aux_regs[enc_init_data->channel - 1], 681 &link_enc_hpd_regs[enc_init_data->hpd_source]); 682 return &enc110->base; 683 } 684 685 struct clock_source *dce80_clock_source_create( 686 struct dc_context *ctx, 687 struct dc_bios *bios, 688 enum clock_source_id id, 689 const struct dce110_clk_src_regs *regs, 690 bool dp_clk_src) 691 { 692 struct dce110_clk_src *clk_src = 693 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 694 695 if (!clk_src) 696 return NULL; 697 698 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 699 regs, &cs_shift, &cs_mask)) { 700 clk_src->base.dp_clk_src = dp_clk_src; 701 return &clk_src->base; 702 } 703 704 BREAK_TO_DEBUGGER(); 705 return NULL; 706 } 707 708 void dce80_clock_source_destroy(struct clock_source **clk_src) 709 { 710 kfree(TO_DCE110_CLK_SRC(*clk_src)); 711 *clk_src = NULL; 712 } 713 714 static struct input_pixel_processor *dce80_ipp_create( 715 struct dc_context *ctx, uint32_t inst) 716 { 717 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 718 719 if (!ipp) { 720 BREAK_TO_DEBUGGER(); 721 return NULL; 722 } 723 724 dce_ipp_construct(ipp, ctx, inst, 725 &ipp_regs[inst], &ipp_shift, &ipp_mask); 726 return &ipp->base; 727 } 728 729 static void destruct(struct dce110_resource_pool *pool) 730 { 731 unsigned int i; 732 733 for (i = 0; i < pool->base.pipe_count; i++) { 734 if (pool->base.opps[i] != NULL) 735 dce110_opp_destroy(&pool->base.opps[i]); 736 737 if (pool->base.transforms[i] != NULL) 738 dce80_transform_destroy(&pool->base.transforms[i]); 739 740 if (pool->base.ipps[i] != NULL) 741 dce_ipp_destroy(&pool->base.ipps[i]); 742 743 if (pool->base.mis[i] != NULL) { 744 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 745 pool->base.mis[i] = NULL; 746 } 747 748 if (pool->base.timing_generators[i] != NULL) { 749 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 750 pool->base.timing_generators[i] = NULL; 751 } 752 } 753 754 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 755 if (pool->base.engines[i] != NULL) 756 dce110_engine_destroy(&pool->base.engines[i]); 757 if (pool->base.hw_i2cs[i] != NULL) { 758 kfree(pool->base.hw_i2cs[i]); 759 pool->base.hw_i2cs[i] = NULL; 760 } 761 if (pool->base.sw_i2cs[i] != NULL) { 762 kfree(pool->base.sw_i2cs[i]); 763 pool->base.sw_i2cs[i] = NULL; 764 } 765 } 766 767 for (i = 0; i < pool->base.stream_enc_count; i++) { 768 if (pool->base.stream_enc[i] != NULL) 769 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 770 } 771 772 for (i = 0; i < pool->base.clk_src_count; i++) { 773 if (pool->base.clock_sources[i] != NULL) { 774 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 775 } 776 } 777 778 if (pool->base.abm != NULL) 779 dce_abm_destroy(&pool->base.abm); 780 781 if (pool->base.dmcu != NULL) 782 dce_dmcu_destroy(&pool->base.dmcu); 783 784 if (pool->base.dp_clock_source != NULL) 785 dce80_clock_source_destroy(&pool->base.dp_clock_source); 786 787 for (i = 0; i < pool->base.audio_count; i++) { 788 if (pool->base.audios[i] != NULL) { 789 dce_aud_destroy(&pool->base.audios[i]); 790 } 791 } 792 793 if (pool->base.irqs != NULL) { 794 dal_irq_service_destroy(&pool->base.irqs); 795 } 796 } 797 798 bool dce80_validate_bandwidth( 799 struct dc *dc, 800 struct dc_state *context, 801 bool fast_validate) 802 { 803 int i; 804 bool at_least_one_pipe = false; 805 806 for (i = 0; i < dc->res_pool->pipe_count; i++) { 807 if (context->res_ctx.pipe_ctx[i].stream) 808 at_least_one_pipe = true; 809 } 810 811 if (at_least_one_pipe) { 812 /* TODO implement when needed but for now hardcode max value*/ 813 context->bw_ctx.bw.dce.dispclk_khz = 681000; 814 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 815 } else { 816 context->bw_ctx.bw.dce.dispclk_khz = 0; 817 context->bw_ctx.bw.dce.yclk_khz = 0; 818 } 819 820 return true; 821 } 822 823 static bool dce80_validate_surface_sets( 824 struct dc_state *context) 825 { 826 int i; 827 828 for (i = 0; i < context->stream_count; i++) { 829 if (context->stream_status[i].plane_count == 0) 830 continue; 831 832 if (context->stream_status[i].plane_count > 1) 833 return false; 834 835 if (context->stream_status[i].plane_states[0]->format 836 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 837 return false; 838 } 839 840 return true; 841 } 842 843 enum dc_status dce80_validate_global( 844 struct dc *dc, 845 struct dc_state *context) 846 { 847 if (!dce80_validate_surface_sets(context)) 848 return DC_FAIL_SURFACE_VALIDATE; 849 850 return DC_OK; 851 } 852 853 static void dce80_destroy_resource_pool(struct resource_pool **pool) 854 { 855 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 856 857 destruct(dce110_pool); 858 kfree(dce110_pool); 859 *pool = NULL; 860 } 861 862 static const struct resource_funcs dce80_res_pool_funcs = { 863 .destroy = dce80_destroy_resource_pool, 864 .link_enc_create = dce80_link_encoder_create, 865 .validate_bandwidth = dce80_validate_bandwidth, 866 .validate_plane = dce100_validate_plane, 867 .add_stream_to_ctx = dce100_add_stream_to_ctx, 868 .validate_global = dce80_validate_global, 869 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 870 }; 871 872 static bool dce80_construct( 873 uint8_t num_virtual_links, 874 struct dc *dc, 875 struct dce110_resource_pool *pool) 876 { 877 unsigned int i; 878 struct dc_context *ctx = dc->ctx; 879 struct dc_bios *bp; 880 881 ctx->dc_bios->regs = &bios_regs; 882 883 pool->base.res_cap = &res_cap; 884 pool->base.funcs = &dce80_res_pool_funcs; 885 886 887 /************************************************* 888 * Resource + asic cap harcoding * 889 *************************************************/ 890 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 891 pool->base.pipe_count = res_cap.num_timing_generator; 892 pool->base.timing_generator_count = res_cap.num_timing_generator; 893 dc->caps.max_downscale_ratio = 200; 894 dc->caps.i2c_speed_in_khz = 40; 895 dc->caps.max_cursor_size = 128; 896 dc->caps.dual_link_dvi = true; 897 898 /************************************************* 899 * Create resources * 900 *************************************************/ 901 902 bp = ctx->dc_bios; 903 904 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 905 pool->base.dp_clock_source = 906 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 907 908 pool->base.clock_sources[0] = 909 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 910 pool->base.clock_sources[1] = 911 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 912 pool->base.clock_sources[2] = 913 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 914 pool->base.clk_src_count = 3; 915 916 } else { 917 pool->base.dp_clock_source = 918 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 919 920 pool->base.clock_sources[0] = 921 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 922 pool->base.clock_sources[1] = 923 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 924 pool->base.clk_src_count = 2; 925 } 926 927 if (pool->base.dp_clock_source == NULL) { 928 dm_error("DC: failed to create dp clock source!\n"); 929 BREAK_TO_DEBUGGER(); 930 goto res_create_fail; 931 } 932 933 for (i = 0; i < pool->base.clk_src_count; i++) { 934 if (pool->base.clock_sources[i] == NULL) { 935 dm_error("DC: failed to create clock sources!\n"); 936 BREAK_TO_DEBUGGER(); 937 goto res_create_fail; 938 } 939 } 940 941 pool->base.dmcu = dce_dmcu_create(ctx, 942 &dmcu_regs, 943 &dmcu_shift, 944 &dmcu_mask); 945 if (pool->base.dmcu == NULL) { 946 dm_error("DC: failed to create dmcu!\n"); 947 BREAK_TO_DEBUGGER(); 948 goto res_create_fail; 949 } 950 951 pool->base.abm = dce_abm_create(ctx, 952 &abm_regs, 953 &abm_shift, 954 &abm_mask); 955 if (pool->base.abm == NULL) { 956 dm_error("DC: failed to create abm!\n"); 957 BREAK_TO_DEBUGGER(); 958 goto res_create_fail; 959 } 960 961 { 962 struct irq_service_init_data init_data; 963 init_data.ctx = dc->ctx; 964 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 965 if (!pool->base.irqs) 966 goto res_create_fail; 967 } 968 969 for (i = 0; i < pool->base.pipe_count; i++) { 970 pool->base.timing_generators[i] = dce80_timing_generator_create( 971 ctx, i, &dce80_tg_offsets[i]); 972 if (pool->base.timing_generators[i] == NULL) { 973 BREAK_TO_DEBUGGER(); 974 dm_error("DC: failed to create tg!\n"); 975 goto res_create_fail; 976 } 977 978 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 979 if (pool->base.mis[i] == NULL) { 980 BREAK_TO_DEBUGGER(); 981 dm_error("DC: failed to create memory input!\n"); 982 goto res_create_fail; 983 } 984 985 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 986 if (pool->base.ipps[i] == NULL) { 987 BREAK_TO_DEBUGGER(); 988 dm_error("DC: failed to create input pixel processor!\n"); 989 goto res_create_fail; 990 } 991 992 pool->base.transforms[i] = dce80_transform_create(ctx, i); 993 if (pool->base.transforms[i] == NULL) { 994 BREAK_TO_DEBUGGER(); 995 dm_error("DC: failed to create transform!\n"); 996 goto res_create_fail; 997 } 998 999 pool->base.opps[i] = dce80_opp_create(ctx, i); 1000 if (pool->base.opps[i] == NULL) { 1001 BREAK_TO_DEBUGGER(); 1002 dm_error("DC: failed to create output pixel processor!\n"); 1003 goto res_create_fail; 1004 } 1005 } 1006 1007 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1008 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1009 if (pool->base.engines[i] == NULL) { 1010 BREAK_TO_DEBUGGER(); 1011 dm_error( 1012 "DC:failed to create aux engine!!\n"); 1013 goto res_create_fail; 1014 } 1015 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1016 if (pool->base.hw_i2cs[i] == NULL) { 1017 BREAK_TO_DEBUGGER(); 1018 dm_error( 1019 "DC:failed to create i2c engine!!\n"); 1020 goto res_create_fail; 1021 } 1022 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1023 if (pool->base.sw_i2cs[i] == NULL) { 1024 BREAK_TO_DEBUGGER(); 1025 dm_error( 1026 "DC:failed to create sw i2c!!\n"); 1027 goto res_create_fail; 1028 } 1029 } 1030 1031 dc->caps.max_planes = pool->base.pipe_count; 1032 1033 for (i = 0; i < dc->caps.max_planes; ++i) 1034 dc->caps.planes[i] = plane_cap; 1035 1036 dc->caps.disable_dp_clk_share = true; 1037 1038 if (!resource_construct(num_virtual_links, dc, &pool->base, 1039 &res_create_funcs)) 1040 goto res_create_fail; 1041 1042 /* Create hardware sequencer */ 1043 dce80_hw_sequencer_construct(dc); 1044 1045 return true; 1046 1047 res_create_fail: 1048 destruct(pool); 1049 return false; 1050 } 1051 1052 struct resource_pool *dce80_create_resource_pool( 1053 uint8_t num_virtual_links, 1054 struct dc *dc) 1055 { 1056 struct dce110_resource_pool *pool = 1057 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1058 1059 if (!pool) 1060 return NULL; 1061 1062 if (dce80_construct(num_virtual_links, dc, pool)) 1063 return &pool->base; 1064 1065 BREAK_TO_DEBUGGER(); 1066 return NULL; 1067 } 1068 1069 static bool dce81_construct( 1070 uint8_t num_virtual_links, 1071 struct dc *dc, 1072 struct dce110_resource_pool *pool) 1073 { 1074 unsigned int i; 1075 struct dc_context *ctx = dc->ctx; 1076 struct dc_bios *bp; 1077 1078 ctx->dc_bios->regs = &bios_regs; 1079 1080 pool->base.res_cap = &res_cap_81; 1081 pool->base.funcs = &dce80_res_pool_funcs; 1082 1083 1084 /************************************************* 1085 * Resource + asic cap harcoding * 1086 *************************************************/ 1087 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1088 pool->base.pipe_count = res_cap_81.num_timing_generator; 1089 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1090 dc->caps.max_downscale_ratio = 200; 1091 dc->caps.i2c_speed_in_khz = 40; 1092 dc->caps.max_cursor_size = 128; 1093 dc->caps.is_apu = true; 1094 1095 /************************************************* 1096 * Create resources * 1097 *************************************************/ 1098 1099 bp = ctx->dc_bios; 1100 1101 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1102 pool->base.dp_clock_source = 1103 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1104 1105 pool->base.clock_sources[0] = 1106 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1107 pool->base.clock_sources[1] = 1108 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1109 pool->base.clock_sources[2] = 1110 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1111 pool->base.clk_src_count = 3; 1112 1113 } else { 1114 pool->base.dp_clock_source = 1115 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1116 1117 pool->base.clock_sources[0] = 1118 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1119 pool->base.clock_sources[1] = 1120 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1121 pool->base.clk_src_count = 2; 1122 } 1123 1124 if (pool->base.dp_clock_source == NULL) { 1125 dm_error("DC: failed to create dp clock source!\n"); 1126 BREAK_TO_DEBUGGER(); 1127 goto res_create_fail; 1128 } 1129 1130 for (i = 0; i < pool->base.clk_src_count; i++) { 1131 if (pool->base.clock_sources[i] == NULL) { 1132 dm_error("DC: failed to create clock sources!\n"); 1133 BREAK_TO_DEBUGGER(); 1134 goto res_create_fail; 1135 } 1136 } 1137 1138 pool->base.dmcu = dce_dmcu_create(ctx, 1139 &dmcu_regs, 1140 &dmcu_shift, 1141 &dmcu_mask); 1142 if (pool->base.dmcu == NULL) { 1143 dm_error("DC: failed to create dmcu!\n"); 1144 BREAK_TO_DEBUGGER(); 1145 goto res_create_fail; 1146 } 1147 1148 pool->base.abm = dce_abm_create(ctx, 1149 &abm_regs, 1150 &abm_shift, 1151 &abm_mask); 1152 if (pool->base.abm == NULL) { 1153 dm_error("DC: failed to create abm!\n"); 1154 BREAK_TO_DEBUGGER(); 1155 goto res_create_fail; 1156 } 1157 1158 { 1159 struct irq_service_init_data init_data; 1160 init_data.ctx = dc->ctx; 1161 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1162 if (!pool->base.irqs) 1163 goto res_create_fail; 1164 } 1165 1166 for (i = 0; i < pool->base.pipe_count; i++) { 1167 pool->base.timing_generators[i] = dce80_timing_generator_create( 1168 ctx, i, &dce80_tg_offsets[i]); 1169 if (pool->base.timing_generators[i] == NULL) { 1170 BREAK_TO_DEBUGGER(); 1171 dm_error("DC: failed to create tg!\n"); 1172 goto res_create_fail; 1173 } 1174 1175 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1176 if (pool->base.mis[i] == NULL) { 1177 BREAK_TO_DEBUGGER(); 1178 dm_error("DC: failed to create memory input!\n"); 1179 goto res_create_fail; 1180 } 1181 1182 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1183 if (pool->base.ipps[i] == NULL) { 1184 BREAK_TO_DEBUGGER(); 1185 dm_error("DC: failed to create input pixel processor!\n"); 1186 goto res_create_fail; 1187 } 1188 1189 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1190 if (pool->base.transforms[i] == NULL) { 1191 BREAK_TO_DEBUGGER(); 1192 dm_error("DC: failed to create transform!\n"); 1193 goto res_create_fail; 1194 } 1195 1196 pool->base.opps[i] = dce80_opp_create(ctx, i); 1197 if (pool->base.opps[i] == NULL) { 1198 BREAK_TO_DEBUGGER(); 1199 dm_error("DC: failed to create output pixel processor!\n"); 1200 goto res_create_fail; 1201 } 1202 } 1203 1204 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1205 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1206 if (pool->base.engines[i] == NULL) { 1207 BREAK_TO_DEBUGGER(); 1208 dm_error( 1209 "DC:failed to create aux engine!!\n"); 1210 goto res_create_fail; 1211 } 1212 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1213 if (pool->base.hw_i2cs[i] == NULL) { 1214 BREAK_TO_DEBUGGER(); 1215 dm_error( 1216 "DC:failed to create i2c engine!!\n"); 1217 goto res_create_fail; 1218 } 1219 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1220 if (pool->base.sw_i2cs[i] == NULL) { 1221 BREAK_TO_DEBUGGER(); 1222 dm_error( 1223 "DC:failed to create sw i2c!!\n"); 1224 goto res_create_fail; 1225 } 1226 } 1227 1228 dc->caps.max_planes = pool->base.pipe_count; 1229 1230 for (i = 0; i < dc->caps.max_planes; ++i) 1231 dc->caps.planes[i] = plane_cap; 1232 1233 dc->caps.disable_dp_clk_share = true; 1234 1235 if (!resource_construct(num_virtual_links, dc, &pool->base, 1236 &res_create_funcs)) 1237 goto res_create_fail; 1238 1239 /* Create hardware sequencer */ 1240 dce80_hw_sequencer_construct(dc); 1241 1242 return true; 1243 1244 res_create_fail: 1245 destruct(pool); 1246 return false; 1247 } 1248 1249 struct resource_pool *dce81_create_resource_pool( 1250 uint8_t num_virtual_links, 1251 struct dc *dc) 1252 { 1253 struct dce110_resource_pool *pool = 1254 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1255 1256 if (!pool) 1257 return NULL; 1258 1259 if (dce81_construct(num_virtual_links, dc, pool)) 1260 return &pool->base; 1261 1262 BREAK_TO_DEBUGGER(); 1263 return NULL; 1264 } 1265 1266 static bool dce83_construct( 1267 uint8_t num_virtual_links, 1268 struct dc *dc, 1269 struct dce110_resource_pool *pool) 1270 { 1271 unsigned int i; 1272 struct dc_context *ctx = dc->ctx; 1273 struct dc_bios *bp; 1274 1275 ctx->dc_bios->regs = &bios_regs; 1276 1277 pool->base.res_cap = &res_cap_83; 1278 pool->base.funcs = &dce80_res_pool_funcs; 1279 1280 1281 /************************************************* 1282 * Resource + asic cap harcoding * 1283 *************************************************/ 1284 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1285 pool->base.pipe_count = res_cap_83.num_timing_generator; 1286 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1287 dc->caps.max_downscale_ratio = 200; 1288 dc->caps.i2c_speed_in_khz = 40; 1289 dc->caps.max_cursor_size = 128; 1290 dc->caps.is_apu = true; 1291 1292 /************************************************* 1293 * Create resources * 1294 *************************************************/ 1295 1296 bp = ctx->dc_bios; 1297 1298 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1299 pool->base.dp_clock_source = 1300 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1301 1302 pool->base.clock_sources[0] = 1303 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1304 pool->base.clock_sources[1] = 1305 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1306 pool->base.clk_src_count = 2; 1307 1308 } else { 1309 pool->base.dp_clock_source = 1310 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1311 1312 pool->base.clock_sources[0] = 1313 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1314 pool->base.clk_src_count = 1; 1315 } 1316 1317 if (pool->base.dp_clock_source == NULL) { 1318 dm_error("DC: failed to create dp clock source!\n"); 1319 BREAK_TO_DEBUGGER(); 1320 goto res_create_fail; 1321 } 1322 1323 for (i = 0; i < pool->base.clk_src_count; i++) { 1324 if (pool->base.clock_sources[i] == NULL) { 1325 dm_error("DC: failed to create clock sources!\n"); 1326 BREAK_TO_DEBUGGER(); 1327 goto res_create_fail; 1328 } 1329 } 1330 1331 pool->base.dmcu = dce_dmcu_create(ctx, 1332 &dmcu_regs, 1333 &dmcu_shift, 1334 &dmcu_mask); 1335 if (pool->base.dmcu == NULL) { 1336 dm_error("DC: failed to create dmcu!\n"); 1337 BREAK_TO_DEBUGGER(); 1338 goto res_create_fail; 1339 } 1340 1341 pool->base.abm = dce_abm_create(ctx, 1342 &abm_regs, 1343 &abm_shift, 1344 &abm_mask); 1345 if (pool->base.abm == NULL) { 1346 dm_error("DC: failed to create abm!\n"); 1347 BREAK_TO_DEBUGGER(); 1348 goto res_create_fail; 1349 } 1350 1351 { 1352 struct irq_service_init_data init_data; 1353 init_data.ctx = dc->ctx; 1354 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1355 if (!pool->base.irqs) 1356 goto res_create_fail; 1357 } 1358 1359 for (i = 0; i < pool->base.pipe_count; i++) { 1360 pool->base.timing_generators[i] = dce80_timing_generator_create( 1361 ctx, i, &dce80_tg_offsets[i]); 1362 if (pool->base.timing_generators[i] == NULL) { 1363 BREAK_TO_DEBUGGER(); 1364 dm_error("DC: failed to create tg!\n"); 1365 goto res_create_fail; 1366 } 1367 1368 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1369 if (pool->base.mis[i] == NULL) { 1370 BREAK_TO_DEBUGGER(); 1371 dm_error("DC: failed to create memory input!\n"); 1372 goto res_create_fail; 1373 } 1374 1375 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1376 if (pool->base.ipps[i] == NULL) { 1377 BREAK_TO_DEBUGGER(); 1378 dm_error("DC: failed to create input pixel processor!\n"); 1379 goto res_create_fail; 1380 } 1381 1382 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1383 if (pool->base.transforms[i] == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error("DC: failed to create transform!\n"); 1386 goto res_create_fail; 1387 } 1388 1389 pool->base.opps[i] = dce80_opp_create(ctx, i); 1390 if (pool->base.opps[i] == NULL) { 1391 BREAK_TO_DEBUGGER(); 1392 dm_error("DC: failed to create output pixel processor!\n"); 1393 goto res_create_fail; 1394 } 1395 } 1396 1397 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1398 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1399 if (pool->base.engines[i] == NULL) { 1400 BREAK_TO_DEBUGGER(); 1401 dm_error( 1402 "DC:failed to create aux engine!!\n"); 1403 goto res_create_fail; 1404 } 1405 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1406 if (pool->base.hw_i2cs[i] == NULL) { 1407 BREAK_TO_DEBUGGER(); 1408 dm_error( 1409 "DC:failed to create i2c engine!!\n"); 1410 goto res_create_fail; 1411 } 1412 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1413 if (pool->base.sw_i2cs[i] == NULL) { 1414 BREAK_TO_DEBUGGER(); 1415 dm_error( 1416 "DC:failed to create sw i2c!!\n"); 1417 goto res_create_fail; 1418 } 1419 } 1420 1421 dc->caps.max_planes = pool->base.pipe_count; 1422 1423 for (i = 0; i < dc->caps.max_planes; ++i) 1424 dc->caps.planes[i] = plane_cap; 1425 1426 dc->caps.disable_dp_clk_share = true; 1427 1428 if (!resource_construct(num_virtual_links, dc, &pool->base, 1429 &res_create_funcs)) 1430 goto res_create_fail; 1431 1432 /* Create hardware sequencer */ 1433 dce80_hw_sequencer_construct(dc); 1434 1435 return true; 1436 1437 res_create_fail: 1438 destruct(pool); 1439 return false; 1440 } 1441 1442 struct resource_pool *dce83_create_resource_pool( 1443 uint8_t num_virtual_links, 1444 struct dc *dc) 1445 { 1446 struct dce110_resource_pool *pool = 1447 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1448 1449 if (!pool) 1450 return NULL; 1451 1452 if (dce83_construct(num_virtual_links, dc, pool)) 1453 return &pool->base; 1454 1455 BREAK_TO_DEBUGGER(); 1456 return NULL; 1457 } 1458