1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_mem_input.h" 39 #include "dce110/dce110_resource.h" 40 #include "dce80/dce80_timing_generator.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce80/dce80_mem_input.h" 44 #include "dce80/dce80_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_ipp.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_audio.h" 51 #include "dce/dce_hwseq.h" 52 #include "dce80/dce80_hw_sequencer.h" 53 54 #include "reg_helper.h" 55 56 /* TODO remove this include */ 57 58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 59 #include "gmc/gmc_7_1_d.h" 60 #include "gmc/gmc_7_1_sh_mask.h" 61 #endif 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 72 #endif 73 74 75 #ifndef mmBIOS_SCRATCH_2 76 #define mmBIOS_SCRATCH_2 0x05CB 77 #define mmBIOS_SCRATCH_6 0x05CF 78 #endif 79 80 #ifndef mmDP_DPHY_FAST_TRAINING 81 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 82 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 83 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 84 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 85 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 86 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 87 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 88 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 89 #endif 90 91 92 #ifndef mmHPD_DC_HPD_CONTROL 93 #define mmHPD_DC_HPD_CONTROL 0x189A 94 #define mmHPD0_DC_HPD_CONTROL 0x189A 95 #define mmHPD1_DC_HPD_CONTROL 0x18A2 96 #define mmHPD2_DC_HPD_CONTROL 0x18AA 97 #define mmHPD3_DC_HPD_CONTROL 0x18B2 98 #define mmHPD4_DC_HPD_CONTROL 0x18BA 99 #define mmHPD5_DC_HPD_CONTROL 0x18C2 100 #endif 101 102 #define DCE11_DIG_FE_CNTL 0x4a00 103 #define DCE11_DIG_BE_CNTL 0x4a47 104 #define DCE11_DP_SEC 0x4ac3 105 106 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 107 { 108 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 109 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 110 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 111 - mmDPG_WATERMARK_MASK_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 115 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 116 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 117 - mmDPG_WATERMARK_MASK_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 122 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 123 - mmDPG_WATERMARK_MASK_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 128 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 129 - mmDPG_WATERMARK_MASK_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 135 - mmDPG_WATERMARK_MASK_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 141 - mmDPG_WATERMARK_MASK_CONTROL), 142 } 143 }; 144 145 static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = { 146 { 147 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 148 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 149 - mmDPG_WATERMARK_MASK_CONTROL), 150 .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL 151 - mmPIPE0_DMIF_BUFFER_CONTROL), 152 }, 153 { 154 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 155 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 156 - mmDPG_WATERMARK_MASK_CONTROL), 157 .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL 158 - mmPIPE0_DMIF_BUFFER_CONTROL), 159 }, 160 { 161 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 162 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 163 - mmDPG_WATERMARK_MASK_CONTROL), 164 .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL 165 - mmPIPE0_DMIF_BUFFER_CONTROL), 166 }, 167 { 168 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 169 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 170 - mmDPG_WATERMARK_MASK_CONTROL), 171 .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL 172 - mmPIPE0_DMIF_BUFFER_CONTROL), 173 }, 174 { 175 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 176 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 177 - mmDPG_WATERMARK_MASK_CONTROL), 178 .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL 179 - mmPIPE0_DMIF_BUFFER_CONTROL), 180 }, 181 { 182 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 183 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 184 - mmDPG_WATERMARK_MASK_CONTROL), 185 .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL 186 - mmPIPE0_DMIF_BUFFER_CONTROL), 187 } 188 }; 189 190 static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { 191 { 192 .dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL), 193 }, 194 { 195 .dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL), 196 }, 197 { 198 .dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL), 199 }, 200 { 201 .dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL), 202 }, 203 { 204 .dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL), 205 }, 206 { 207 .dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL), 208 } 209 }; 210 211 /* set register offset */ 212 #define SR(reg_name)\ 213 .reg_name = mm ## reg_name 214 215 /* set register offset with instance */ 216 #define SRI(reg_name, block, id)\ 217 .reg_name = mm ## block ## id ## _ ## reg_name 218 219 220 static const struct dce_disp_clk_registers disp_clk_regs = { 221 CLK_COMMON_REG_LIST_DCE_BASE() 222 }; 223 224 static const struct dce_disp_clk_shift disp_clk_shift = { 225 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 226 }; 227 228 static const struct dce_disp_clk_mask disp_clk_mask = { 229 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 230 }; 231 232 #define transform_regs(id)\ 233 [id] = {\ 234 XFM_COMMON_REG_LIST_DCE_BASE(id)\ 235 } 236 237 static const struct dce_transform_registers xfm_regs[] = { 238 transform_regs(0), 239 transform_regs(1), 240 transform_regs(2), 241 transform_regs(3), 242 transform_regs(4), 243 transform_regs(5) 244 }; 245 246 static const struct dce_transform_shift xfm_shift = { 247 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 248 }; 249 250 static const struct dce_transform_mask xfm_mask = { 251 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 252 }; 253 254 #define aux_regs(id)\ 255 [id] = {\ 256 AUX_REG_LIST(id)\ 257 } 258 259 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 260 aux_regs(0), 261 aux_regs(1), 262 aux_regs(2), 263 aux_regs(3), 264 aux_regs(4), 265 aux_regs(5) 266 }; 267 268 #define hpd_regs(id)\ 269 [id] = {\ 270 HPD_REG_LIST(id)\ 271 } 272 273 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 274 hpd_regs(0), 275 hpd_regs(1), 276 hpd_regs(2), 277 hpd_regs(3), 278 hpd_regs(4), 279 hpd_regs(5) 280 }; 281 282 #define link_regs(id)\ 283 [id] = {\ 284 LE_DCE80_REG_LIST(id)\ 285 } 286 287 static const struct dce110_link_enc_registers link_enc_regs[] = { 288 link_regs(0), 289 link_regs(1), 290 link_regs(2), 291 link_regs(3), 292 link_regs(4), 293 link_regs(5), 294 link_regs(6), 295 }; 296 297 #define stream_enc_regs(id)\ 298 [id] = {\ 299 SE_COMMON_REG_LIST_DCE_BASE(id),\ 300 .AFMT_CNTL = 0,\ 301 } 302 303 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 304 stream_enc_regs(0), 305 stream_enc_regs(1), 306 stream_enc_regs(2), 307 stream_enc_regs(3), 308 stream_enc_regs(4), 309 stream_enc_regs(5) 310 }; 311 312 static const struct dce_stream_encoder_shift se_shift = { 313 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 314 }; 315 316 static const struct dce_stream_encoder_mask se_mask = { 317 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 318 }; 319 320 #define opp_regs(id)\ 321 [id] = {\ 322 OPP_DCE_80_REG_LIST(id),\ 323 } 324 325 static const struct dce_opp_registers opp_regs[] = { 326 opp_regs(0), 327 opp_regs(1), 328 opp_regs(2), 329 opp_regs(3), 330 opp_regs(4), 331 opp_regs(5) 332 }; 333 334 static const struct dce_opp_shift opp_shift = { 335 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 336 }; 337 338 static const struct dce_opp_mask opp_mask = { 339 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 340 }; 341 342 #define audio_regs(id)\ 343 [id] = {\ 344 AUD_COMMON_REG_LIST(id)\ 345 } 346 347 static const struct dce_audio_registers audio_regs[] = { 348 audio_regs(0), 349 audio_regs(1), 350 audio_regs(2), 351 audio_regs(3), 352 audio_regs(4), 353 audio_regs(5), 354 audio_regs(6), 355 }; 356 357 static const struct dce_audio_shift audio_shift = { 358 AUD_COMMON_MASK_SH_LIST(__SHIFT) 359 }; 360 361 static const struct dce_aduio_mask audio_mask = { 362 AUD_COMMON_MASK_SH_LIST(_MASK) 363 }; 364 365 #define clk_src_regs(id)\ 366 [id] = {\ 367 CS_COMMON_REG_LIST_DCE_80(id),\ 368 } 369 370 371 static const struct dce110_clk_src_regs clk_src_regs[] = { 372 clk_src_regs(0), 373 clk_src_regs(1), 374 clk_src_regs(2) 375 }; 376 377 static const struct dce110_clk_src_shift cs_shift = { 378 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 379 }; 380 381 static const struct dce110_clk_src_mask cs_mask = { 382 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 383 }; 384 385 static const struct bios_registers bios_regs = { 386 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 387 }; 388 389 static const struct resource_caps res_cap = { 390 .num_timing_generator = 6, 391 .num_audio = 6, 392 .num_stream_encoder = 6, 393 .num_pll = 3, 394 }; 395 396 #define CTX ctx 397 #define REG(reg) mm ## reg 398 399 #ifndef mmCC_DC_HDMI_STRAPS 400 #define mmCC_DC_HDMI_STRAPS 0x1918 401 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 402 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 403 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 404 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 405 #endif 406 407 static void read_dce_straps( 408 struct dc_context *ctx, 409 struct resource_straps *straps) 410 { 411 REG_GET_2(CC_DC_HDMI_STRAPS, 412 HDMI_DISABLE, &straps->hdmi_disable, 413 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 414 415 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 416 } 417 418 static struct audio *create_audio( 419 struct dc_context *ctx, unsigned int inst) 420 { 421 return dce_audio_create(ctx, inst, 422 &audio_regs[inst], &audio_shift, &audio_mask); 423 } 424 425 static struct timing_generator *dce80_timing_generator_create( 426 struct dc_context *ctx, 427 uint32_t instance, 428 const struct dce110_timing_generator_offsets *offsets) 429 { 430 struct dce110_timing_generator *tg110 = 431 dm_alloc(sizeof(struct dce110_timing_generator)); 432 433 if (!tg110) 434 return NULL; 435 436 if (dce80_timing_generator_construct(tg110, ctx, instance, offsets)) 437 return &tg110->base; 438 439 BREAK_TO_DEBUGGER(); 440 dm_free(tg110); 441 return NULL; 442 } 443 444 static struct output_pixel_processor *dce80_opp_create( 445 struct dc_context *ctx, 446 uint32_t inst) 447 { 448 struct dce110_opp *opp = 449 dm_alloc(sizeof(struct dce110_opp)); 450 451 if (!opp) 452 return NULL; 453 454 if (dce110_opp_construct(opp, 455 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 456 return &opp->base; 457 458 BREAK_TO_DEBUGGER(); 459 dm_free(opp); 460 return NULL; 461 } 462 463 static struct stream_encoder *dce80_stream_encoder_create( 464 enum engine_id eng_id, 465 struct dc_context *ctx) 466 { 467 struct dce110_stream_encoder *enc110 = 468 dm_alloc(sizeof(struct dce110_stream_encoder)); 469 470 if (!enc110) 471 return NULL; 472 473 if (dce110_stream_encoder_construct( 474 enc110, ctx, ctx->dc_bios, eng_id, 475 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 476 return &enc110->base; 477 478 BREAK_TO_DEBUGGER(); 479 dm_free(enc110); 480 return NULL; 481 } 482 483 #define SRII(reg_name, block, id)\ 484 .reg_name[id] = mm ## block ## id ## _ ## reg_name 485 486 static const struct dce_hwseq_registers hwseq_reg = { 487 HWSEQ_DCE8_REG_LIST() 488 }; 489 490 static const struct dce_hwseq_shift hwseq_shift = { 491 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 492 }; 493 494 static const struct dce_hwseq_mask hwseq_mask = { 495 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 496 }; 497 498 static struct dce_hwseq *dce80_hwseq_create( 499 struct dc_context *ctx) 500 { 501 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); 502 503 if (hws) { 504 hws->ctx = ctx; 505 hws->regs = &hwseq_reg; 506 hws->shifts = &hwseq_shift; 507 hws->masks = &hwseq_mask; 508 } 509 return hws; 510 } 511 512 static const struct resource_create_funcs res_create_funcs = { 513 .read_dce_straps = read_dce_straps, 514 .create_audio = create_audio, 515 .create_stream_encoder = dce80_stream_encoder_create, 516 .create_hwseq = dce80_hwseq_create, 517 }; 518 519 #define mi_inst_regs(id) { \ 520 MI_DCE8_REG_LIST(id), \ 521 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 522 } 523 static const struct dce_mem_input_registers mi_regs[] = { 524 mi_inst_regs(0), 525 mi_inst_regs(1), 526 mi_inst_regs(2), 527 mi_inst_regs(3), 528 mi_inst_regs(4), 529 mi_inst_regs(5), 530 }; 531 532 static const struct dce_mem_input_shift mi_shifts = { 533 MI_DCE8_MASK_SH_LIST(__SHIFT), 534 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 535 }; 536 537 static const struct dce_mem_input_mask mi_masks = { 538 MI_DCE8_MASK_SH_LIST(_MASK), 539 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 540 }; 541 542 static struct mem_input *dce80_mem_input_create( 543 struct dc_context *ctx, 544 uint32_t inst, 545 const struct dce110_mem_input_reg_offsets *offsets) 546 { 547 struct dce110_mem_input *mem_input80 = 548 dm_alloc(sizeof(struct dce110_mem_input)); 549 550 if (!mem_input80) 551 return NULL; 552 553 if (dce80_mem_input_construct(mem_input80, ctx, inst, offsets)) { 554 struct mem_input *mi = &mem_input80->base; 555 556 mi->regs = &mi_regs[inst]; 557 mi->shifts = &mi_shifts; 558 mi->masks = &mi_masks; 559 mi->wa.single_head_rdreq_dmif_limit = 2; 560 return mi; 561 } 562 563 BREAK_TO_DEBUGGER(); 564 dm_free(mem_input80); 565 return NULL; 566 } 567 568 static void dce80_transform_destroy(struct transform **xfm) 569 { 570 dm_free(TO_DCE_TRANSFORM(*xfm)); 571 *xfm = NULL; 572 } 573 574 static struct transform *dce80_transform_create( 575 struct dc_context *ctx, 576 uint32_t inst) 577 { 578 struct dce_transform *transform = 579 dm_alloc(sizeof(struct dce_transform)); 580 581 if (!transform) 582 return NULL; 583 584 if (dce_transform_construct(transform, ctx, inst, 585 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 586 transform->prescaler_on = false; 587 return &transform->base; 588 } 589 590 BREAK_TO_DEBUGGER(); 591 dm_free(transform); 592 return NULL; 593 } 594 595 static struct input_pixel_processor *dce80_ipp_create( 596 struct dc_context *ctx, 597 uint32_t inst, 598 const struct dce110_ipp_reg_offsets *offset) 599 { 600 struct dce110_ipp *ipp = 601 dm_alloc(sizeof(struct dce110_ipp)); 602 603 if (!ipp) 604 return NULL; 605 606 if (dce80_ipp_construct(ipp, ctx, inst, offset)) 607 return &ipp->base; 608 609 BREAK_TO_DEBUGGER(); 610 dm_free(ipp); 611 return NULL; 612 } 613 614 static const struct encoder_feature_support link_enc_feature = { 615 .max_hdmi_deep_color = COLOR_DEPTH_121212, 616 .max_hdmi_pixel_clock = 297000, 617 .flags.bits.IS_HBR2_CAPABLE = true, 618 .flags.bits.IS_TPS3_CAPABLE = true, 619 .flags.bits.IS_YCBCR_CAPABLE = true 620 }; 621 622 struct link_encoder *dce80_link_encoder_create( 623 const struct encoder_init_data *enc_init_data) 624 { 625 struct dce110_link_encoder *enc110 = 626 dm_alloc(sizeof(struct dce110_link_encoder)); 627 628 if (!enc110) 629 return NULL; 630 631 if (dce110_link_encoder_construct( 632 enc110, 633 enc_init_data, 634 &link_enc_feature, 635 &link_enc_regs[enc_init_data->transmitter], 636 &link_enc_aux_regs[enc_init_data->channel - 1], 637 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 638 639 return &enc110->base; 640 } 641 642 BREAK_TO_DEBUGGER(); 643 dm_free(enc110); 644 return NULL; 645 } 646 647 struct clock_source *dce80_clock_source_create( 648 struct dc_context *ctx, 649 struct dc_bios *bios, 650 enum clock_source_id id, 651 const struct dce110_clk_src_regs *regs, 652 bool dp_clk_src) 653 { 654 struct dce110_clk_src *clk_src = 655 dm_alloc(sizeof(struct dce110_clk_src)); 656 657 if (!clk_src) 658 return NULL; 659 660 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 661 regs, &cs_shift, &cs_mask)) { 662 clk_src->base.dp_clk_src = dp_clk_src; 663 return &clk_src->base; 664 } 665 666 BREAK_TO_DEBUGGER(); 667 return NULL; 668 } 669 670 void dce80_clock_source_destroy(struct clock_source **clk_src) 671 { 672 dm_free(TO_DCE110_CLK_SRC(*clk_src)); 673 *clk_src = NULL; 674 } 675 676 static void destruct(struct dce110_resource_pool *pool) 677 { 678 unsigned int i; 679 680 for (i = 0; i < pool->base.pipe_count; i++) { 681 if (pool->base.opps[i] != NULL) 682 dce110_opp_destroy(&pool->base.opps[i]); 683 684 if (pool->base.transforms[i] != NULL) 685 dce80_transform_destroy(&pool->base.transforms[i]); 686 687 if (pool->base.ipps[i] != NULL) 688 dce80_ipp_destroy(&pool->base.ipps[i]); 689 690 if (pool->base.mis[i] != NULL) { 691 dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); 692 pool->base.mis[i] = NULL; 693 } 694 695 if (pool->base.timing_generators[i] != NULL) { 696 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 697 pool->base.timing_generators[i] = NULL; 698 } 699 } 700 701 for (i = 0; i < pool->base.stream_enc_count; i++) { 702 if (pool->base.stream_enc[i] != NULL) 703 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 704 } 705 706 for (i = 0; i < pool->base.clk_src_count; i++) { 707 if (pool->base.clock_sources[i] != NULL) { 708 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 709 } 710 } 711 712 if (pool->base.dp_clock_source != NULL) 713 dce80_clock_source_destroy(&pool->base.dp_clock_source); 714 715 for (i = 0; i < pool->base.audio_count; i++) { 716 if (pool->base.audios[i] != NULL) { 717 dce_aud_destroy(&pool->base.audios[i]); 718 } 719 } 720 721 if (pool->base.display_clock != NULL) 722 dce_disp_clk_destroy(&pool->base.display_clock); 723 724 if (pool->base.irqs != NULL) { 725 dal_irq_service_destroy(&pool->base.irqs); 726 } 727 } 728 729 static enum dc_status validate_mapped_resource( 730 const struct core_dc *dc, 731 struct validate_context *context) 732 { 733 enum dc_status status = DC_OK; 734 uint8_t i, j; 735 736 for (i = 0; i < context->stream_count; i++) { 737 struct core_stream *stream = context->streams[i]; 738 struct core_link *link = stream->sink->link; 739 740 if (resource_is_stream_unchanged(dc->current_context, stream)) 741 continue; 742 743 for (j = 0; j < MAX_PIPES; j++) { 744 struct pipe_ctx *pipe_ctx = 745 &context->res_ctx.pipe_ctx[j]; 746 747 if (context->res_ctx.pipe_ctx[j].stream != stream) 748 continue; 749 750 if (!pipe_ctx->tg->funcs->validate_timing( 751 pipe_ctx->tg, &stream->public.timing)) 752 return DC_FAIL_CONTROLLER_VALIDATE; 753 754 status = dce110_resource_build_pipe_hw_param(pipe_ctx); 755 756 if (status != DC_OK) 757 return status; 758 759 if (!link->link_enc->funcs->validate_output_with_stream( 760 link->link_enc, 761 pipe_ctx)) 762 return DC_FAIL_ENC_VALIDATE; 763 764 /* TODO: validate audio ASIC caps, encoder */ 765 766 status = dc_link_validate_mode_timing(stream, 767 link, 768 &stream->public.timing); 769 770 if (status != DC_OK) 771 return status; 772 773 resource_build_info_frame(pipe_ctx); 774 775 /* do not need to validate non root pipes */ 776 break; 777 } 778 } 779 780 return DC_OK; 781 } 782 783 enum dc_status dce80_validate_bandwidth( 784 const struct core_dc *dc, 785 struct validate_context *context) 786 { 787 /* TODO implement when needed but for now hardcode max value*/ 788 context->bw_results.dispclk_khz = 681000; 789 context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; 790 791 return DC_OK; 792 } 793 794 static bool dce80_validate_surface_sets( 795 const struct dc_validation_set set[], 796 int set_count) 797 { 798 int i; 799 800 for (i = 0; i < set_count; i++) { 801 if (set[i].surface_count == 0) 802 continue; 803 804 if (set[i].surface_count > 1) 805 return false; 806 807 if (set[i].surfaces[0]->clip_rect.width 808 != set[i].stream->src.width 809 || set[i].surfaces[0]->clip_rect.height 810 != set[i].stream->src.height) 811 return false; 812 if (set[i].surfaces[0]->format 813 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 814 return false; 815 } 816 817 return true; 818 } 819 820 enum dc_status dce80_validate_with_context( 821 const struct core_dc *dc, 822 const struct dc_validation_set set[], 823 int set_count, 824 struct validate_context *context) 825 { 826 struct dc_context *dc_ctx = dc->ctx; 827 enum dc_status result = DC_ERROR_UNEXPECTED; 828 int i; 829 830 if (!dce80_validate_surface_sets(set, set_count)) 831 return DC_FAIL_SURFACE_VALIDATE; 832 833 context->res_ctx.pool = dc->res_pool; 834 835 for (i = 0; i < set_count; i++) { 836 context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); 837 dc_stream_retain(&context->streams[i]->public); 838 context->stream_count++; 839 } 840 841 result = resource_map_pool_resources(dc, context); 842 843 if (result == DC_OK) 844 result = resource_map_clock_resources(dc, context); 845 846 if (!resource_validate_attach_surfaces( 847 set, set_count, dc->current_context, context)) { 848 DC_ERROR("Failed to attach surface to stream!\n"); 849 return DC_FAIL_ATTACH_SURFACES; 850 } 851 852 if (result == DC_OK) 853 result = validate_mapped_resource(dc, context); 854 855 if (result == DC_OK) 856 result = resource_build_scaling_params_for_context(dc, context); 857 858 if (result == DC_OK) 859 result = dce80_validate_bandwidth(dc, context); 860 861 return result; 862 } 863 864 enum dc_status dce80_validate_guaranteed( 865 const struct core_dc *dc, 866 const struct dc_stream *dc_stream, 867 struct validate_context *context) 868 { 869 enum dc_status result = DC_ERROR_UNEXPECTED; 870 871 context->res_ctx.pool = dc->res_pool; 872 873 context->streams[0] = DC_STREAM_TO_CORE(dc_stream); 874 dc_stream_retain(&context->streams[0]->public); 875 context->stream_count++; 876 877 result = resource_map_pool_resources(dc, context); 878 879 if (result == DC_OK) 880 result = resource_map_clock_resources(dc, context); 881 882 if (result == DC_OK) 883 result = validate_mapped_resource(dc, context); 884 885 if (result == DC_OK) { 886 validate_guaranteed_copy_streams( 887 context, dc->public.caps.max_streams); 888 result = resource_build_scaling_params_for_context(dc, context); 889 } 890 891 if (result == DC_OK) 892 result = dce80_validate_bandwidth(dc, context); 893 894 return result; 895 } 896 897 static void dce80_destroy_resource_pool(struct resource_pool **pool) 898 { 899 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 900 901 destruct(dce110_pool); 902 dm_free(dce110_pool); 903 *pool = NULL; 904 } 905 906 static const struct resource_funcs dce80_res_pool_funcs = { 907 .destroy = dce80_destroy_resource_pool, 908 .link_enc_create = dce80_link_encoder_create, 909 .validate_with_context = dce80_validate_with_context, 910 .validate_guaranteed = dce80_validate_guaranteed, 911 .validate_bandwidth = dce80_validate_bandwidth 912 }; 913 914 static bool construct( 915 uint8_t num_virtual_links, 916 struct core_dc *dc, 917 struct dce110_resource_pool *pool) 918 { 919 unsigned int i; 920 struct dc_context *ctx = dc->ctx; 921 struct firmware_info info; 922 struct dc_bios *bp; 923 struct dm_pp_static_clock_info static_clk_info = {0}; 924 925 ctx->dc_bios->regs = &bios_regs; 926 927 pool->base.res_cap = &res_cap; 928 pool->base.funcs = &dce80_res_pool_funcs; 929 930 931 /************************************************* 932 * Resource + asic cap harcoding * 933 *************************************************/ 934 pool->base.underlay_pipe_index = -1; 935 pool->base.pipe_count = res_cap.num_timing_generator; 936 dc->public.caps.max_downscale_ratio = 200; 937 dc->public.caps.i2c_speed_in_khz = 40; 938 939 /************************************************* 940 * Create resources * 941 *************************************************/ 942 943 bp = ctx->dc_bios; 944 945 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 946 info.external_clock_source_frequency_for_dp != 0) { 947 pool->base.dp_clock_source = 948 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 949 950 pool->base.clock_sources[0] = 951 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 952 pool->base.clock_sources[1] = 953 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 954 pool->base.clock_sources[2] = 955 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 956 pool->base.clk_src_count = 3; 957 958 } else { 959 pool->base.dp_clock_source = 960 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 961 962 pool->base.clock_sources[0] = 963 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 964 pool->base.clock_sources[1] = 965 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 966 pool->base.clk_src_count = 2; 967 } 968 969 if (pool->base.dp_clock_source == NULL) { 970 dm_error("DC: failed to create dp clock source!\n"); 971 BREAK_TO_DEBUGGER(); 972 goto res_create_fail; 973 } 974 975 for (i = 0; i < pool->base.clk_src_count; i++) { 976 if (pool->base.clock_sources[i] == NULL) { 977 dm_error("DC: failed to create clock sources!\n"); 978 BREAK_TO_DEBUGGER(); 979 goto res_create_fail; 980 } 981 } 982 983 pool->base.display_clock = dce_disp_clk_create(ctx, 984 &disp_clk_regs, 985 &disp_clk_shift, 986 &disp_clk_mask); 987 if (pool->base.display_clock == NULL) { 988 dm_error("DC: failed to create display clock!\n"); 989 BREAK_TO_DEBUGGER(); 990 goto res_create_fail; 991 } 992 993 994 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 995 pool->base.display_clock->max_clks_state = 996 static_clk_info.max_clocks_state; 997 998 { 999 struct irq_service_init_data init_data; 1000 init_data.ctx = dc->ctx; 1001 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1002 if (!pool->base.irqs) 1003 goto res_create_fail; 1004 } 1005 1006 for (i = 0; i < pool->base.pipe_count; i++) { 1007 pool->base.timing_generators[i] = dce80_timing_generator_create( 1008 ctx, i, &dce80_tg_offsets[i]); 1009 if (pool->base.timing_generators[i] == NULL) { 1010 BREAK_TO_DEBUGGER(); 1011 dm_error("DC: failed to create tg!\n"); 1012 goto res_create_fail; 1013 } 1014 1015 pool->base.mis[i] = dce80_mem_input_create(ctx, i, 1016 &dce80_mi_reg_offsets[i]); 1017 if (pool->base.mis[i] == NULL) { 1018 BREAK_TO_DEBUGGER(); 1019 dm_error("DC: failed to create memory input!\n"); 1020 goto res_create_fail; 1021 } 1022 1023 pool->base.ipps[i] = dce80_ipp_create(ctx, i, &ipp_reg_offsets[i]); 1024 if (pool->base.ipps[i] == NULL) { 1025 BREAK_TO_DEBUGGER(); 1026 dm_error("DC: failed to create input pixel processor!\n"); 1027 goto res_create_fail; 1028 } 1029 1030 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1031 if (pool->base.transforms[i] == NULL) { 1032 BREAK_TO_DEBUGGER(); 1033 dm_error("DC: failed to create transform!\n"); 1034 goto res_create_fail; 1035 } 1036 1037 pool->base.opps[i] = dce80_opp_create(ctx, i); 1038 if (pool->base.opps[i] == NULL) { 1039 BREAK_TO_DEBUGGER(); 1040 dm_error("DC: failed to create output pixel processor!\n"); 1041 goto res_create_fail; 1042 } 1043 } 1044 1045 if (!resource_construct(num_virtual_links, dc, &pool->base, 1046 &res_create_funcs)) 1047 goto res_create_fail; 1048 1049 /* Create hardware sequencer */ 1050 if (!dce80_hw_sequencer_construct(dc)) 1051 goto res_create_fail; 1052 1053 return true; 1054 1055 res_create_fail: 1056 destruct(pool); 1057 return false; 1058 } 1059 1060 struct resource_pool *dce80_create_resource_pool( 1061 uint8_t num_virtual_links, 1062 struct core_dc *dc) 1063 { 1064 struct dce110_resource_pool *pool = 1065 dm_alloc(sizeof(struct dce110_resource_pool)); 1066 1067 if (!pool) 1068 return NULL; 1069 1070 if (construct(num_virtual_links, dc, pool)) 1071 return &pool->base; 1072 1073 BREAK_TO_DEBUGGER(); 1074 return NULL; 1075 } 1076 1077