1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce/dce_opp.h" 46 #include "dce/dce_clock_source.h" 47 #include "dce/dce_audio.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce80/dce80_hw_sequencer.h" 50 #include "dce100/dce100_resource.h" 51 52 #include "reg_helper.h" 53 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_aux.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_i2c.h" 58 /* TODO remove this include */ 59 60 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 61 #include "gmc/gmc_7_1_d.h" 62 #include "gmc/gmc_7_1_sh_mask.h" 63 #endif 64 65 #ifndef mmDP_DPHY_INTERNAL_CTRL 66 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 74 #endif 75 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_FAST_TRAINING 84 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 85 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 87 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 88 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 89 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 90 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 91 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 92 #endif 93 94 95 #ifndef mmHPD_DC_HPD_CONTROL 96 #define mmHPD_DC_HPD_CONTROL 0x189A 97 #define mmHPD0_DC_HPD_CONTROL 0x189A 98 #define mmHPD1_DC_HPD_CONTROL 0x18A2 99 #define mmHPD2_DC_HPD_CONTROL 0x18AA 100 #define mmHPD3_DC_HPD_CONTROL 0x18B2 101 #define mmHPD4_DC_HPD_CONTROL 0x18BA 102 #define mmHPD5_DC_HPD_CONTROL 0x18C2 103 #endif 104 105 #define DCE11_DIG_FE_CNTL 0x4a00 106 #define DCE11_DIG_BE_CNTL 0x4a47 107 #define DCE11_DP_SEC 0x4ac3 108 109 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 110 { 111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 112 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 113 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 114 - mmDPG_WATERMARK_MASK_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 119 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 120 - mmDPG_WATERMARK_MASK_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 125 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 126 - mmDPG_WATERMARK_MASK_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 132 - mmDPG_WATERMARK_MASK_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 138 - mmDPG_WATERMARK_MASK_CONTROL), 139 }, 140 { 141 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 142 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 143 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 144 - mmDPG_WATERMARK_MASK_CONTROL), 145 } 146 }; 147 148 /* set register offset */ 149 #define SR(reg_name)\ 150 .reg_name = mm ## reg_name 151 152 /* set register offset with instance */ 153 #define SRI(reg_name, block, id)\ 154 .reg_name = mm ## block ## id ## _ ## reg_name 155 156 #define ipp_regs(id)\ 157 [id] = {\ 158 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 159 } 160 161 static const struct dce_ipp_registers ipp_regs[] = { 162 ipp_regs(0), 163 ipp_regs(1), 164 ipp_regs(2), 165 ipp_regs(3), 166 ipp_regs(4), 167 ipp_regs(5) 168 }; 169 170 static const struct dce_ipp_shift ipp_shift = { 171 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 172 }; 173 174 static const struct dce_ipp_mask ipp_mask = { 175 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 176 }; 177 178 #define transform_regs(id)\ 179 [id] = {\ 180 XFM_COMMON_REG_LIST_DCE80(id)\ 181 } 182 183 static const struct dce_transform_registers xfm_regs[] = { 184 transform_regs(0), 185 transform_regs(1), 186 transform_regs(2), 187 transform_regs(3), 188 transform_regs(4), 189 transform_regs(5) 190 }; 191 192 static const struct dce_transform_shift xfm_shift = { 193 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 194 }; 195 196 static const struct dce_transform_mask xfm_mask = { 197 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 198 }; 199 200 #define aux_regs(id)\ 201 [id] = {\ 202 AUX_REG_LIST(id)\ 203 } 204 205 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 206 aux_regs(0), 207 aux_regs(1), 208 aux_regs(2), 209 aux_regs(3), 210 aux_regs(4), 211 aux_regs(5) 212 }; 213 214 #define hpd_regs(id)\ 215 [id] = {\ 216 HPD_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 220 hpd_regs(0), 221 hpd_regs(1), 222 hpd_regs(2), 223 hpd_regs(3), 224 hpd_regs(4), 225 hpd_regs(5) 226 }; 227 228 #define link_regs(id)\ 229 [id] = {\ 230 LE_DCE80_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_registers link_enc_regs[] = { 234 link_regs(0), 235 link_regs(1), 236 link_regs(2), 237 link_regs(3), 238 link_regs(4), 239 link_regs(5), 240 link_regs(6), 241 }; 242 243 #define stream_enc_regs(id)\ 244 [id] = {\ 245 SE_COMMON_REG_LIST_DCE_BASE(id),\ 246 .AFMT_CNTL = 0,\ 247 } 248 249 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 250 stream_enc_regs(0), 251 stream_enc_regs(1), 252 stream_enc_regs(2), 253 stream_enc_regs(3), 254 stream_enc_regs(4), 255 stream_enc_regs(5), 256 stream_enc_regs(6) 257 }; 258 259 static const struct dce_stream_encoder_shift se_shift = { 260 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 261 }; 262 263 static const struct dce_stream_encoder_mask se_mask = { 264 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 265 }; 266 267 #define opp_regs(id)\ 268 [id] = {\ 269 OPP_DCE_80_REG_LIST(id),\ 270 } 271 272 static const struct dce_opp_registers opp_regs[] = { 273 opp_regs(0), 274 opp_regs(1), 275 opp_regs(2), 276 opp_regs(3), 277 opp_regs(4), 278 opp_regs(5) 279 }; 280 281 static const struct dce_opp_shift opp_shift = { 282 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 283 }; 284 285 static const struct dce_opp_mask opp_mask = { 286 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 287 }; 288 289 #define aux_engine_regs(id)\ 290 [id] = {\ 291 AUX_COMMON_REG_LIST(id), \ 292 .AUX_RESET_MASK = 0 \ 293 } 294 295 static const struct dce110_aux_registers aux_engine_regs[] = { 296 aux_engine_regs(0), 297 aux_engine_regs(1), 298 aux_engine_regs(2), 299 aux_engine_regs(3), 300 aux_engine_regs(4), 301 aux_engine_regs(5) 302 }; 303 304 #define audio_regs(id)\ 305 [id] = {\ 306 AUD_COMMON_REG_LIST(id)\ 307 } 308 309 static const struct dce_audio_registers audio_regs[] = { 310 audio_regs(0), 311 audio_regs(1), 312 audio_regs(2), 313 audio_regs(3), 314 audio_regs(4), 315 audio_regs(5), 316 audio_regs(6), 317 }; 318 319 static const struct dce_audio_shift audio_shift = { 320 AUD_COMMON_MASK_SH_LIST(__SHIFT) 321 }; 322 323 static const struct dce_aduio_mask audio_mask = { 324 AUD_COMMON_MASK_SH_LIST(_MASK) 325 }; 326 327 #define clk_src_regs(id)\ 328 [id] = {\ 329 CS_COMMON_REG_LIST_DCE_80(id),\ 330 } 331 332 333 static const struct dce110_clk_src_regs clk_src_regs[] = { 334 clk_src_regs(0), 335 clk_src_regs(1), 336 clk_src_regs(2) 337 }; 338 339 static const struct dce110_clk_src_shift cs_shift = { 340 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 341 }; 342 343 static const struct dce110_clk_src_mask cs_mask = { 344 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 345 }; 346 347 static const struct bios_registers bios_regs = { 348 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 349 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 350 }; 351 352 static const struct resource_caps res_cap = { 353 .num_timing_generator = 6, 354 .num_audio = 6, 355 .num_stream_encoder = 6, 356 .num_pll = 3, 357 .num_ddc = 6, 358 }; 359 360 static const struct resource_caps res_cap_81 = { 361 .num_timing_generator = 4, 362 .num_audio = 7, 363 .num_stream_encoder = 7, 364 .num_pll = 3, 365 .num_ddc = 6, 366 }; 367 368 static const struct resource_caps res_cap_83 = { 369 .num_timing_generator = 2, 370 .num_audio = 6, 371 .num_stream_encoder = 6, 372 .num_pll = 2, 373 .num_ddc = 2, 374 }; 375 376 static const struct dc_plane_cap plane_cap = { 377 .type = DC_PLANE_TYPE_DCE_RGB, 378 379 .pixel_format_support = { 380 .argb8888 = true, 381 .nv12 = false, 382 .fp16 = false 383 }, 384 385 .max_upscale_factor = { 386 .argb8888 = 16000, 387 .nv12 = 1, 388 .fp16 = 1 389 }, 390 391 .max_downscale_factor = { 392 .argb8888 = 250, 393 .nv12 = 1, 394 .fp16 = 1 395 } 396 }; 397 398 static const struct dce_dmcu_registers dmcu_regs = { 399 DMCU_DCE80_REG_LIST() 400 }; 401 402 static const struct dce_dmcu_shift dmcu_shift = { 403 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 404 }; 405 406 static const struct dce_dmcu_mask dmcu_mask = { 407 DMCU_MASK_SH_LIST_DCE80(_MASK) 408 }; 409 static const struct dce_abm_registers abm_regs = { 410 ABM_DCE110_COMMON_REG_LIST() 411 }; 412 413 static const struct dce_abm_shift abm_shift = { 414 ABM_MASK_SH_LIST_DCE110(__SHIFT) 415 }; 416 417 static const struct dce_abm_mask abm_mask = { 418 ABM_MASK_SH_LIST_DCE110(_MASK) 419 }; 420 421 #define CTX ctx 422 #define REG(reg) mm ## reg 423 424 #ifndef mmCC_DC_HDMI_STRAPS 425 #define mmCC_DC_HDMI_STRAPS 0x1918 426 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 427 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 428 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 429 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 430 #endif 431 432 static void read_dce_straps( 433 struct dc_context *ctx, 434 struct resource_straps *straps) 435 { 436 REG_GET_2(CC_DC_HDMI_STRAPS, 437 HDMI_DISABLE, &straps->hdmi_disable, 438 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 439 440 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 441 } 442 443 static struct audio *create_audio( 444 struct dc_context *ctx, unsigned int inst) 445 { 446 return dce_audio_create(ctx, inst, 447 &audio_regs[inst], &audio_shift, &audio_mask); 448 } 449 450 static struct timing_generator *dce80_timing_generator_create( 451 struct dc_context *ctx, 452 uint32_t instance, 453 const struct dce110_timing_generator_offsets *offsets) 454 { 455 struct dce110_timing_generator *tg110 = 456 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 457 458 if (!tg110) 459 return NULL; 460 461 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 462 return &tg110->base; 463 } 464 465 static struct output_pixel_processor *dce80_opp_create( 466 struct dc_context *ctx, 467 uint32_t inst) 468 { 469 struct dce110_opp *opp = 470 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 471 472 if (!opp) 473 return NULL; 474 475 dce110_opp_construct(opp, 476 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 477 return &opp->base; 478 } 479 480 struct dce_aux *dce80_aux_engine_create( 481 struct dc_context *ctx, 482 uint32_t inst) 483 { 484 struct aux_engine_dce110 *aux_engine = 485 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 486 487 if (!aux_engine) 488 return NULL; 489 490 dce110_aux_engine_construct(aux_engine, ctx, inst, 491 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 492 &aux_engine_regs[inst]); 493 494 return &aux_engine->base; 495 } 496 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 497 498 static const struct dce_i2c_registers i2c_hw_regs[] = { 499 i2c_inst_regs(1), 500 i2c_inst_regs(2), 501 i2c_inst_regs(3), 502 i2c_inst_regs(4), 503 i2c_inst_regs(5), 504 i2c_inst_regs(6), 505 }; 506 507 static const struct dce_i2c_shift i2c_shifts = { 508 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 509 }; 510 511 static const struct dce_i2c_mask i2c_masks = { 512 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 513 }; 514 515 struct dce_i2c_hw *dce80_i2c_hw_create( 516 struct dc_context *ctx, 517 uint32_t inst) 518 { 519 struct dce_i2c_hw *dce_i2c_hw = 520 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 521 522 if (!dce_i2c_hw) 523 return NULL; 524 525 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 526 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 527 528 return dce_i2c_hw; 529 } 530 531 struct dce_i2c_sw *dce80_i2c_sw_create( 532 struct dc_context *ctx) 533 { 534 struct dce_i2c_sw *dce_i2c_sw = 535 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 536 537 if (!dce_i2c_sw) 538 return NULL; 539 540 dce_i2c_sw_construct(dce_i2c_sw, ctx); 541 542 return dce_i2c_sw; 543 } 544 static struct stream_encoder *dce80_stream_encoder_create( 545 enum engine_id eng_id, 546 struct dc_context *ctx) 547 { 548 struct dce110_stream_encoder *enc110 = 549 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 550 551 if (!enc110) 552 return NULL; 553 554 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 555 &stream_enc_regs[eng_id], 556 &se_shift, &se_mask); 557 return &enc110->base; 558 } 559 560 #define SRII(reg_name, block, id)\ 561 .reg_name[id] = mm ## block ## id ## _ ## reg_name 562 563 static const struct dce_hwseq_registers hwseq_reg = { 564 HWSEQ_DCE8_REG_LIST() 565 }; 566 567 static const struct dce_hwseq_shift hwseq_shift = { 568 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 569 }; 570 571 static const struct dce_hwseq_mask hwseq_mask = { 572 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 573 }; 574 575 static struct dce_hwseq *dce80_hwseq_create( 576 struct dc_context *ctx) 577 { 578 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 579 580 if (hws) { 581 hws->ctx = ctx; 582 hws->regs = &hwseq_reg; 583 hws->shifts = &hwseq_shift; 584 hws->masks = &hwseq_mask; 585 } 586 return hws; 587 } 588 589 static const struct resource_create_funcs res_create_funcs = { 590 .read_dce_straps = read_dce_straps, 591 .create_audio = create_audio, 592 .create_stream_encoder = dce80_stream_encoder_create, 593 .create_hwseq = dce80_hwseq_create, 594 }; 595 596 #define mi_inst_regs(id) { \ 597 MI_DCE8_REG_LIST(id), \ 598 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 599 } 600 static const struct dce_mem_input_registers mi_regs[] = { 601 mi_inst_regs(0), 602 mi_inst_regs(1), 603 mi_inst_regs(2), 604 mi_inst_regs(3), 605 mi_inst_regs(4), 606 mi_inst_regs(5), 607 }; 608 609 static const struct dce_mem_input_shift mi_shifts = { 610 MI_DCE8_MASK_SH_LIST(__SHIFT), 611 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 612 }; 613 614 static const struct dce_mem_input_mask mi_masks = { 615 MI_DCE8_MASK_SH_LIST(_MASK), 616 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 617 }; 618 619 static struct mem_input *dce80_mem_input_create( 620 struct dc_context *ctx, 621 uint32_t inst) 622 { 623 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 624 GFP_KERNEL); 625 626 if (!dce_mi) { 627 BREAK_TO_DEBUGGER(); 628 return NULL; 629 } 630 631 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 632 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 633 return &dce_mi->base; 634 } 635 636 static void dce80_transform_destroy(struct transform **xfm) 637 { 638 kfree(TO_DCE_TRANSFORM(*xfm)); 639 *xfm = NULL; 640 } 641 642 static struct transform *dce80_transform_create( 643 struct dc_context *ctx, 644 uint32_t inst) 645 { 646 struct dce_transform *transform = 647 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 648 649 if (!transform) 650 return NULL; 651 652 dce_transform_construct(transform, ctx, inst, 653 &xfm_regs[inst], &xfm_shift, &xfm_mask); 654 transform->prescaler_on = false; 655 return &transform->base; 656 } 657 658 static const struct encoder_feature_support link_enc_feature = { 659 .max_hdmi_deep_color = COLOR_DEPTH_121212, 660 .max_hdmi_pixel_clock = 297000, 661 .flags.bits.IS_HBR2_CAPABLE = true, 662 .flags.bits.IS_TPS3_CAPABLE = true 663 }; 664 665 struct link_encoder *dce80_link_encoder_create( 666 const struct encoder_init_data *enc_init_data) 667 { 668 struct dce110_link_encoder *enc110 = 669 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 670 671 if (!enc110) 672 return NULL; 673 674 dce110_link_encoder_construct(enc110, 675 enc_init_data, 676 &link_enc_feature, 677 &link_enc_regs[enc_init_data->transmitter], 678 &link_enc_aux_regs[enc_init_data->channel - 1], 679 &link_enc_hpd_regs[enc_init_data->hpd_source]); 680 return &enc110->base; 681 } 682 683 struct clock_source *dce80_clock_source_create( 684 struct dc_context *ctx, 685 struct dc_bios *bios, 686 enum clock_source_id id, 687 const struct dce110_clk_src_regs *regs, 688 bool dp_clk_src) 689 { 690 struct dce110_clk_src *clk_src = 691 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 692 693 if (!clk_src) 694 return NULL; 695 696 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 697 regs, &cs_shift, &cs_mask)) { 698 clk_src->base.dp_clk_src = dp_clk_src; 699 return &clk_src->base; 700 } 701 702 BREAK_TO_DEBUGGER(); 703 return NULL; 704 } 705 706 void dce80_clock_source_destroy(struct clock_source **clk_src) 707 { 708 kfree(TO_DCE110_CLK_SRC(*clk_src)); 709 *clk_src = NULL; 710 } 711 712 static struct input_pixel_processor *dce80_ipp_create( 713 struct dc_context *ctx, uint32_t inst) 714 { 715 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 716 717 if (!ipp) { 718 BREAK_TO_DEBUGGER(); 719 return NULL; 720 } 721 722 dce_ipp_construct(ipp, ctx, inst, 723 &ipp_regs[inst], &ipp_shift, &ipp_mask); 724 return &ipp->base; 725 } 726 727 static void destruct(struct dce110_resource_pool *pool) 728 { 729 unsigned int i; 730 731 for (i = 0; i < pool->base.pipe_count; i++) { 732 if (pool->base.opps[i] != NULL) 733 dce110_opp_destroy(&pool->base.opps[i]); 734 735 if (pool->base.transforms[i] != NULL) 736 dce80_transform_destroy(&pool->base.transforms[i]); 737 738 if (pool->base.ipps[i] != NULL) 739 dce_ipp_destroy(&pool->base.ipps[i]); 740 741 if (pool->base.mis[i] != NULL) { 742 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 743 pool->base.mis[i] = NULL; 744 } 745 746 if (pool->base.timing_generators[i] != NULL) { 747 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 748 pool->base.timing_generators[i] = NULL; 749 } 750 } 751 752 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 753 if (pool->base.engines[i] != NULL) 754 dce110_engine_destroy(&pool->base.engines[i]); 755 if (pool->base.hw_i2cs[i] != NULL) { 756 kfree(pool->base.hw_i2cs[i]); 757 pool->base.hw_i2cs[i] = NULL; 758 } 759 if (pool->base.sw_i2cs[i] != NULL) { 760 kfree(pool->base.sw_i2cs[i]); 761 pool->base.sw_i2cs[i] = NULL; 762 } 763 } 764 765 for (i = 0; i < pool->base.stream_enc_count; i++) { 766 if (pool->base.stream_enc[i] != NULL) 767 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 768 } 769 770 for (i = 0; i < pool->base.clk_src_count; i++) { 771 if (pool->base.clock_sources[i] != NULL) { 772 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 773 } 774 } 775 776 if (pool->base.abm != NULL) 777 dce_abm_destroy(&pool->base.abm); 778 779 if (pool->base.dmcu != NULL) 780 dce_dmcu_destroy(&pool->base.dmcu); 781 782 if (pool->base.dp_clock_source != NULL) 783 dce80_clock_source_destroy(&pool->base.dp_clock_source); 784 785 for (i = 0; i < pool->base.audio_count; i++) { 786 if (pool->base.audios[i] != NULL) { 787 dce_aud_destroy(&pool->base.audios[i]); 788 } 789 } 790 791 if (pool->base.irqs != NULL) { 792 dal_irq_service_destroy(&pool->base.irqs); 793 } 794 } 795 796 bool dce80_validate_bandwidth( 797 struct dc *dc, 798 struct dc_state *context, 799 bool fast_validate) 800 { 801 int i; 802 bool at_least_one_pipe = false; 803 804 for (i = 0; i < dc->res_pool->pipe_count; i++) { 805 if (context->res_ctx.pipe_ctx[i].stream) 806 at_least_one_pipe = true; 807 } 808 809 if (at_least_one_pipe) { 810 /* TODO implement when needed but for now hardcode max value*/ 811 context->bw_ctx.bw.dce.dispclk_khz = 681000; 812 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 813 } else { 814 context->bw_ctx.bw.dce.dispclk_khz = 0; 815 context->bw_ctx.bw.dce.yclk_khz = 0; 816 } 817 818 return true; 819 } 820 821 static bool dce80_validate_surface_sets( 822 struct dc_state *context) 823 { 824 int i; 825 826 for (i = 0; i < context->stream_count; i++) { 827 if (context->stream_status[i].plane_count == 0) 828 continue; 829 830 if (context->stream_status[i].plane_count > 1) 831 return false; 832 833 if (context->stream_status[i].plane_states[0]->format 834 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 835 return false; 836 } 837 838 return true; 839 } 840 841 enum dc_status dce80_validate_global( 842 struct dc *dc, 843 struct dc_state *context) 844 { 845 if (!dce80_validate_surface_sets(context)) 846 return DC_FAIL_SURFACE_VALIDATE; 847 848 return DC_OK; 849 } 850 851 static void dce80_destroy_resource_pool(struct resource_pool **pool) 852 { 853 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 854 855 destruct(dce110_pool); 856 kfree(dce110_pool); 857 *pool = NULL; 858 } 859 860 static const struct resource_funcs dce80_res_pool_funcs = { 861 .destroy = dce80_destroy_resource_pool, 862 .link_enc_create = dce80_link_encoder_create, 863 .validate_bandwidth = dce80_validate_bandwidth, 864 .validate_plane = dce100_validate_plane, 865 .add_stream_to_ctx = dce100_add_stream_to_ctx, 866 .validate_global = dce80_validate_global, 867 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 868 }; 869 870 static bool dce80_construct( 871 uint8_t num_virtual_links, 872 struct dc *dc, 873 struct dce110_resource_pool *pool) 874 { 875 unsigned int i; 876 struct dc_context *ctx = dc->ctx; 877 struct dc_firmware_info info; 878 struct dc_bios *bp; 879 880 ctx->dc_bios->regs = &bios_regs; 881 882 pool->base.res_cap = &res_cap; 883 pool->base.funcs = &dce80_res_pool_funcs; 884 885 886 /************************************************* 887 * Resource + asic cap harcoding * 888 *************************************************/ 889 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 890 pool->base.pipe_count = res_cap.num_timing_generator; 891 pool->base.timing_generator_count = res_cap.num_timing_generator; 892 dc->caps.max_downscale_ratio = 200; 893 dc->caps.i2c_speed_in_khz = 40; 894 dc->caps.max_cursor_size = 128; 895 dc->caps.dual_link_dvi = true; 896 897 /************************************************* 898 * Create resources * 899 *************************************************/ 900 901 bp = ctx->dc_bios; 902 903 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 904 info.external_clock_source_frequency_for_dp != 0) { 905 pool->base.dp_clock_source = 906 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 907 908 pool->base.clock_sources[0] = 909 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 910 pool->base.clock_sources[1] = 911 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 912 pool->base.clock_sources[2] = 913 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 914 pool->base.clk_src_count = 3; 915 916 } else { 917 pool->base.dp_clock_source = 918 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 919 920 pool->base.clock_sources[0] = 921 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 922 pool->base.clock_sources[1] = 923 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 924 pool->base.clk_src_count = 2; 925 } 926 927 if (pool->base.dp_clock_source == NULL) { 928 dm_error("DC: failed to create dp clock source!\n"); 929 BREAK_TO_DEBUGGER(); 930 goto res_create_fail; 931 } 932 933 for (i = 0; i < pool->base.clk_src_count; i++) { 934 if (pool->base.clock_sources[i] == NULL) { 935 dm_error("DC: failed to create clock sources!\n"); 936 BREAK_TO_DEBUGGER(); 937 goto res_create_fail; 938 } 939 } 940 941 pool->base.dmcu = dce_dmcu_create(ctx, 942 &dmcu_regs, 943 &dmcu_shift, 944 &dmcu_mask); 945 if (pool->base.dmcu == NULL) { 946 dm_error("DC: failed to create dmcu!\n"); 947 BREAK_TO_DEBUGGER(); 948 goto res_create_fail; 949 } 950 951 pool->base.abm = dce_abm_create(ctx, 952 &abm_regs, 953 &abm_shift, 954 &abm_mask); 955 if (pool->base.abm == NULL) { 956 dm_error("DC: failed to create abm!\n"); 957 BREAK_TO_DEBUGGER(); 958 goto res_create_fail; 959 } 960 961 { 962 struct irq_service_init_data init_data; 963 init_data.ctx = dc->ctx; 964 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 965 if (!pool->base.irqs) 966 goto res_create_fail; 967 } 968 969 for (i = 0; i < pool->base.pipe_count; i++) { 970 pool->base.timing_generators[i] = dce80_timing_generator_create( 971 ctx, i, &dce80_tg_offsets[i]); 972 if (pool->base.timing_generators[i] == NULL) { 973 BREAK_TO_DEBUGGER(); 974 dm_error("DC: failed to create tg!\n"); 975 goto res_create_fail; 976 } 977 978 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 979 if (pool->base.mis[i] == NULL) { 980 BREAK_TO_DEBUGGER(); 981 dm_error("DC: failed to create memory input!\n"); 982 goto res_create_fail; 983 } 984 985 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 986 if (pool->base.ipps[i] == NULL) { 987 BREAK_TO_DEBUGGER(); 988 dm_error("DC: failed to create input pixel processor!\n"); 989 goto res_create_fail; 990 } 991 992 pool->base.transforms[i] = dce80_transform_create(ctx, i); 993 if (pool->base.transforms[i] == NULL) { 994 BREAK_TO_DEBUGGER(); 995 dm_error("DC: failed to create transform!\n"); 996 goto res_create_fail; 997 } 998 999 pool->base.opps[i] = dce80_opp_create(ctx, i); 1000 if (pool->base.opps[i] == NULL) { 1001 BREAK_TO_DEBUGGER(); 1002 dm_error("DC: failed to create output pixel processor!\n"); 1003 goto res_create_fail; 1004 } 1005 } 1006 1007 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1008 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1009 if (pool->base.engines[i] == NULL) { 1010 BREAK_TO_DEBUGGER(); 1011 dm_error( 1012 "DC:failed to create aux engine!!\n"); 1013 goto res_create_fail; 1014 } 1015 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1016 if (pool->base.hw_i2cs[i] == NULL) { 1017 BREAK_TO_DEBUGGER(); 1018 dm_error( 1019 "DC:failed to create i2c engine!!\n"); 1020 goto res_create_fail; 1021 } 1022 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1023 if (pool->base.sw_i2cs[i] == NULL) { 1024 BREAK_TO_DEBUGGER(); 1025 dm_error( 1026 "DC:failed to create sw i2c!!\n"); 1027 goto res_create_fail; 1028 } 1029 } 1030 1031 dc->caps.max_planes = pool->base.pipe_count; 1032 1033 for (i = 0; i < dc->caps.max_planes; ++i) 1034 dc->caps.planes[i] = plane_cap; 1035 1036 dc->caps.disable_dp_clk_share = true; 1037 1038 if (!resource_construct(num_virtual_links, dc, &pool->base, 1039 &res_create_funcs)) 1040 goto res_create_fail; 1041 1042 /* Create hardware sequencer */ 1043 dce80_hw_sequencer_construct(dc); 1044 1045 return true; 1046 1047 res_create_fail: 1048 destruct(pool); 1049 return false; 1050 } 1051 1052 struct resource_pool *dce80_create_resource_pool( 1053 uint8_t num_virtual_links, 1054 struct dc *dc) 1055 { 1056 struct dce110_resource_pool *pool = 1057 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1058 1059 if (!pool) 1060 return NULL; 1061 1062 if (dce80_construct(num_virtual_links, dc, pool)) 1063 return &pool->base; 1064 1065 BREAK_TO_DEBUGGER(); 1066 return NULL; 1067 } 1068 1069 static bool dce81_construct( 1070 uint8_t num_virtual_links, 1071 struct dc *dc, 1072 struct dce110_resource_pool *pool) 1073 { 1074 unsigned int i; 1075 struct dc_context *ctx = dc->ctx; 1076 struct dc_firmware_info info; 1077 struct dc_bios *bp; 1078 1079 ctx->dc_bios->regs = &bios_regs; 1080 1081 pool->base.res_cap = &res_cap_81; 1082 pool->base.funcs = &dce80_res_pool_funcs; 1083 1084 1085 /************************************************* 1086 * Resource + asic cap harcoding * 1087 *************************************************/ 1088 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1089 pool->base.pipe_count = res_cap_81.num_timing_generator; 1090 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1091 dc->caps.max_downscale_ratio = 200; 1092 dc->caps.i2c_speed_in_khz = 40; 1093 dc->caps.max_cursor_size = 128; 1094 dc->caps.is_apu = true; 1095 1096 /************************************************* 1097 * Create resources * 1098 *************************************************/ 1099 1100 bp = ctx->dc_bios; 1101 1102 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1103 info.external_clock_source_frequency_for_dp != 0) { 1104 pool->base.dp_clock_source = 1105 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1106 1107 pool->base.clock_sources[0] = 1108 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1109 pool->base.clock_sources[1] = 1110 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1111 pool->base.clock_sources[2] = 1112 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1113 pool->base.clk_src_count = 3; 1114 1115 } else { 1116 pool->base.dp_clock_source = 1117 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1118 1119 pool->base.clock_sources[0] = 1120 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1121 pool->base.clock_sources[1] = 1122 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1123 pool->base.clk_src_count = 2; 1124 } 1125 1126 if (pool->base.dp_clock_source == NULL) { 1127 dm_error("DC: failed to create dp clock source!\n"); 1128 BREAK_TO_DEBUGGER(); 1129 goto res_create_fail; 1130 } 1131 1132 for (i = 0; i < pool->base.clk_src_count; i++) { 1133 if (pool->base.clock_sources[i] == NULL) { 1134 dm_error("DC: failed to create clock sources!\n"); 1135 BREAK_TO_DEBUGGER(); 1136 goto res_create_fail; 1137 } 1138 } 1139 1140 pool->base.dmcu = dce_dmcu_create(ctx, 1141 &dmcu_regs, 1142 &dmcu_shift, 1143 &dmcu_mask); 1144 if (pool->base.dmcu == NULL) { 1145 dm_error("DC: failed to create dmcu!\n"); 1146 BREAK_TO_DEBUGGER(); 1147 goto res_create_fail; 1148 } 1149 1150 pool->base.abm = dce_abm_create(ctx, 1151 &abm_regs, 1152 &abm_shift, 1153 &abm_mask); 1154 if (pool->base.abm == NULL) { 1155 dm_error("DC: failed to create abm!\n"); 1156 BREAK_TO_DEBUGGER(); 1157 goto res_create_fail; 1158 } 1159 1160 { 1161 struct irq_service_init_data init_data; 1162 init_data.ctx = dc->ctx; 1163 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1164 if (!pool->base.irqs) 1165 goto res_create_fail; 1166 } 1167 1168 for (i = 0; i < pool->base.pipe_count; i++) { 1169 pool->base.timing_generators[i] = dce80_timing_generator_create( 1170 ctx, i, &dce80_tg_offsets[i]); 1171 if (pool->base.timing_generators[i] == NULL) { 1172 BREAK_TO_DEBUGGER(); 1173 dm_error("DC: failed to create tg!\n"); 1174 goto res_create_fail; 1175 } 1176 1177 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1178 if (pool->base.mis[i] == NULL) { 1179 BREAK_TO_DEBUGGER(); 1180 dm_error("DC: failed to create memory input!\n"); 1181 goto res_create_fail; 1182 } 1183 1184 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1185 if (pool->base.ipps[i] == NULL) { 1186 BREAK_TO_DEBUGGER(); 1187 dm_error("DC: failed to create input pixel processor!\n"); 1188 goto res_create_fail; 1189 } 1190 1191 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1192 if (pool->base.transforms[i] == NULL) { 1193 BREAK_TO_DEBUGGER(); 1194 dm_error("DC: failed to create transform!\n"); 1195 goto res_create_fail; 1196 } 1197 1198 pool->base.opps[i] = dce80_opp_create(ctx, i); 1199 if (pool->base.opps[i] == NULL) { 1200 BREAK_TO_DEBUGGER(); 1201 dm_error("DC: failed to create output pixel processor!\n"); 1202 goto res_create_fail; 1203 } 1204 } 1205 1206 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1207 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1208 if (pool->base.engines[i] == NULL) { 1209 BREAK_TO_DEBUGGER(); 1210 dm_error( 1211 "DC:failed to create aux engine!!\n"); 1212 goto res_create_fail; 1213 } 1214 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1215 if (pool->base.hw_i2cs[i] == NULL) { 1216 BREAK_TO_DEBUGGER(); 1217 dm_error( 1218 "DC:failed to create i2c engine!!\n"); 1219 goto res_create_fail; 1220 } 1221 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1222 if (pool->base.sw_i2cs[i] == NULL) { 1223 BREAK_TO_DEBUGGER(); 1224 dm_error( 1225 "DC:failed to create sw i2c!!\n"); 1226 goto res_create_fail; 1227 } 1228 } 1229 1230 dc->caps.max_planes = pool->base.pipe_count; 1231 1232 for (i = 0; i < dc->caps.max_planes; ++i) 1233 dc->caps.planes[i] = plane_cap; 1234 1235 dc->caps.disable_dp_clk_share = true; 1236 1237 if (!resource_construct(num_virtual_links, dc, &pool->base, 1238 &res_create_funcs)) 1239 goto res_create_fail; 1240 1241 /* Create hardware sequencer */ 1242 dce80_hw_sequencer_construct(dc); 1243 1244 return true; 1245 1246 res_create_fail: 1247 destruct(pool); 1248 return false; 1249 } 1250 1251 struct resource_pool *dce81_create_resource_pool( 1252 uint8_t num_virtual_links, 1253 struct dc *dc) 1254 { 1255 struct dce110_resource_pool *pool = 1256 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1257 1258 if (!pool) 1259 return NULL; 1260 1261 if (dce81_construct(num_virtual_links, dc, pool)) 1262 return &pool->base; 1263 1264 BREAK_TO_DEBUGGER(); 1265 return NULL; 1266 } 1267 1268 static bool dce83_construct( 1269 uint8_t num_virtual_links, 1270 struct dc *dc, 1271 struct dce110_resource_pool *pool) 1272 { 1273 unsigned int i; 1274 struct dc_context *ctx = dc->ctx; 1275 struct dc_firmware_info info; 1276 struct dc_bios *bp; 1277 1278 ctx->dc_bios->regs = &bios_regs; 1279 1280 pool->base.res_cap = &res_cap_83; 1281 pool->base.funcs = &dce80_res_pool_funcs; 1282 1283 1284 /************************************************* 1285 * Resource + asic cap harcoding * 1286 *************************************************/ 1287 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1288 pool->base.pipe_count = res_cap_83.num_timing_generator; 1289 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1290 dc->caps.max_downscale_ratio = 200; 1291 dc->caps.i2c_speed_in_khz = 40; 1292 dc->caps.max_cursor_size = 128; 1293 dc->caps.is_apu = true; 1294 1295 /************************************************* 1296 * Create resources * 1297 *************************************************/ 1298 1299 bp = ctx->dc_bios; 1300 1301 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1302 info.external_clock_source_frequency_for_dp != 0) { 1303 pool->base.dp_clock_source = 1304 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1305 1306 pool->base.clock_sources[0] = 1307 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1308 pool->base.clock_sources[1] = 1309 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1310 pool->base.clk_src_count = 2; 1311 1312 } else { 1313 pool->base.dp_clock_source = 1314 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1315 1316 pool->base.clock_sources[0] = 1317 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1318 pool->base.clk_src_count = 1; 1319 } 1320 1321 if (pool->base.dp_clock_source == NULL) { 1322 dm_error("DC: failed to create dp clock source!\n"); 1323 BREAK_TO_DEBUGGER(); 1324 goto res_create_fail; 1325 } 1326 1327 for (i = 0; i < pool->base.clk_src_count; i++) { 1328 if (pool->base.clock_sources[i] == NULL) { 1329 dm_error("DC: failed to create clock sources!\n"); 1330 BREAK_TO_DEBUGGER(); 1331 goto res_create_fail; 1332 } 1333 } 1334 1335 pool->base.dmcu = dce_dmcu_create(ctx, 1336 &dmcu_regs, 1337 &dmcu_shift, 1338 &dmcu_mask); 1339 if (pool->base.dmcu == NULL) { 1340 dm_error("DC: failed to create dmcu!\n"); 1341 BREAK_TO_DEBUGGER(); 1342 goto res_create_fail; 1343 } 1344 1345 pool->base.abm = dce_abm_create(ctx, 1346 &abm_regs, 1347 &abm_shift, 1348 &abm_mask); 1349 if (pool->base.abm == NULL) { 1350 dm_error("DC: failed to create abm!\n"); 1351 BREAK_TO_DEBUGGER(); 1352 goto res_create_fail; 1353 } 1354 1355 { 1356 struct irq_service_init_data init_data; 1357 init_data.ctx = dc->ctx; 1358 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1359 if (!pool->base.irqs) 1360 goto res_create_fail; 1361 } 1362 1363 for (i = 0; i < pool->base.pipe_count; i++) { 1364 pool->base.timing_generators[i] = dce80_timing_generator_create( 1365 ctx, i, &dce80_tg_offsets[i]); 1366 if (pool->base.timing_generators[i] == NULL) { 1367 BREAK_TO_DEBUGGER(); 1368 dm_error("DC: failed to create tg!\n"); 1369 goto res_create_fail; 1370 } 1371 1372 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1373 if (pool->base.mis[i] == NULL) { 1374 BREAK_TO_DEBUGGER(); 1375 dm_error("DC: failed to create memory input!\n"); 1376 goto res_create_fail; 1377 } 1378 1379 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1380 if (pool->base.ipps[i] == NULL) { 1381 BREAK_TO_DEBUGGER(); 1382 dm_error("DC: failed to create input pixel processor!\n"); 1383 goto res_create_fail; 1384 } 1385 1386 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1387 if (pool->base.transforms[i] == NULL) { 1388 BREAK_TO_DEBUGGER(); 1389 dm_error("DC: failed to create transform!\n"); 1390 goto res_create_fail; 1391 } 1392 1393 pool->base.opps[i] = dce80_opp_create(ctx, i); 1394 if (pool->base.opps[i] == NULL) { 1395 BREAK_TO_DEBUGGER(); 1396 dm_error("DC: failed to create output pixel processor!\n"); 1397 goto res_create_fail; 1398 } 1399 } 1400 1401 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1402 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1403 if (pool->base.engines[i] == NULL) { 1404 BREAK_TO_DEBUGGER(); 1405 dm_error( 1406 "DC:failed to create aux engine!!\n"); 1407 goto res_create_fail; 1408 } 1409 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1410 if (pool->base.hw_i2cs[i] == NULL) { 1411 BREAK_TO_DEBUGGER(); 1412 dm_error( 1413 "DC:failed to create i2c engine!!\n"); 1414 goto res_create_fail; 1415 } 1416 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1417 if (pool->base.sw_i2cs[i] == NULL) { 1418 BREAK_TO_DEBUGGER(); 1419 dm_error( 1420 "DC:failed to create sw i2c!!\n"); 1421 goto res_create_fail; 1422 } 1423 } 1424 1425 dc->caps.max_planes = pool->base.pipe_count; 1426 1427 for (i = 0; i < dc->caps.max_planes; ++i) 1428 dc->caps.planes[i] = plane_cap; 1429 1430 dc->caps.disable_dp_clk_share = true; 1431 1432 if (!resource_construct(num_virtual_links, dc, &pool->base, 1433 &res_create_funcs)) 1434 goto res_create_fail; 1435 1436 /* Create hardware sequencer */ 1437 dce80_hw_sequencer_construct(dc); 1438 1439 return true; 1440 1441 res_create_fail: 1442 destruct(pool); 1443 return false; 1444 } 1445 1446 struct resource_pool *dce83_create_resource_pool( 1447 uint8_t num_virtual_links, 1448 struct dc *dc) 1449 { 1450 struct dce110_resource_pool *pool = 1451 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1452 1453 if (!pool) 1454 return NULL; 1455 1456 if (dce83_construct(num_virtual_links, dc, pool)) 1457 return &pool->base; 1458 1459 BREAK_TO_DEBUGGER(); 1460 return NULL; 1461 } 1462