1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_8_0_d.h" 29 #include "dce/dce_8_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "include/irq_service_interface.h" 38 #include "irq/dce80/irq_service_dce80.h" 39 #include "dce110/dce110_timing_generator.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce80/dce80_timing_generator.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce/dce_link_encoder.h" 44 #include "dce/dce_stream_encoder.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_transform.h" 47 #include "dce/dce_opp.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 #include "dce/dce_i2c.h" 60 /* TODO remove this include */ 61 62 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 63 #include "gmc/gmc_7_1_d.h" 64 #include "gmc/gmc_7_1_sh_mask.h" 65 #endif 66 67 #ifndef mmDP_DPHY_INTERNAL_CTRL 68 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 94 #endif 95 96 97 #ifndef mmHPD_DC_HPD_CONTROL 98 #define mmHPD_DC_HPD_CONTROL 0x189A 99 #define mmHPD0_DC_HPD_CONTROL 0x189A 100 #define mmHPD1_DC_HPD_CONTROL 0x18A2 101 #define mmHPD2_DC_HPD_CONTROL 0x18AA 102 #define mmHPD3_DC_HPD_CONTROL 0x18B2 103 #define mmHPD4_DC_HPD_CONTROL 0x18BA 104 #define mmHPD5_DC_HPD_CONTROL 0x18C2 105 #endif 106 107 #define DCE11_DIG_FE_CNTL 0x4a00 108 #define DCE11_DIG_BE_CNTL 0x4a47 109 #define DCE11_DP_SEC 0x4ac3 110 111 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 115 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 116 - mmDPG_WATERMARK_MASK_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 122 - mmDPG_WATERMARK_MASK_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 128 - mmDPG_WATERMARK_MASK_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 134 - mmDPG_WATERMARK_MASK_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 139 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 140 - mmDPG_WATERMARK_MASK_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 146 - mmDPG_WATERMARK_MASK_CONTROL), 147 } 148 }; 149 150 /* set register offset */ 151 #define SR(reg_name)\ 152 .reg_name = mm ## reg_name 153 154 /* set register offset with instance */ 155 #define SRI(reg_name, block, id)\ 156 .reg_name = mm ## block ## id ## _ ## reg_name 157 158 #define ipp_regs(id)\ 159 [id] = {\ 160 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 161 } 162 163 static const struct dce_ipp_registers ipp_regs[] = { 164 ipp_regs(0), 165 ipp_regs(1), 166 ipp_regs(2), 167 ipp_regs(3), 168 ipp_regs(4), 169 ipp_regs(5) 170 }; 171 172 static const struct dce_ipp_shift ipp_shift = { 173 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 174 }; 175 176 static const struct dce_ipp_mask ipp_mask = { 177 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 178 }; 179 180 #define transform_regs(id)\ 181 [id] = {\ 182 XFM_COMMON_REG_LIST_DCE80(id)\ 183 } 184 185 static const struct dce_transform_registers xfm_regs[] = { 186 transform_regs(0), 187 transform_regs(1), 188 transform_regs(2), 189 transform_regs(3), 190 transform_regs(4), 191 transform_regs(5) 192 }; 193 194 static const struct dce_transform_shift xfm_shift = { 195 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 196 }; 197 198 static const struct dce_transform_mask xfm_mask = { 199 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 200 }; 201 202 #define aux_regs(id)\ 203 [id] = {\ 204 AUX_REG_LIST(id)\ 205 } 206 207 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 208 aux_regs(0), 209 aux_regs(1), 210 aux_regs(2), 211 aux_regs(3), 212 aux_regs(4), 213 aux_regs(5) 214 }; 215 216 #define hpd_regs(id)\ 217 [id] = {\ 218 HPD_REG_LIST(id)\ 219 } 220 221 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 222 hpd_regs(0), 223 hpd_regs(1), 224 hpd_regs(2), 225 hpd_regs(3), 226 hpd_regs(4), 227 hpd_regs(5) 228 }; 229 230 #define link_regs(id)\ 231 [id] = {\ 232 LE_DCE80_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_registers link_enc_regs[] = { 236 link_regs(0), 237 link_regs(1), 238 link_regs(2), 239 link_regs(3), 240 link_regs(4), 241 link_regs(5), 242 link_regs(6), 243 }; 244 245 #define stream_enc_regs(id)\ 246 [id] = {\ 247 SE_COMMON_REG_LIST_DCE_BASE(id),\ 248 .AFMT_CNTL = 0,\ 249 } 250 251 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 252 stream_enc_regs(0), 253 stream_enc_regs(1), 254 stream_enc_regs(2), 255 stream_enc_regs(3), 256 stream_enc_regs(4), 257 stream_enc_regs(5), 258 stream_enc_regs(6) 259 }; 260 261 static const struct dce_stream_encoder_shift se_shift = { 262 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 263 }; 264 265 static const struct dce_stream_encoder_mask se_mask = { 266 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 267 }; 268 269 #define opp_regs(id)\ 270 [id] = {\ 271 OPP_DCE_80_REG_LIST(id),\ 272 } 273 274 static const struct dce_opp_registers opp_regs[] = { 275 opp_regs(0), 276 opp_regs(1), 277 opp_regs(2), 278 opp_regs(3), 279 opp_regs(4), 280 opp_regs(5) 281 }; 282 283 static const struct dce_opp_shift opp_shift = { 284 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 285 }; 286 287 static const struct dce_opp_mask opp_mask = { 288 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 289 }; 290 291 static const struct dce110_aux_registers_shift aux_shift = { 292 DCE10_AUX_MASK_SH_LIST(__SHIFT) 293 }; 294 295 static const struct dce110_aux_registers_mask aux_mask = { 296 DCE10_AUX_MASK_SH_LIST(_MASK) 297 }; 298 299 #define aux_engine_regs(id)\ 300 [id] = {\ 301 AUX_COMMON_REG_LIST(id), \ 302 .AUX_RESET_MASK = 0 \ 303 } 304 305 static const struct dce110_aux_registers aux_engine_regs[] = { 306 aux_engine_regs(0), 307 aux_engine_regs(1), 308 aux_engine_regs(2), 309 aux_engine_regs(3), 310 aux_engine_regs(4), 311 aux_engine_regs(5) 312 }; 313 314 #define audio_regs(id)\ 315 [id] = {\ 316 AUD_COMMON_REG_LIST(id)\ 317 } 318 319 static const struct dce_audio_registers audio_regs[] = { 320 audio_regs(0), 321 audio_regs(1), 322 audio_regs(2), 323 audio_regs(3), 324 audio_regs(4), 325 audio_regs(5), 326 audio_regs(6), 327 }; 328 329 static const struct dce_audio_shift audio_shift = { 330 AUD_COMMON_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dce_audio_mask audio_mask = { 334 AUD_COMMON_MASK_SH_LIST(_MASK) 335 }; 336 337 #define clk_src_regs(id)\ 338 [id] = {\ 339 CS_COMMON_REG_LIST_DCE_80(id),\ 340 } 341 342 343 static const struct dce110_clk_src_regs clk_src_regs[] = { 344 clk_src_regs(0), 345 clk_src_regs(1), 346 clk_src_regs(2) 347 }; 348 349 static const struct dce110_clk_src_shift cs_shift = { 350 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 351 }; 352 353 static const struct dce110_clk_src_mask cs_mask = { 354 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 355 }; 356 357 static const struct bios_registers bios_regs = { 358 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 359 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 360 }; 361 362 static const struct resource_caps res_cap = { 363 .num_timing_generator = 6, 364 .num_audio = 6, 365 .num_stream_encoder = 6, 366 .num_pll = 3, 367 .num_ddc = 6, 368 }; 369 370 static const struct resource_caps res_cap_81 = { 371 .num_timing_generator = 4, 372 .num_audio = 7, 373 .num_stream_encoder = 7, 374 .num_pll = 3, 375 .num_ddc = 6, 376 }; 377 378 static const struct resource_caps res_cap_83 = { 379 .num_timing_generator = 2, 380 .num_audio = 6, 381 .num_stream_encoder = 6, 382 .num_pll = 2, 383 .num_ddc = 2, 384 }; 385 386 static const struct dc_plane_cap plane_cap = { 387 .type = DC_PLANE_TYPE_DCE_RGB, 388 389 .pixel_format_support = { 390 .argb8888 = true, 391 .nv12 = false, 392 .fp16 = false 393 }, 394 395 .max_upscale_factor = { 396 .argb8888 = 16000, 397 .nv12 = 1, 398 .fp16 = 1 399 }, 400 401 .max_downscale_factor = { 402 .argb8888 = 250, 403 .nv12 = 1, 404 .fp16 = 1 405 } 406 }; 407 408 static const struct dce_dmcu_registers dmcu_regs = { 409 DMCU_DCE80_REG_LIST() 410 }; 411 412 static const struct dce_dmcu_shift dmcu_shift = { 413 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 414 }; 415 416 static const struct dce_dmcu_mask dmcu_mask = { 417 DMCU_MASK_SH_LIST_DCE80(_MASK) 418 }; 419 static const struct dce_abm_registers abm_regs = { 420 ABM_DCE110_COMMON_REG_LIST() 421 }; 422 423 static const struct dce_abm_shift abm_shift = { 424 ABM_MASK_SH_LIST_DCE110(__SHIFT) 425 }; 426 427 static const struct dce_abm_mask abm_mask = { 428 ABM_MASK_SH_LIST_DCE110(_MASK) 429 }; 430 431 #define CTX ctx 432 #define REG(reg) mm ## reg 433 434 #ifndef mmCC_DC_HDMI_STRAPS 435 #define mmCC_DC_HDMI_STRAPS 0x1918 436 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 437 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 438 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 439 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 440 #endif 441 442 static void read_dce_straps( 443 struct dc_context *ctx, 444 struct resource_straps *straps) 445 { 446 REG_GET_2(CC_DC_HDMI_STRAPS, 447 HDMI_DISABLE, &straps->hdmi_disable, 448 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 449 450 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 451 } 452 453 static struct audio *create_audio( 454 struct dc_context *ctx, unsigned int inst) 455 { 456 return dce_audio_create(ctx, inst, 457 &audio_regs[inst], &audio_shift, &audio_mask); 458 } 459 460 static struct timing_generator *dce80_timing_generator_create( 461 struct dc_context *ctx, 462 uint32_t instance, 463 const struct dce110_timing_generator_offsets *offsets) 464 { 465 struct dce110_timing_generator *tg110 = 466 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 467 468 if (!tg110) 469 return NULL; 470 471 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 472 return &tg110->base; 473 } 474 475 static struct output_pixel_processor *dce80_opp_create( 476 struct dc_context *ctx, 477 uint32_t inst) 478 { 479 struct dce110_opp *opp = 480 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 481 482 if (!opp) 483 return NULL; 484 485 dce110_opp_construct(opp, 486 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 487 return &opp->base; 488 } 489 490 struct dce_aux *dce80_aux_engine_create( 491 struct dc_context *ctx, 492 uint32_t inst) 493 { 494 struct aux_engine_dce110 *aux_engine = 495 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 496 497 if (!aux_engine) 498 return NULL; 499 500 dce110_aux_engine_construct(aux_engine, ctx, inst, 501 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 502 &aux_engine_regs[inst], 503 &aux_mask, 504 &aux_shift, 505 ctx->dc->caps.extended_aux_timeout_support); 506 507 return &aux_engine->base; 508 } 509 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 510 511 static const struct dce_i2c_registers i2c_hw_regs[] = { 512 i2c_inst_regs(1), 513 i2c_inst_regs(2), 514 i2c_inst_regs(3), 515 i2c_inst_regs(4), 516 i2c_inst_regs(5), 517 i2c_inst_regs(6), 518 }; 519 520 static const struct dce_i2c_shift i2c_shifts = { 521 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 522 }; 523 524 static const struct dce_i2c_mask i2c_masks = { 525 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 526 }; 527 528 struct dce_i2c_hw *dce80_i2c_hw_create( 529 struct dc_context *ctx, 530 uint32_t inst) 531 { 532 struct dce_i2c_hw *dce_i2c_hw = 533 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 534 535 if (!dce_i2c_hw) 536 return NULL; 537 538 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 539 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 540 541 return dce_i2c_hw; 542 } 543 544 struct dce_i2c_sw *dce80_i2c_sw_create( 545 struct dc_context *ctx) 546 { 547 struct dce_i2c_sw *dce_i2c_sw = 548 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 549 550 if (!dce_i2c_sw) 551 return NULL; 552 553 dce_i2c_sw_construct(dce_i2c_sw, ctx); 554 555 return dce_i2c_sw; 556 } 557 static struct stream_encoder *dce80_stream_encoder_create( 558 enum engine_id eng_id, 559 struct dc_context *ctx) 560 { 561 struct dce110_stream_encoder *enc110 = 562 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 563 564 if (!enc110) 565 return NULL; 566 567 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 568 &stream_enc_regs[eng_id], 569 &se_shift, &se_mask); 570 return &enc110->base; 571 } 572 573 #define SRII(reg_name, block, id)\ 574 .reg_name[id] = mm ## block ## id ## _ ## reg_name 575 576 static const struct dce_hwseq_registers hwseq_reg = { 577 HWSEQ_DCE8_REG_LIST() 578 }; 579 580 static const struct dce_hwseq_shift hwseq_shift = { 581 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 582 }; 583 584 static const struct dce_hwseq_mask hwseq_mask = { 585 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 586 }; 587 588 static struct dce_hwseq *dce80_hwseq_create( 589 struct dc_context *ctx) 590 { 591 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 592 593 if (hws) { 594 hws->ctx = ctx; 595 hws->regs = &hwseq_reg; 596 hws->shifts = &hwseq_shift; 597 hws->masks = &hwseq_mask; 598 } 599 return hws; 600 } 601 602 static const struct resource_create_funcs res_create_funcs = { 603 .read_dce_straps = read_dce_straps, 604 .create_audio = create_audio, 605 .create_stream_encoder = dce80_stream_encoder_create, 606 .create_hwseq = dce80_hwseq_create, 607 }; 608 609 #define mi_inst_regs(id) { \ 610 MI_DCE8_REG_LIST(id), \ 611 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 612 } 613 static const struct dce_mem_input_registers mi_regs[] = { 614 mi_inst_regs(0), 615 mi_inst_regs(1), 616 mi_inst_regs(2), 617 mi_inst_regs(3), 618 mi_inst_regs(4), 619 mi_inst_regs(5), 620 }; 621 622 static const struct dce_mem_input_shift mi_shifts = { 623 MI_DCE8_MASK_SH_LIST(__SHIFT), 624 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 625 }; 626 627 static const struct dce_mem_input_mask mi_masks = { 628 MI_DCE8_MASK_SH_LIST(_MASK), 629 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 630 }; 631 632 static struct mem_input *dce80_mem_input_create( 633 struct dc_context *ctx, 634 uint32_t inst) 635 { 636 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 637 GFP_KERNEL); 638 639 if (!dce_mi) { 640 BREAK_TO_DEBUGGER(); 641 return NULL; 642 } 643 644 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 645 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 646 return &dce_mi->base; 647 } 648 649 static void dce80_transform_destroy(struct transform **xfm) 650 { 651 kfree(TO_DCE_TRANSFORM(*xfm)); 652 *xfm = NULL; 653 } 654 655 static struct transform *dce80_transform_create( 656 struct dc_context *ctx, 657 uint32_t inst) 658 { 659 struct dce_transform *transform = 660 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 661 662 if (!transform) 663 return NULL; 664 665 dce_transform_construct(transform, ctx, inst, 666 &xfm_regs[inst], &xfm_shift, &xfm_mask); 667 transform->prescaler_on = false; 668 return &transform->base; 669 } 670 671 static const struct encoder_feature_support link_enc_feature = { 672 .max_hdmi_deep_color = COLOR_DEPTH_121212, 673 .max_hdmi_pixel_clock = 297000, 674 .flags.bits.IS_HBR2_CAPABLE = true, 675 .flags.bits.IS_TPS3_CAPABLE = true 676 }; 677 678 struct link_encoder *dce80_link_encoder_create( 679 const struct encoder_init_data *enc_init_data) 680 { 681 struct dce110_link_encoder *enc110 = 682 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 683 684 if (!enc110) 685 return NULL; 686 687 dce110_link_encoder_construct(enc110, 688 enc_init_data, 689 &link_enc_feature, 690 &link_enc_regs[enc_init_data->transmitter], 691 &link_enc_aux_regs[enc_init_data->channel - 1], 692 &link_enc_hpd_regs[enc_init_data->hpd_source]); 693 return &enc110->base; 694 } 695 696 struct clock_source *dce80_clock_source_create( 697 struct dc_context *ctx, 698 struct dc_bios *bios, 699 enum clock_source_id id, 700 const struct dce110_clk_src_regs *regs, 701 bool dp_clk_src) 702 { 703 struct dce110_clk_src *clk_src = 704 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 705 706 if (!clk_src) 707 return NULL; 708 709 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 710 regs, &cs_shift, &cs_mask)) { 711 clk_src->base.dp_clk_src = dp_clk_src; 712 return &clk_src->base; 713 } 714 715 kfree(clk_src); 716 BREAK_TO_DEBUGGER(); 717 return NULL; 718 } 719 720 void dce80_clock_source_destroy(struct clock_source **clk_src) 721 { 722 kfree(TO_DCE110_CLK_SRC(*clk_src)); 723 *clk_src = NULL; 724 } 725 726 static struct input_pixel_processor *dce80_ipp_create( 727 struct dc_context *ctx, uint32_t inst) 728 { 729 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 730 731 if (!ipp) { 732 BREAK_TO_DEBUGGER(); 733 return NULL; 734 } 735 736 dce_ipp_construct(ipp, ctx, inst, 737 &ipp_regs[inst], &ipp_shift, &ipp_mask); 738 return &ipp->base; 739 } 740 741 static void destruct(struct dce110_resource_pool *pool) 742 { 743 unsigned int i; 744 745 for (i = 0; i < pool->base.pipe_count; i++) { 746 if (pool->base.opps[i] != NULL) 747 dce110_opp_destroy(&pool->base.opps[i]); 748 749 if (pool->base.transforms[i] != NULL) 750 dce80_transform_destroy(&pool->base.transforms[i]); 751 752 if (pool->base.ipps[i] != NULL) 753 dce_ipp_destroy(&pool->base.ipps[i]); 754 755 if (pool->base.mis[i] != NULL) { 756 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 757 pool->base.mis[i] = NULL; 758 } 759 760 if (pool->base.timing_generators[i] != NULL) { 761 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 762 pool->base.timing_generators[i] = NULL; 763 } 764 } 765 766 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 767 if (pool->base.engines[i] != NULL) 768 dce110_engine_destroy(&pool->base.engines[i]); 769 if (pool->base.hw_i2cs[i] != NULL) { 770 kfree(pool->base.hw_i2cs[i]); 771 pool->base.hw_i2cs[i] = NULL; 772 } 773 if (pool->base.sw_i2cs[i] != NULL) { 774 kfree(pool->base.sw_i2cs[i]); 775 pool->base.sw_i2cs[i] = NULL; 776 } 777 } 778 779 for (i = 0; i < pool->base.stream_enc_count; i++) { 780 if (pool->base.stream_enc[i] != NULL) 781 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 782 } 783 784 for (i = 0; i < pool->base.clk_src_count; i++) { 785 if (pool->base.clock_sources[i] != NULL) { 786 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 787 } 788 } 789 790 if (pool->base.abm != NULL) 791 dce_abm_destroy(&pool->base.abm); 792 793 if (pool->base.dmcu != NULL) 794 dce_dmcu_destroy(&pool->base.dmcu); 795 796 if (pool->base.dp_clock_source != NULL) 797 dce80_clock_source_destroy(&pool->base.dp_clock_source); 798 799 for (i = 0; i < pool->base.audio_count; i++) { 800 if (pool->base.audios[i] != NULL) { 801 dce_aud_destroy(&pool->base.audios[i]); 802 } 803 } 804 805 if (pool->base.irqs != NULL) { 806 dal_irq_service_destroy(&pool->base.irqs); 807 } 808 } 809 810 bool dce80_validate_bandwidth( 811 struct dc *dc, 812 struct dc_state *context, 813 bool fast_validate) 814 { 815 int i; 816 bool at_least_one_pipe = false; 817 818 for (i = 0; i < dc->res_pool->pipe_count; i++) { 819 if (context->res_ctx.pipe_ctx[i].stream) 820 at_least_one_pipe = true; 821 } 822 823 if (at_least_one_pipe) { 824 /* TODO implement when needed but for now hardcode max value*/ 825 context->bw_ctx.bw.dce.dispclk_khz = 681000; 826 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 827 } else { 828 context->bw_ctx.bw.dce.dispclk_khz = 0; 829 context->bw_ctx.bw.dce.yclk_khz = 0; 830 } 831 832 return true; 833 } 834 835 static bool dce80_validate_surface_sets( 836 struct dc_state *context) 837 { 838 int i; 839 840 for (i = 0; i < context->stream_count; i++) { 841 if (context->stream_status[i].plane_count == 0) 842 continue; 843 844 if (context->stream_status[i].plane_count > 1) 845 return false; 846 847 if (context->stream_status[i].plane_states[0]->format 848 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 849 return false; 850 } 851 852 return true; 853 } 854 855 enum dc_status dce80_validate_global( 856 struct dc *dc, 857 struct dc_state *context) 858 { 859 if (!dce80_validate_surface_sets(context)) 860 return DC_FAIL_SURFACE_VALIDATE; 861 862 return DC_OK; 863 } 864 865 static void dce80_destroy_resource_pool(struct resource_pool **pool) 866 { 867 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 868 869 destruct(dce110_pool); 870 kfree(dce110_pool); 871 *pool = NULL; 872 } 873 874 static const struct resource_funcs dce80_res_pool_funcs = { 875 .destroy = dce80_destroy_resource_pool, 876 .link_enc_create = dce80_link_encoder_create, 877 .validate_bandwidth = dce80_validate_bandwidth, 878 .validate_plane = dce100_validate_plane, 879 .add_stream_to_ctx = dce100_add_stream_to_ctx, 880 .validate_global = dce80_validate_global, 881 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 882 }; 883 884 static bool dce80_construct( 885 uint8_t num_virtual_links, 886 struct dc *dc, 887 struct dce110_resource_pool *pool) 888 { 889 unsigned int i; 890 struct dc_context *ctx = dc->ctx; 891 struct dc_bios *bp; 892 893 ctx->dc_bios->regs = &bios_regs; 894 895 pool->base.res_cap = &res_cap; 896 pool->base.funcs = &dce80_res_pool_funcs; 897 898 899 /************************************************* 900 * Resource + asic cap harcoding * 901 *************************************************/ 902 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 903 pool->base.pipe_count = res_cap.num_timing_generator; 904 pool->base.timing_generator_count = res_cap.num_timing_generator; 905 dc->caps.max_downscale_ratio = 200; 906 dc->caps.i2c_speed_in_khz = 40; 907 dc->caps.max_cursor_size = 128; 908 dc->caps.dual_link_dvi = true; 909 dc->caps.extended_aux_timeout_support = false; 910 911 /************************************************* 912 * Create resources * 913 *************************************************/ 914 915 bp = ctx->dc_bios; 916 917 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 918 pool->base.dp_clock_source = 919 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 920 921 pool->base.clock_sources[0] = 922 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 923 pool->base.clock_sources[1] = 924 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 925 pool->base.clock_sources[2] = 926 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 927 pool->base.clk_src_count = 3; 928 929 } else { 930 pool->base.dp_clock_source = 931 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 932 933 pool->base.clock_sources[0] = 934 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 935 pool->base.clock_sources[1] = 936 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 937 pool->base.clk_src_count = 2; 938 } 939 940 if (pool->base.dp_clock_source == NULL) { 941 dm_error("DC: failed to create dp clock source!\n"); 942 BREAK_TO_DEBUGGER(); 943 goto res_create_fail; 944 } 945 946 for (i = 0; i < pool->base.clk_src_count; i++) { 947 if (pool->base.clock_sources[i] == NULL) { 948 dm_error("DC: failed to create clock sources!\n"); 949 BREAK_TO_DEBUGGER(); 950 goto res_create_fail; 951 } 952 } 953 954 pool->base.dmcu = dce_dmcu_create(ctx, 955 &dmcu_regs, 956 &dmcu_shift, 957 &dmcu_mask); 958 if (pool->base.dmcu == NULL) { 959 dm_error("DC: failed to create dmcu!\n"); 960 BREAK_TO_DEBUGGER(); 961 goto res_create_fail; 962 } 963 964 pool->base.abm = dce_abm_create(ctx, 965 &abm_regs, 966 &abm_shift, 967 &abm_mask); 968 if (pool->base.abm == NULL) { 969 dm_error("DC: failed to create abm!\n"); 970 BREAK_TO_DEBUGGER(); 971 goto res_create_fail; 972 } 973 974 { 975 struct irq_service_init_data init_data; 976 init_data.ctx = dc->ctx; 977 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 978 if (!pool->base.irqs) 979 goto res_create_fail; 980 } 981 982 for (i = 0; i < pool->base.pipe_count; i++) { 983 pool->base.timing_generators[i] = dce80_timing_generator_create( 984 ctx, i, &dce80_tg_offsets[i]); 985 if (pool->base.timing_generators[i] == NULL) { 986 BREAK_TO_DEBUGGER(); 987 dm_error("DC: failed to create tg!\n"); 988 goto res_create_fail; 989 } 990 991 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 992 if (pool->base.mis[i] == NULL) { 993 BREAK_TO_DEBUGGER(); 994 dm_error("DC: failed to create memory input!\n"); 995 goto res_create_fail; 996 } 997 998 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 999 if (pool->base.ipps[i] == NULL) { 1000 BREAK_TO_DEBUGGER(); 1001 dm_error("DC: failed to create input pixel processor!\n"); 1002 goto res_create_fail; 1003 } 1004 1005 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1006 if (pool->base.transforms[i] == NULL) { 1007 BREAK_TO_DEBUGGER(); 1008 dm_error("DC: failed to create transform!\n"); 1009 goto res_create_fail; 1010 } 1011 1012 pool->base.opps[i] = dce80_opp_create(ctx, i); 1013 if (pool->base.opps[i] == NULL) { 1014 BREAK_TO_DEBUGGER(); 1015 dm_error("DC: failed to create output pixel processor!\n"); 1016 goto res_create_fail; 1017 } 1018 } 1019 1020 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1021 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1022 if (pool->base.engines[i] == NULL) { 1023 BREAK_TO_DEBUGGER(); 1024 dm_error( 1025 "DC:failed to create aux engine!!\n"); 1026 goto res_create_fail; 1027 } 1028 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1029 if (pool->base.hw_i2cs[i] == NULL) { 1030 BREAK_TO_DEBUGGER(); 1031 dm_error( 1032 "DC:failed to create i2c engine!!\n"); 1033 goto res_create_fail; 1034 } 1035 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1036 if (pool->base.sw_i2cs[i] == NULL) { 1037 BREAK_TO_DEBUGGER(); 1038 dm_error( 1039 "DC:failed to create sw i2c!!\n"); 1040 goto res_create_fail; 1041 } 1042 } 1043 1044 dc->caps.max_planes = pool->base.pipe_count; 1045 1046 for (i = 0; i < dc->caps.max_planes; ++i) 1047 dc->caps.planes[i] = plane_cap; 1048 1049 dc->caps.disable_dp_clk_share = true; 1050 1051 if (!resource_construct(num_virtual_links, dc, &pool->base, 1052 &res_create_funcs)) 1053 goto res_create_fail; 1054 1055 /* Create hardware sequencer */ 1056 dce80_hw_sequencer_construct(dc); 1057 1058 return true; 1059 1060 res_create_fail: 1061 destruct(pool); 1062 return false; 1063 } 1064 1065 struct resource_pool *dce80_create_resource_pool( 1066 uint8_t num_virtual_links, 1067 struct dc *dc) 1068 { 1069 struct dce110_resource_pool *pool = 1070 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1071 1072 if (!pool) 1073 return NULL; 1074 1075 if (dce80_construct(num_virtual_links, dc, pool)) 1076 return &pool->base; 1077 1078 BREAK_TO_DEBUGGER(); 1079 return NULL; 1080 } 1081 1082 static bool dce81_construct( 1083 uint8_t num_virtual_links, 1084 struct dc *dc, 1085 struct dce110_resource_pool *pool) 1086 { 1087 unsigned int i; 1088 struct dc_context *ctx = dc->ctx; 1089 struct dc_bios *bp; 1090 1091 ctx->dc_bios->regs = &bios_regs; 1092 1093 pool->base.res_cap = &res_cap_81; 1094 pool->base.funcs = &dce80_res_pool_funcs; 1095 1096 1097 /************************************************* 1098 * Resource + asic cap harcoding * 1099 *************************************************/ 1100 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1101 pool->base.pipe_count = res_cap_81.num_timing_generator; 1102 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1103 dc->caps.max_downscale_ratio = 200; 1104 dc->caps.i2c_speed_in_khz = 40; 1105 dc->caps.max_cursor_size = 128; 1106 dc->caps.is_apu = true; 1107 1108 /************************************************* 1109 * Create resources * 1110 *************************************************/ 1111 1112 bp = ctx->dc_bios; 1113 1114 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1115 pool->base.dp_clock_source = 1116 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1117 1118 pool->base.clock_sources[0] = 1119 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1120 pool->base.clock_sources[1] = 1121 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1122 pool->base.clock_sources[2] = 1123 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1124 pool->base.clk_src_count = 3; 1125 1126 } else { 1127 pool->base.dp_clock_source = 1128 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1129 1130 pool->base.clock_sources[0] = 1131 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1132 pool->base.clock_sources[1] = 1133 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1134 pool->base.clk_src_count = 2; 1135 } 1136 1137 if (pool->base.dp_clock_source == NULL) { 1138 dm_error("DC: failed to create dp clock source!\n"); 1139 BREAK_TO_DEBUGGER(); 1140 goto res_create_fail; 1141 } 1142 1143 for (i = 0; i < pool->base.clk_src_count; i++) { 1144 if (pool->base.clock_sources[i] == NULL) { 1145 dm_error("DC: failed to create clock sources!\n"); 1146 BREAK_TO_DEBUGGER(); 1147 goto res_create_fail; 1148 } 1149 } 1150 1151 pool->base.dmcu = dce_dmcu_create(ctx, 1152 &dmcu_regs, 1153 &dmcu_shift, 1154 &dmcu_mask); 1155 if (pool->base.dmcu == NULL) { 1156 dm_error("DC: failed to create dmcu!\n"); 1157 BREAK_TO_DEBUGGER(); 1158 goto res_create_fail; 1159 } 1160 1161 pool->base.abm = dce_abm_create(ctx, 1162 &abm_regs, 1163 &abm_shift, 1164 &abm_mask); 1165 if (pool->base.abm == NULL) { 1166 dm_error("DC: failed to create abm!\n"); 1167 BREAK_TO_DEBUGGER(); 1168 goto res_create_fail; 1169 } 1170 1171 { 1172 struct irq_service_init_data init_data; 1173 init_data.ctx = dc->ctx; 1174 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1175 if (!pool->base.irqs) 1176 goto res_create_fail; 1177 } 1178 1179 for (i = 0; i < pool->base.pipe_count; i++) { 1180 pool->base.timing_generators[i] = dce80_timing_generator_create( 1181 ctx, i, &dce80_tg_offsets[i]); 1182 if (pool->base.timing_generators[i] == NULL) { 1183 BREAK_TO_DEBUGGER(); 1184 dm_error("DC: failed to create tg!\n"); 1185 goto res_create_fail; 1186 } 1187 1188 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1189 if (pool->base.mis[i] == NULL) { 1190 BREAK_TO_DEBUGGER(); 1191 dm_error("DC: failed to create memory input!\n"); 1192 goto res_create_fail; 1193 } 1194 1195 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1196 if (pool->base.ipps[i] == NULL) { 1197 BREAK_TO_DEBUGGER(); 1198 dm_error("DC: failed to create input pixel processor!\n"); 1199 goto res_create_fail; 1200 } 1201 1202 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1203 if (pool->base.transforms[i] == NULL) { 1204 BREAK_TO_DEBUGGER(); 1205 dm_error("DC: failed to create transform!\n"); 1206 goto res_create_fail; 1207 } 1208 1209 pool->base.opps[i] = dce80_opp_create(ctx, i); 1210 if (pool->base.opps[i] == NULL) { 1211 BREAK_TO_DEBUGGER(); 1212 dm_error("DC: failed to create output pixel processor!\n"); 1213 goto res_create_fail; 1214 } 1215 } 1216 1217 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1218 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1219 if (pool->base.engines[i] == NULL) { 1220 BREAK_TO_DEBUGGER(); 1221 dm_error( 1222 "DC:failed to create aux engine!!\n"); 1223 goto res_create_fail; 1224 } 1225 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1226 if (pool->base.hw_i2cs[i] == NULL) { 1227 BREAK_TO_DEBUGGER(); 1228 dm_error( 1229 "DC:failed to create i2c engine!!\n"); 1230 goto res_create_fail; 1231 } 1232 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1233 if (pool->base.sw_i2cs[i] == NULL) { 1234 BREAK_TO_DEBUGGER(); 1235 dm_error( 1236 "DC:failed to create sw i2c!!\n"); 1237 goto res_create_fail; 1238 } 1239 } 1240 1241 dc->caps.max_planes = pool->base.pipe_count; 1242 1243 for (i = 0; i < dc->caps.max_planes; ++i) 1244 dc->caps.planes[i] = plane_cap; 1245 1246 dc->caps.disable_dp_clk_share = true; 1247 1248 if (!resource_construct(num_virtual_links, dc, &pool->base, 1249 &res_create_funcs)) 1250 goto res_create_fail; 1251 1252 /* Create hardware sequencer */ 1253 dce80_hw_sequencer_construct(dc); 1254 1255 return true; 1256 1257 res_create_fail: 1258 destruct(pool); 1259 return false; 1260 } 1261 1262 struct resource_pool *dce81_create_resource_pool( 1263 uint8_t num_virtual_links, 1264 struct dc *dc) 1265 { 1266 struct dce110_resource_pool *pool = 1267 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1268 1269 if (!pool) 1270 return NULL; 1271 1272 if (dce81_construct(num_virtual_links, dc, pool)) 1273 return &pool->base; 1274 1275 BREAK_TO_DEBUGGER(); 1276 return NULL; 1277 } 1278 1279 static bool dce83_construct( 1280 uint8_t num_virtual_links, 1281 struct dc *dc, 1282 struct dce110_resource_pool *pool) 1283 { 1284 unsigned int i; 1285 struct dc_context *ctx = dc->ctx; 1286 struct dc_bios *bp; 1287 1288 ctx->dc_bios->regs = &bios_regs; 1289 1290 pool->base.res_cap = &res_cap_83; 1291 pool->base.funcs = &dce80_res_pool_funcs; 1292 1293 1294 /************************************************* 1295 * Resource + asic cap harcoding * 1296 *************************************************/ 1297 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1298 pool->base.pipe_count = res_cap_83.num_timing_generator; 1299 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1300 dc->caps.max_downscale_ratio = 200; 1301 dc->caps.i2c_speed_in_khz = 40; 1302 dc->caps.max_cursor_size = 128; 1303 dc->caps.is_apu = true; 1304 1305 /************************************************* 1306 * Create resources * 1307 *************************************************/ 1308 1309 bp = ctx->dc_bios; 1310 1311 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1312 pool->base.dp_clock_source = 1313 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1314 1315 pool->base.clock_sources[0] = 1316 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1317 pool->base.clock_sources[1] = 1318 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1319 pool->base.clk_src_count = 2; 1320 1321 } else { 1322 pool->base.dp_clock_source = 1323 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1324 1325 pool->base.clock_sources[0] = 1326 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1327 pool->base.clk_src_count = 1; 1328 } 1329 1330 if (pool->base.dp_clock_source == NULL) { 1331 dm_error("DC: failed to create dp clock source!\n"); 1332 BREAK_TO_DEBUGGER(); 1333 goto res_create_fail; 1334 } 1335 1336 for (i = 0; i < pool->base.clk_src_count; i++) { 1337 if (pool->base.clock_sources[i] == NULL) { 1338 dm_error("DC: failed to create clock sources!\n"); 1339 BREAK_TO_DEBUGGER(); 1340 goto res_create_fail; 1341 } 1342 } 1343 1344 pool->base.dmcu = dce_dmcu_create(ctx, 1345 &dmcu_regs, 1346 &dmcu_shift, 1347 &dmcu_mask); 1348 if (pool->base.dmcu == NULL) { 1349 dm_error("DC: failed to create dmcu!\n"); 1350 BREAK_TO_DEBUGGER(); 1351 goto res_create_fail; 1352 } 1353 1354 pool->base.abm = dce_abm_create(ctx, 1355 &abm_regs, 1356 &abm_shift, 1357 &abm_mask); 1358 if (pool->base.abm == NULL) { 1359 dm_error("DC: failed to create abm!\n"); 1360 BREAK_TO_DEBUGGER(); 1361 goto res_create_fail; 1362 } 1363 1364 { 1365 struct irq_service_init_data init_data; 1366 init_data.ctx = dc->ctx; 1367 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1368 if (!pool->base.irqs) 1369 goto res_create_fail; 1370 } 1371 1372 for (i = 0; i < pool->base.pipe_count; i++) { 1373 pool->base.timing_generators[i] = dce80_timing_generator_create( 1374 ctx, i, &dce80_tg_offsets[i]); 1375 if (pool->base.timing_generators[i] == NULL) { 1376 BREAK_TO_DEBUGGER(); 1377 dm_error("DC: failed to create tg!\n"); 1378 goto res_create_fail; 1379 } 1380 1381 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1382 if (pool->base.mis[i] == NULL) { 1383 BREAK_TO_DEBUGGER(); 1384 dm_error("DC: failed to create memory input!\n"); 1385 goto res_create_fail; 1386 } 1387 1388 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1389 if (pool->base.ipps[i] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error("DC: failed to create input pixel processor!\n"); 1392 goto res_create_fail; 1393 } 1394 1395 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1396 if (pool->base.transforms[i] == NULL) { 1397 BREAK_TO_DEBUGGER(); 1398 dm_error("DC: failed to create transform!\n"); 1399 goto res_create_fail; 1400 } 1401 1402 pool->base.opps[i] = dce80_opp_create(ctx, i); 1403 if (pool->base.opps[i] == NULL) { 1404 BREAK_TO_DEBUGGER(); 1405 dm_error("DC: failed to create output pixel processor!\n"); 1406 goto res_create_fail; 1407 } 1408 } 1409 1410 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1411 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1412 if (pool->base.engines[i] == NULL) { 1413 BREAK_TO_DEBUGGER(); 1414 dm_error( 1415 "DC:failed to create aux engine!!\n"); 1416 goto res_create_fail; 1417 } 1418 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1419 if (pool->base.hw_i2cs[i] == NULL) { 1420 BREAK_TO_DEBUGGER(); 1421 dm_error( 1422 "DC:failed to create i2c engine!!\n"); 1423 goto res_create_fail; 1424 } 1425 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1426 if (pool->base.sw_i2cs[i] == NULL) { 1427 BREAK_TO_DEBUGGER(); 1428 dm_error( 1429 "DC:failed to create sw i2c!!\n"); 1430 goto res_create_fail; 1431 } 1432 } 1433 1434 dc->caps.max_planes = pool->base.pipe_count; 1435 1436 for (i = 0; i < dc->caps.max_planes; ++i) 1437 dc->caps.planes[i] = plane_cap; 1438 1439 dc->caps.disable_dp_clk_share = true; 1440 1441 if (!resource_construct(num_virtual_links, dc, &pool->base, 1442 &res_create_funcs)) 1443 goto res_create_fail; 1444 1445 /* Create hardware sequencer */ 1446 dce80_hw_sequencer_construct(dc); 1447 1448 return true; 1449 1450 res_create_fail: 1451 destruct(pool); 1452 return false; 1453 } 1454 1455 struct resource_pool *dce83_create_resource_pool( 1456 uint8_t num_virtual_links, 1457 struct dc *dc) 1458 { 1459 struct dce110_resource_pool *pool = 1460 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1461 1462 if (!pool) 1463 return NULL; 1464 1465 if (dce83_construct(num_virtual_links, dc, pool)) 1466 return &pool->base; 1467 1468 BREAK_TO_DEBUGGER(); 1469 return NULL; 1470 } 1471