1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 /* TODO remove this include */ 60 61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 62 #include "gmc/gmc_7_1_d.h" 63 #include "gmc/gmc_7_1_sh_mask.h" 64 #endif 65 66 #ifndef mmDP_DPHY_INTERNAL_CTRL 67 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 75 #endif 76 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_FAST_TRAINING 84 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 85 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 87 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 88 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 89 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 90 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 91 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 92 #endif 93 94 95 #ifndef mmHPD_DC_HPD_CONTROL 96 #define mmHPD_DC_HPD_CONTROL 0x189A 97 #define mmHPD0_DC_HPD_CONTROL 0x189A 98 #define mmHPD1_DC_HPD_CONTROL 0x18A2 99 #define mmHPD2_DC_HPD_CONTROL 0x18AA 100 #define mmHPD3_DC_HPD_CONTROL 0x18B2 101 #define mmHPD4_DC_HPD_CONTROL 0x18BA 102 #define mmHPD5_DC_HPD_CONTROL 0x18C2 103 #endif 104 105 #define DCE11_DIG_FE_CNTL 0x4a00 106 #define DCE11_DIG_BE_CNTL 0x4a47 107 #define DCE11_DP_SEC 0x4ac3 108 109 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 110 { 111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 112 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 113 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 114 - mmDPG_WATERMARK_MASK_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 119 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 120 - mmDPG_WATERMARK_MASK_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 125 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 126 - mmDPG_WATERMARK_MASK_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 132 - mmDPG_WATERMARK_MASK_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 138 - mmDPG_WATERMARK_MASK_CONTROL), 139 }, 140 { 141 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 142 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 143 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 144 - mmDPG_WATERMARK_MASK_CONTROL), 145 } 146 }; 147 148 /* set register offset */ 149 #define SR(reg_name)\ 150 .reg_name = mm ## reg_name 151 152 /* set register offset with instance */ 153 #define SRI(reg_name, block, id)\ 154 .reg_name = mm ## block ## id ## _ ## reg_name 155 156 157 static const struct dccg_registers disp_clk_regs = { 158 CLK_COMMON_REG_LIST_DCE_BASE() 159 }; 160 161 static const struct dccg_shift disp_clk_shift = { 162 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 163 }; 164 165 static const struct dccg_mask disp_clk_mask = { 166 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 167 }; 168 169 #define ipp_regs(id)\ 170 [id] = {\ 171 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 172 } 173 174 static const struct dce_ipp_registers ipp_regs[] = { 175 ipp_regs(0), 176 ipp_regs(1), 177 ipp_regs(2), 178 ipp_regs(3), 179 ipp_regs(4), 180 ipp_regs(5) 181 }; 182 183 static const struct dce_ipp_shift ipp_shift = { 184 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 185 }; 186 187 static const struct dce_ipp_mask ipp_mask = { 188 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 189 }; 190 191 #define transform_regs(id)\ 192 [id] = {\ 193 XFM_COMMON_REG_LIST_DCE80(id)\ 194 } 195 196 static const struct dce_transform_registers xfm_regs[] = { 197 transform_regs(0), 198 transform_regs(1), 199 transform_regs(2), 200 transform_regs(3), 201 transform_regs(4), 202 transform_regs(5) 203 }; 204 205 static const struct dce_transform_shift xfm_shift = { 206 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 207 }; 208 209 static const struct dce_transform_mask xfm_mask = { 210 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 211 }; 212 213 #define aux_regs(id)\ 214 [id] = {\ 215 AUX_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 219 aux_regs(0), 220 aux_regs(1), 221 aux_regs(2), 222 aux_regs(3), 223 aux_regs(4), 224 aux_regs(5) 225 }; 226 227 #define hpd_regs(id)\ 228 [id] = {\ 229 HPD_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 233 hpd_regs(0), 234 hpd_regs(1), 235 hpd_regs(2), 236 hpd_regs(3), 237 hpd_regs(4), 238 hpd_regs(5) 239 }; 240 241 #define link_regs(id)\ 242 [id] = {\ 243 LE_DCE80_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_registers link_enc_regs[] = { 247 link_regs(0), 248 link_regs(1), 249 link_regs(2), 250 link_regs(3), 251 link_regs(4), 252 link_regs(5), 253 link_regs(6), 254 }; 255 256 #define stream_enc_regs(id)\ 257 [id] = {\ 258 SE_COMMON_REG_LIST_DCE_BASE(id),\ 259 .AFMT_CNTL = 0,\ 260 } 261 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 263 stream_enc_regs(0), 264 stream_enc_regs(1), 265 stream_enc_regs(2), 266 stream_enc_regs(3), 267 stream_enc_regs(4), 268 stream_enc_regs(5), 269 stream_enc_regs(6) 270 }; 271 272 static const struct dce_stream_encoder_shift se_shift = { 273 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 274 }; 275 276 static const struct dce_stream_encoder_mask se_mask = { 277 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 278 }; 279 280 #define opp_regs(id)\ 281 [id] = {\ 282 OPP_DCE_80_REG_LIST(id),\ 283 } 284 285 static const struct dce_opp_registers opp_regs[] = { 286 opp_regs(0), 287 opp_regs(1), 288 opp_regs(2), 289 opp_regs(3), 290 opp_regs(4), 291 opp_regs(5) 292 }; 293 294 static const struct dce_opp_shift opp_shift = { 295 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 296 }; 297 298 static const struct dce_opp_mask opp_mask = { 299 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 300 }; 301 302 #define aux_engine_regs(id)\ 303 [id] = {\ 304 AUX_COMMON_REG_LIST(id), \ 305 .AUX_RESET_MASK = 0 \ 306 } 307 308 static const struct dce110_aux_registers aux_engine_regs[] = { 309 aux_engine_regs(0), 310 aux_engine_regs(1), 311 aux_engine_regs(2), 312 aux_engine_regs(3), 313 aux_engine_regs(4), 314 aux_engine_regs(5) 315 }; 316 317 #define audio_regs(id)\ 318 [id] = {\ 319 AUD_COMMON_REG_LIST(id)\ 320 } 321 322 static const struct dce_audio_registers audio_regs[] = { 323 audio_regs(0), 324 audio_regs(1), 325 audio_regs(2), 326 audio_regs(3), 327 audio_regs(4), 328 audio_regs(5), 329 audio_regs(6), 330 }; 331 332 static const struct dce_audio_shift audio_shift = { 333 AUD_COMMON_MASK_SH_LIST(__SHIFT) 334 }; 335 336 static const struct dce_aduio_mask audio_mask = { 337 AUD_COMMON_MASK_SH_LIST(_MASK) 338 }; 339 340 #define clk_src_regs(id)\ 341 [id] = {\ 342 CS_COMMON_REG_LIST_DCE_80(id),\ 343 } 344 345 346 static const struct dce110_clk_src_regs clk_src_regs[] = { 347 clk_src_regs(0), 348 clk_src_regs(1), 349 clk_src_regs(2) 350 }; 351 352 static const struct dce110_clk_src_shift cs_shift = { 353 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 354 }; 355 356 static const struct dce110_clk_src_mask cs_mask = { 357 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 358 }; 359 360 static const struct bios_registers bios_regs = { 361 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 362 }; 363 364 static const struct resource_caps res_cap = { 365 .num_timing_generator = 6, 366 .num_audio = 6, 367 .num_stream_encoder = 6, 368 .num_pll = 3, 369 }; 370 371 static const struct resource_caps res_cap_81 = { 372 .num_timing_generator = 4, 373 .num_audio = 7, 374 .num_stream_encoder = 7, 375 .num_pll = 3, 376 }; 377 378 static const struct resource_caps res_cap_83 = { 379 .num_timing_generator = 2, 380 .num_audio = 6, 381 .num_stream_encoder = 6, 382 .num_pll = 2, 383 }; 384 385 static const struct dce_dmcu_registers dmcu_regs = { 386 DMCU_DCE80_REG_LIST() 387 }; 388 389 static const struct dce_dmcu_shift dmcu_shift = { 390 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 391 }; 392 393 static const struct dce_dmcu_mask dmcu_mask = { 394 DMCU_MASK_SH_LIST_DCE80(_MASK) 395 }; 396 static const struct dce_abm_registers abm_regs = { 397 ABM_DCE110_COMMON_REG_LIST() 398 }; 399 400 static const struct dce_abm_shift abm_shift = { 401 ABM_MASK_SH_LIST_DCE110(__SHIFT) 402 }; 403 404 static const struct dce_abm_mask abm_mask = { 405 ABM_MASK_SH_LIST_DCE110(_MASK) 406 }; 407 408 #define CTX ctx 409 #define REG(reg) mm ## reg 410 411 #ifndef mmCC_DC_HDMI_STRAPS 412 #define mmCC_DC_HDMI_STRAPS 0x1918 413 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 414 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 415 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 416 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 417 #endif 418 419 static void read_dce_straps( 420 struct dc_context *ctx, 421 struct resource_straps *straps) 422 { 423 REG_GET_2(CC_DC_HDMI_STRAPS, 424 HDMI_DISABLE, &straps->hdmi_disable, 425 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 426 427 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 428 } 429 430 static struct audio *create_audio( 431 struct dc_context *ctx, unsigned int inst) 432 { 433 return dce_audio_create(ctx, inst, 434 &audio_regs[inst], &audio_shift, &audio_mask); 435 } 436 437 static struct timing_generator *dce80_timing_generator_create( 438 struct dc_context *ctx, 439 uint32_t instance, 440 const struct dce110_timing_generator_offsets *offsets) 441 { 442 struct dce110_timing_generator *tg110 = 443 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 444 445 if (!tg110) 446 return NULL; 447 448 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 449 return &tg110->base; 450 } 451 452 static struct output_pixel_processor *dce80_opp_create( 453 struct dc_context *ctx, 454 uint32_t inst) 455 { 456 struct dce110_opp *opp = 457 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 458 459 if (!opp) 460 return NULL; 461 462 dce110_opp_construct(opp, 463 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 464 return &opp->base; 465 } 466 467 struct aux_engine *dce80_aux_engine_create( 468 struct dc_context *ctx, 469 uint32_t inst) 470 { 471 struct aux_engine_dce110 *aux_engine = 472 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 473 474 if (!aux_engine) 475 return NULL; 476 477 dce110_aux_engine_construct(aux_engine, ctx, inst, 478 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 479 &aux_engine_regs[inst]); 480 481 return &aux_engine->base; 482 } 483 484 static struct stream_encoder *dce80_stream_encoder_create( 485 enum engine_id eng_id, 486 struct dc_context *ctx) 487 { 488 struct dce110_stream_encoder *enc110 = 489 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 490 491 if (!enc110) 492 return NULL; 493 494 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 495 &stream_enc_regs[eng_id], 496 &se_shift, &se_mask); 497 return &enc110->base; 498 } 499 500 #define SRII(reg_name, block, id)\ 501 .reg_name[id] = mm ## block ## id ## _ ## reg_name 502 503 static const struct dce_hwseq_registers hwseq_reg = { 504 HWSEQ_DCE8_REG_LIST() 505 }; 506 507 static const struct dce_hwseq_shift hwseq_shift = { 508 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 509 }; 510 511 static const struct dce_hwseq_mask hwseq_mask = { 512 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 513 }; 514 515 static struct dce_hwseq *dce80_hwseq_create( 516 struct dc_context *ctx) 517 { 518 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 519 520 if (hws) { 521 hws->ctx = ctx; 522 hws->regs = &hwseq_reg; 523 hws->shifts = &hwseq_shift; 524 hws->masks = &hwseq_mask; 525 } 526 return hws; 527 } 528 529 static const struct resource_create_funcs res_create_funcs = { 530 .read_dce_straps = read_dce_straps, 531 .create_audio = create_audio, 532 .create_stream_encoder = dce80_stream_encoder_create, 533 .create_hwseq = dce80_hwseq_create, 534 }; 535 536 #define mi_inst_regs(id) { \ 537 MI_DCE8_REG_LIST(id), \ 538 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 539 } 540 static const struct dce_mem_input_registers mi_regs[] = { 541 mi_inst_regs(0), 542 mi_inst_regs(1), 543 mi_inst_regs(2), 544 mi_inst_regs(3), 545 mi_inst_regs(4), 546 mi_inst_regs(5), 547 }; 548 549 static const struct dce_mem_input_shift mi_shifts = { 550 MI_DCE8_MASK_SH_LIST(__SHIFT), 551 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 552 }; 553 554 static const struct dce_mem_input_mask mi_masks = { 555 MI_DCE8_MASK_SH_LIST(_MASK), 556 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 557 }; 558 559 static struct mem_input *dce80_mem_input_create( 560 struct dc_context *ctx, 561 uint32_t inst) 562 { 563 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 564 GFP_KERNEL); 565 566 if (!dce_mi) { 567 BREAK_TO_DEBUGGER(); 568 return NULL; 569 } 570 571 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 572 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 573 return &dce_mi->base; 574 } 575 576 static void dce80_transform_destroy(struct transform **xfm) 577 { 578 kfree(TO_DCE_TRANSFORM(*xfm)); 579 *xfm = NULL; 580 } 581 582 static struct transform *dce80_transform_create( 583 struct dc_context *ctx, 584 uint32_t inst) 585 { 586 struct dce_transform *transform = 587 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 588 589 if (!transform) 590 return NULL; 591 592 dce_transform_construct(transform, ctx, inst, 593 &xfm_regs[inst], &xfm_shift, &xfm_mask); 594 transform->prescaler_on = false; 595 return &transform->base; 596 } 597 598 static const struct encoder_feature_support link_enc_feature = { 599 .max_hdmi_deep_color = COLOR_DEPTH_121212, 600 .max_hdmi_pixel_clock = 297000, 601 .flags.bits.IS_HBR2_CAPABLE = true, 602 .flags.bits.IS_TPS3_CAPABLE = true, 603 .flags.bits.IS_YCBCR_CAPABLE = true 604 }; 605 606 struct link_encoder *dce80_link_encoder_create( 607 const struct encoder_init_data *enc_init_data) 608 { 609 struct dce110_link_encoder *enc110 = 610 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 611 612 if (!enc110) 613 return NULL; 614 615 dce110_link_encoder_construct(enc110, 616 enc_init_data, 617 &link_enc_feature, 618 &link_enc_regs[enc_init_data->transmitter], 619 &link_enc_aux_regs[enc_init_data->channel - 1], 620 &link_enc_hpd_regs[enc_init_data->hpd_source]); 621 return &enc110->base; 622 } 623 624 struct clock_source *dce80_clock_source_create( 625 struct dc_context *ctx, 626 struct dc_bios *bios, 627 enum clock_source_id id, 628 const struct dce110_clk_src_regs *regs, 629 bool dp_clk_src) 630 { 631 struct dce110_clk_src *clk_src = 632 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 633 634 if (!clk_src) 635 return NULL; 636 637 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 638 regs, &cs_shift, &cs_mask)) { 639 clk_src->base.dp_clk_src = dp_clk_src; 640 return &clk_src->base; 641 } 642 643 BREAK_TO_DEBUGGER(); 644 return NULL; 645 } 646 647 void dce80_clock_source_destroy(struct clock_source **clk_src) 648 { 649 kfree(TO_DCE110_CLK_SRC(*clk_src)); 650 *clk_src = NULL; 651 } 652 653 static struct input_pixel_processor *dce80_ipp_create( 654 struct dc_context *ctx, uint32_t inst) 655 { 656 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 657 658 if (!ipp) { 659 BREAK_TO_DEBUGGER(); 660 return NULL; 661 } 662 663 dce_ipp_construct(ipp, ctx, inst, 664 &ipp_regs[inst], &ipp_shift, &ipp_mask); 665 return &ipp->base; 666 } 667 668 static void destruct(struct dce110_resource_pool *pool) 669 { 670 unsigned int i; 671 672 for (i = 0; i < pool->base.pipe_count; i++) { 673 if (pool->base.opps[i] != NULL) 674 dce110_opp_destroy(&pool->base.opps[i]); 675 676 if (pool->base.transforms[i] != NULL) 677 dce80_transform_destroy(&pool->base.transforms[i]); 678 679 if (pool->base.ipps[i] != NULL) 680 dce_ipp_destroy(&pool->base.ipps[i]); 681 682 if (pool->base.mis[i] != NULL) { 683 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 684 pool->base.mis[i] = NULL; 685 } 686 687 if (pool->base.timing_generators[i] != NULL) { 688 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 689 pool->base.timing_generators[i] = NULL; 690 } 691 692 if (pool->base.engines[i] != NULL) 693 dce110_engine_destroy(&pool->base.engines[i]); 694 } 695 696 for (i = 0; i < pool->base.stream_enc_count; i++) { 697 if (pool->base.stream_enc[i] != NULL) 698 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 699 } 700 701 for (i = 0; i < pool->base.clk_src_count; i++) { 702 if (pool->base.clock_sources[i] != NULL) { 703 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 704 } 705 } 706 707 if (pool->base.abm != NULL) 708 dce_abm_destroy(&pool->base.abm); 709 710 if (pool->base.dmcu != NULL) 711 dce_dmcu_destroy(&pool->base.dmcu); 712 713 if (pool->base.dp_clock_source != NULL) 714 dce80_clock_source_destroy(&pool->base.dp_clock_source); 715 716 for (i = 0; i < pool->base.audio_count; i++) { 717 if (pool->base.audios[i] != NULL) { 718 dce_aud_destroy(&pool->base.audios[i]); 719 } 720 } 721 722 if (pool->base.dccg != NULL) 723 dce_dccg_destroy(&pool->base.dccg); 724 725 if (pool->base.irqs != NULL) { 726 dal_irq_service_destroy(&pool->base.irqs); 727 } 728 } 729 730 bool dce80_validate_bandwidth( 731 struct dc *dc, 732 struct dc_state *context) 733 { 734 /* TODO implement when needed but for now hardcode max value*/ 735 context->bw.dce.dispclk_khz = 681000; 736 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 737 738 return true; 739 } 740 741 static bool dce80_validate_surface_sets( 742 struct dc_state *context) 743 { 744 int i; 745 746 for (i = 0; i < context->stream_count; i++) { 747 if (context->stream_status[i].plane_count == 0) 748 continue; 749 750 if (context->stream_status[i].plane_count > 1) 751 return false; 752 753 if (context->stream_status[i].plane_states[0]->format 754 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 755 return false; 756 } 757 758 return true; 759 } 760 761 enum dc_status dce80_validate_global( 762 struct dc *dc, 763 struct dc_state *context) 764 { 765 if (!dce80_validate_surface_sets(context)) 766 return DC_FAIL_SURFACE_VALIDATE; 767 768 return DC_OK; 769 } 770 771 static void dce80_destroy_resource_pool(struct resource_pool **pool) 772 { 773 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 774 775 destruct(dce110_pool); 776 kfree(dce110_pool); 777 *pool = NULL; 778 } 779 780 static const struct resource_funcs dce80_res_pool_funcs = { 781 .destroy = dce80_destroy_resource_pool, 782 .link_enc_create = dce80_link_encoder_create, 783 .validate_bandwidth = dce80_validate_bandwidth, 784 .validate_plane = dce100_validate_plane, 785 .add_stream_to_ctx = dce100_add_stream_to_ctx, 786 .validate_global = dce80_validate_global 787 }; 788 789 static bool dce80_construct( 790 uint8_t num_virtual_links, 791 struct dc *dc, 792 struct dce110_resource_pool *pool) 793 { 794 unsigned int i; 795 struct dc_context *ctx = dc->ctx; 796 struct dc_firmware_info info; 797 struct dc_bios *bp; 798 struct dm_pp_static_clock_info static_clk_info = {0}; 799 800 ctx->dc_bios->regs = &bios_regs; 801 802 pool->base.res_cap = &res_cap; 803 pool->base.funcs = &dce80_res_pool_funcs; 804 805 806 /************************************************* 807 * Resource + asic cap harcoding * 808 *************************************************/ 809 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 810 pool->base.pipe_count = res_cap.num_timing_generator; 811 pool->base.timing_generator_count = res_cap.num_timing_generator; 812 dc->caps.max_downscale_ratio = 200; 813 dc->caps.i2c_speed_in_khz = 40; 814 dc->caps.max_cursor_size = 128; 815 dc->caps.dual_link_dvi = true; 816 817 /************************************************* 818 * Create resources * 819 *************************************************/ 820 821 bp = ctx->dc_bios; 822 823 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 824 info.external_clock_source_frequency_for_dp != 0) { 825 pool->base.dp_clock_source = 826 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 827 828 pool->base.clock_sources[0] = 829 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 830 pool->base.clock_sources[1] = 831 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 832 pool->base.clock_sources[2] = 833 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 834 pool->base.clk_src_count = 3; 835 836 } else { 837 pool->base.dp_clock_source = 838 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 839 840 pool->base.clock_sources[0] = 841 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 842 pool->base.clock_sources[1] = 843 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 844 pool->base.clk_src_count = 2; 845 } 846 847 if (pool->base.dp_clock_source == NULL) { 848 dm_error("DC: failed to create dp clock source!\n"); 849 BREAK_TO_DEBUGGER(); 850 goto res_create_fail; 851 } 852 853 for (i = 0; i < pool->base.clk_src_count; i++) { 854 if (pool->base.clock_sources[i] == NULL) { 855 dm_error("DC: failed to create clock sources!\n"); 856 BREAK_TO_DEBUGGER(); 857 goto res_create_fail; 858 } 859 } 860 861 pool->base.dccg = dce_dccg_create(ctx, 862 &disp_clk_regs, 863 &disp_clk_shift, 864 &disp_clk_mask); 865 if (pool->base.dccg == NULL) { 866 dm_error("DC: failed to create display clock!\n"); 867 BREAK_TO_DEBUGGER(); 868 goto res_create_fail; 869 } 870 871 pool->base.dmcu = dce_dmcu_create(ctx, 872 &dmcu_regs, 873 &dmcu_shift, 874 &dmcu_mask); 875 if (pool->base.dmcu == NULL) { 876 dm_error("DC: failed to create dmcu!\n"); 877 BREAK_TO_DEBUGGER(); 878 goto res_create_fail; 879 } 880 881 pool->base.abm = dce_abm_create(ctx, 882 &abm_regs, 883 &abm_shift, 884 &abm_mask); 885 if (pool->base.abm == NULL) { 886 dm_error("DC: failed to create abm!\n"); 887 BREAK_TO_DEBUGGER(); 888 goto res_create_fail; 889 } 890 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 891 pool->base.dccg->max_clks_state = 892 static_clk_info.max_clocks_state; 893 894 { 895 struct irq_service_init_data init_data; 896 init_data.ctx = dc->ctx; 897 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 898 if (!pool->base.irqs) 899 goto res_create_fail; 900 } 901 902 for (i = 0; i < pool->base.pipe_count; i++) { 903 pool->base.timing_generators[i] = dce80_timing_generator_create( 904 ctx, i, &dce80_tg_offsets[i]); 905 if (pool->base.timing_generators[i] == NULL) { 906 BREAK_TO_DEBUGGER(); 907 dm_error("DC: failed to create tg!\n"); 908 goto res_create_fail; 909 } 910 911 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 912 if (pool->base.mis[i] == NULL) { 913 BREAK_TO_DEBUGGER(); 914 dm_error("DC: failed to create memory input!\n"); 915 goto res_create_fail; 916 } 917 918 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 919 if (pool->base.ipps[i] == NULL) { 920 BREAK_TO_DEBUGGER(); 921 dm_error("DC: failed to create input pixel processor!\n"); 922 goto res_create_fail; 923 } 924 925 pool->base.transforms[i] = dce80_transform_create(ctx, i); 926 if (pool->base.transforms[i] == NULL) { 927 BREAK_TO_DEBUGGER(); 928 dm_error("DC: failed to create transform!\n"); 929 goto res_create_fail; 930 } 931 932 pool->base.opps[i] = dce80_opp_create(ctx, i); 933 if (pool->base.opps[i] == NULL) { 934 BREAK_TO_DEBUGGER(); 935 dm_error("DC: failed to create output pixel processor!\n"); 936 goto res_create_fail; 937 } 938 939 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 940 if (pool->base.engines[i] == NULL) { 941 BREAK_TO_DEBUGGER(); 942 dm_error( 943 "DC:failed to create aux engine!!\n"); 944 goto res_create_fail; 945 } 946 } 947 948 dc->caps.max_planes = pool->base.pipe_count; 949 dc->caps.disable_dp_clk_share = true; 950 951 if (!resource_construct(num_virtual_links, dc, &pool->base, 952 &res_create_funcs)) 953 goto res_create_fail; 954 955 /* Create hardware sequencer */ 956 dce80_hw_sequencer_construct(dc); 957 958 return true; 959 960 res_create_fail: 961 destruct(pool); 962 return false; 963 } 964 965 struct resource_pool *dce80_create_resource_pool( 966 uint8_t num_virtual_links, 967 struct dc *dc) 968 { 969 struct dce110_resource_pool *pool = 970 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 971 972 if (!pool) 973 return NULL; 974 975 if (dce80_construct(num_virtual_links, dc, pool)) 976 return &pool->base; 977 978 BREAK_TO_DEBUGGER(); 979 return NULL; 980 } 981 982 static bool dce81_construct( 983 uint8_t num_virtual_links, 984 struct dc *dc, 985 struct dce110_resource_pool *pool) 986 { 987 unsigned int i; 988 struct dc_context *ctx = dc->ctx; 989 struct dc_firmware_info info; 990 struct dc_bios *bp; 991 struct dm_pp_static_clock_info static_clk_info = {0}; 992 993 ctx->dc_bios->regs = &bios_regs; 994 995 pool->base.res_cap = &res_cap_81; 996 pool->base.funcs = &dce80_res_pool_funcs; 997 998 999 /************************************************* 1000 * Resource + asic cap harcoding * 1001 *************************************************/ 1002 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1003 pool->base.pipe_count = res_cap_81.num_timing_generator; 1004 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1005 dc->caps.max_downscale_ratio = 200; 1006 dc->caps.i2c_speed_in_khz = 40; 1007 dc->caps.max_cursor_size = 128; 1008 dc->caps.is_apu = true; 1009 1010 /************************************************* 1011 * Create resources * 1012 *************************************************/ 1013 1014 bp = ctx->dc_bios; 1015 1016 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1017 info.external_clock_source_frequency_for_dp != 0) { 1018 pool->base.dp_clock_source = 1019 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1020 1021 pool->base.clock_sources[0] = 1022 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1023 pool->base.clock_sources[1] = 1024 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1025 pool->base.clock_sources[2] = 1026 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1027 pool->base.clk_src_count = 3; 1028 1029 } else { 1030 pool->base.dp_clock_source = 1031 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1032 1033 pool->base.clock_sources[0] = 1034 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1035 pool->base.clock_sources[1] = 1036 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1037 pool->base.clk_src_count = 2; 1038 } 1039 1040 if (pool->base.dp_clock_source == NULL) { 1041 dm_error("DC: failed to create dp clock source!\n"); 1042 BREAK_TO_DEBUGGER(); 1043 goto res_create_fail; 1044 } 1045 1046 for (i = 0; i < pool->base.clk_src_count; i++) { 1047 if (pool->base.clock_sources[i] == NULL) { 1048 dm_error("DC: failed to create clock sources!\n"); 1049 BREAK_TO_DEBUGGER(); 1050 goto res_create_fail; 1051 } 1052 } 1053 1054 pool->base.dccg = dce_dccg_create(ctx, 1055 &disp_clk_regs, 1056 &disp_clk_shift, 1057 &disp_clk_mask); 1058 if (pool->base.dccg == NULL) { 1059 dm_error("DC: failed to create display clock!\n"); 1060 BREAK_TO_DEBUGGER(); 1061 goto res_create_fail; 1062 } 1063 1064 pool->base.dmcu = dce_dmcu_create(ctx, 1065 &dmcu_regs, 1066 &dmcu_shift, 1067 &dmcu_mask); 1068 if (pool->base.dmcu == NULL) { 1069 dm_error("DC: failed to create dmcu!\n"); 1070 BREAK_TO_DEBUGGER(); 1071 goto res_create_fail; 1072 } 1073 1074 pool->base.abm = dce_abm_create(ctx, 1075 &abm_regs, 1076 &abm_shift, 1077 &abm_mask); 1078 if (pool->base.abm == NULL) { 1079 dm_error("DC: failed to create abm!\n"); 1080 BREAK_TO_DEBUGGER(); 1081 goto res_create_fail; 1082 } 1083 1084 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1085 pool->base.dccg->max_clks_state = 1086 static_clk_info.max_clocks_state; 1087 1088 { 1089 struct irq_service_init_data init_data; 1090 init_data.ctx = dc->ctx; 1091 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1092 if (!pool->base.irqs) 1093 goto res_create_fail; 1094 } 1095 1096 for (i = 0; i < pool->base.pipe_count; i++) { 1097 pool->base.timing_generators[i] = dce80_timing_generator_create( 1098 ctx, i, &dce80_tg_offsets[i]); 1099 if (pool->base.timing_generators[i] == NULL) { 1100 BREAK_TO_DEBUGGER(); 1101 dm_error("DC: failed to create tg!\n"); 1102 goto res_create_fail; 1103 } 1104 1105 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1106 if (pool->base.mis[i] == NULL) { 1107 BREAK_TO_DEBUGGER(); 1108 dm_error("DC: failed to create memory input!\n"); 1109 goto res_create_fail; 1110 } 1111 1112 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1113 if (pool->base.ipps[i] == NULL) { 1114 BREAK_TO_DEBUGGER(); 1115 dm_error("DC: failed to create input pixel processor!\n"); 1116 goto res_create_fail; 1117 } 1118 1119 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1120 if (pool->base.transforms[i] == NULL) { 1121 BREAK_TO_DEBUGGER(); 1122 dm_error("DC: failed to create transform!\n"); 1123 goto res_create_fail; 1124 } 1125 1126 pool->base.opps[i] = dce80_opp_create(ctx, i); 1127 if (pool->base.opps[i] == NULL) { 1128 BREAK_TO_DEBUGGER(); 1129 dm_error("DC: failed to create output pixel processor!\n"); 1130 goto res_create_fail; 1131 } 1132 } 1133 1134 dc->caps.max_planes = pool->base.pipe_count; 1135 dc->caps.disable_dp_clk_share = true; 1136 1137 if (!resource_construct(num_virtual_links, dc, &pool->base, 1138 &res_create_funcs)) 1139 goto res_create_fail; 1140 1141 /* Create hardware sequencer */ 1142 dce80_hw_sequencer_construct(dc); 1143 1144 return true; 1145 1146 res_create_fail: 1147 destruct(pool); 1148 return false; 1149 } 1150 1151 struct resource_pool *dce81_create_resource_pool( 1152 uint8_t num_virtual_links, 1153 struct dc *dc) 1154 { 1155 struct dce110_resource_pool *pool = 1156 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1157 1158 if (!pool) 1159 return NULL; 1160 1161 if (dce81_construct(num_virtual_links, dc, pool)) 1162 return &pool->base; 1163 1164 BREAK_TO_DEBUGGER(); 1165 return NULL; 1166 } 1167 1168 static bool dce83_construct( 1169 uint8_t num_virtual_links, 1170 struct dc *dc, 1171 struct dce110_resource_pool *pool) 1172 { 1173 unsigned int i; 1174 struct dc_context *ctx = dc->ctx; 1175 struct dc_firmware_info info; 1176 struct dc_bios *bp; 1177 struct dm_pp_static_clock_info static_clk_info = {0}; 1178 1179 ctx->dc_bios->regs = &bios_regs; 1180 1181 pool->base.res_cap = &res_cap_83; 1182 pool->base.funcs = &dce80_res_pool_funcs; 1183 1184 1185 /************************************************* 1186 * Resource + asic cap harcoding * 1187 *************************************************/ 1188 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1189 pool->base.pipe_count = res_cap_83.num_timing_generator; 1190 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1191 dc->caps.max_downscale_ratio = 200; 1192 dc->caps.i2c_speed_in_khz = 40; 1193 dc->caps.max_cursor_size = 128; 1194 dc->caps.is_apu = true; 1195 1196 /************************************************* 1197 * Create resources * 1198 *************************************************/ 1199 1200 bp = ctx->dc_bios; 1201 1202 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1203 info.external_clock_source_frequency_for_dp != 0) { 1204 pool->base.dp_clock_source = 1205 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1206 1207 pool->base.clock_sources[0] = 1208 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1209 pool->base.clock_sources[1] = 1210 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1211 pool->base.clk_src_count = 2; 1212 1213 } else { 1214 pool->base.dp_clock_source = 1215 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1216 1217 pool->base.clock_sources[0] = 1218 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1219 pool->base.clk_src_count = 1; 1220 } 1221 1222 if (pool->base.dp_clock_source == NULL) { 1223 dm_error("DC: failed to create dp clock source!\n"); 1224 BREAK_TO_DEBUGGER(); 1225 goto res_create_fail; 1226 } 1227 1228 for (i = 0; i < pool->base.clk_src_count; i++) { 1229 if (pool->base.clock_sources[i] == NULL) { 1230 dm_error("DC: failed to create clock sources!\n"); 1231 BREAK_TO_DEBUGGER(); 1232 goto res_create_fail; 1233 } 1234 } 1235 1236 pool->base.dccg = dce_dccg_create(ctx, 1237 &disp_clk_regs, 1238 &disp_clk_shift, 1239 &disp_clk_mask); 1240 if (pool->base.dccg == NULL) { 1241 dm_error("DC: failed to create display clock!\n"); 1242 BREAK_TO_DEBUGGER(); 1243 goto res_create_fail; 1244 } 1245 1246 pool->base.dmcu = dce_dmcu_create(ctx, 1247 &dmcu_regs, 1248 &dmcu_shift, 1249 &dmcu_mask); 1250 if (pool->base.dmcu == NULL) { 1251 dm_error("DC: failed to create dmcu!\n"); 1252 BREAK_TO_DEBUGGER(); 1253 goto res_create_fail; 1254 } 1255 1256 pool->base.abm = dce_abm_create(ctx, 1257 &abm_regs, 1258 &abm_shift, 1259 &abm_mask); 1260 if (pool->base.abm == NULL) { 1261 dm_error("DC: failed to create abm!\n"); 1262 BREAK_TO_DEBUGGER(); 1263 goto res_create_fail; 1264 } 1265 1266 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1267 pool->base.dccg->max_clks_state = 1268 static_clk_info.max_clocks_state; 1269 1270 { 1271 struct irq_service_init_data init_data; 1272 init_data.ctx = dc->ctx; 1273 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1274 if (!pool->base.irqs) 1275 goto res_create_fail; 1276 } 1277 1278 for (i = 0; i < pool->base.pipe_count; i++) { 1279 pool->base.timing_generators[i] = dce80_timing_generator_create( 1280 ctx, i, &dce80_tg_offsets[i]); 1281 if (pool->base.timing_generators[i] == NULL) { 1282 BREAK_TO_DEBUGGER(); 1283 dm_error("DC: failed to create tg!\n"); 1284 goto res_create_fail; 1285 } 1286 1287 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1288 if (pool->base.mis[i] == NULL) { 1289 BREAK_TO_DEBUGGER(); 1290 dm_error("DC: failed to create memory input!\n"); 1291 goto res_create_fail; 1292 } 1293 1294 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1295 if (pool->base.ipps[i] == NULL) { 1296 BREAK_TO_DEBUGGER(); 1297 dm_error("DC: failed to create input pixel processor!\n"); 1298 goto res_create_fail; 1299 } 1300 1301 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1302 if (pool->base.transforms[i] == NULL) { 1303 BREAK_TO_DEBUGGER(); 1304 dm_error("DC: failed to create transform!\n"); 1305 goto res_create_fail; 1306 } 1307 1308 pool->base.opps[i] = dce80_opp_create(ctx, i); 1309 if (pool->base.opps[i] == NULL) { 1310 BREAK_TO_DEBUGGER(); 1311 dm_error("DC: failed to create output pixel processor!\n"); 1312 goto res_create_fail; 1313 } 1314 } 1315 1316 dc->caps.max_planes = pool->base.pipe_count; 1317 dc->caps.disable_dp_clk_share = true; 1318 1319 if (!resource_construct(num_virtual_links, dc, &pool->base, 1320 &res_create_funcs)) 1321 goto res_create_fail; 1322 1323 /* Create hardware sequencer */ 1324 dce80_hw_sequencer_construct(dc); 1325 1326 return true; 1327 1328 res_create_fail: 1329 destruct(pool); 1330 return false; 1331 } 1332 1333 struct resource_pool *dce83_create_resource_pool( 1334 uint8_t num_virtual_links, 1335 struct dc *dc) 1336 { 1337 struct dce110_resource_pool *pool = 1338 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1339 1340 if (!pool) 1341 return NULL; 1342 1343 if (dce83_construct(num_virtual_links, dc, pool)) 1344 return &pool->base; 1345 1346 BREAK_TO_DEBUGGER(); 1347 return NULL; 1348 } 1349