1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_clk_mgr.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce/dce_link_encoder.h" 43 #include "dce/dce_stream_encoder.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_audio.h" 49 #include "dce/dce_hwseq.h" 50 #include "dce80/dce80_hw_sequencer.h" 51 #include "dce100/dce100_resource.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_i2c.h" 59 /* TODO remove this include */ 60 61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 62 #include "gmc/gmc_7_1_d.h" 63 #include "gmc/gmc_7_1_sh_mask.h" 64 #endif 65 66 #ifndef mmDP_DPHY_INTERNAL_CTRL 67 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 75 #endif 76 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_3 0x05CC 81 #define mmBIOS_SCRATCH_6 0x05CF 82 #endif 83 84 #ifndef mmDP_DPHY_FAST_TRAINING 85 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 86 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 88 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 89 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 90 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 91 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 92 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 93 #endif 94 95 96 #ifndef mmHPD_DC_HPD_CONTROL 97 #define mmHPD_DC_HPD_CONTROL 0x189A 98 #define mmHPD0_DC_HPD_CONTROL 0x189A 99 #define mmHPD1_DC_HPD_CONTROL 0x18A2 100 #define mmHPD2_DC_HPD_CONTROL 0x18AA 101 #define mmHPD3_DC_HPD_CONTROL 0x18B2 102 #define mmHPD4_DC_HPD_CONTROL 0x18BA 103 #define mmHPD5_DC_HPD_CONTROL 0x18C2 104 #endif 105 106 #define DCE11_DIG_FE_CNTL 0x4a00 107 #define DCE11_DIG_BE_CNTL 0x4a47 108 #define DCE11_DP_SEC 0x4ac3 109 110 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 111 { 112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 114 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 115 - mmDPG_WATERMARK_MASK_CONTROL), 116 }, 117 { 118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 120 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 121 - mmDPG_WATERMARK_MASK_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 127 - mmDPG_WATERMARK_MASK_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 133 - mmDPG_WATERMARK_MASK_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 138 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 139 - mmDPG_WATERMARK_MASK_CONTROL), 140 }, 141 { 142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 144 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 145 - mmDPG_WATERMARK_MASK_CONTROL), 146 } 147 }; 148 149 /* set register offset */ 150 #define SR(reg_name)\ 151 .reg_name = mm ## reg_name 152 153 /* set register offset with instance */ 154 #define SRI(reg_name, block, id)\ 155 .reg_name = mm ## block ## id ## _ ## reg_name 156 157 158 static const struct clk_mgr_registers disp_clk_regs = { 159 CLK_COMMON_REG_LIST_DCE_BASE() 160 }; 161 162 static const struct clk_mgr_shift disp_clk_shift = { 163 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 164 }; 165 166 static const struct clk_mgr_mask disp_clk_mask = { 167 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 168 }; 169 170 #define ipp_regs(id)\ 171 [id] = {\ 172 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 173 } 174 175 static const struct dce_ipp_registers ipp_regs[] = { 176 ipp_regs(0), 177 ipp_regs(1), 178 ipp_regs(2), 179 ipp_regs(3), 180 ipp_regs(4), 181 ipp_regs(5) 182 }; 183 184 static const struct dce_ipp_shift ipp_shift = { 185 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 186 }; 187 188 static const struct dce_ipp_mask ipp_mask = { 189 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 190 }; 191 192 #define transform_regs(id)\ 193 [id] = {\ 194 XFM_COMMON_REG_LIST_DCE80(id)\ 195 } 196 197 static const struct dce_transform_registers xfm_regs[] = { 198 transform_regs(0), 199 transform_regs(1), 200 transform_regs(2), 201 transform_regs(3), 202 transform_regs(4), 203 transform_regs(5) 204 }; 205 206 static const struct dce_transform_shift xfm_shift = { 207 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 208 }; 209 210 static const struct dce_transform_mask xfm_mask = { 211 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 212 }; 213 214 #define aux_regs(id)\ 215 [id] = {\ 216 AUX_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 220 aux_regs(0), 221 aux_regs(1), 222 aux_regs(2), 223 aux_regs(3), 224 aux_regs(4), 225 aux_regs(5) 226 }; 227 228 #define hpd_regs(id)\ 229 [id] = {\ 230 HPD_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 234 hpd_regs(0), 235 hpd_regs(1), 236 hpd_regs(2), 237 hpd_regs(3), 238 hpd_regs(4), 239 hpd_regs(5) 240 }; 241 242 #define link_regs(id)\ 243 [id] = {\ 244 LE_DCE80_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_registers link_enc_regs[] = { 248 link_regs(0), 249 link_regs(1), 250 link_regs(2), 251 link_regs(3), 252 link_regs(4), 253 link_regs(5), 254 link_regs(6), 255 }; 256 257 #define stream_enc_regs(id)\ 258 [id] = {\ 259 SE_COMMON_REG_LIST_DCE_BASE(id),\ 260 .AFMT_CNTL = 0,\ 261 } 262 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 264 stream_enc_regs(0), 265 stream_enc_regs(1), 266 stream_enc_regs(2), 267 stream_enc_regs(3), 268 stream_enc_regs(4), 269 stream_enc_regs(5), 270 stream_enc_regs(6) 271 }; 272 273 static const struct dce_stream_encoder_shift se_shift = { 274 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 275 }; 276 277 static const struct dce_stream_encoder_mask se_mask = { 278 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 279 }; 280 281 #define opp_regs(id)\ 282 [id] = {\ 283 OPP_DCE_80_REG_LIST(id),\ 284 } 285 286 static const struct dce_opp_registers opp_regs[] = { 287 opp_regs(0), 288 opp_regs(1), 289 opp_regs(2), 290 opp_regs(3), 291 opp_regs(4), 292 opp_regs(5) 293 }; 294 295 static const struct dce_opp_shift opp_shift = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 297 }; 298 299 static const struct dce_opp_mask opp_mask = { 300 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 301 }; 302 303 #define aux_engine_regs(id)\ 304 [id] = {\ 305 AUX_COMMON_REG_LIST(id), \ 306 .AUX_RESET_MASK = 0 \ 307 } 308 309 static const struct dce110_aux_registers aux_engine_regs[] = { 310 aux_engine_regs(0), 311 aux_engine_regs(1), 312 aux_engine_regs(2), 313 aux_engine_regs(3), 314 aux_engine_regs(4), 315 aux_engine_regs(5) 316 }; 317 318 #define audio_regs(id)\ 319 [id] = {\ 320 AUD_COMMON_REG_LIST(id)\ 321 } 322 323 static const struct dce_audio_registers audio_regs[] = { 324 audio_regs(0), 325 audio_regs(1), 326 audio_regs(2), 327 audio_regs(3), 328 audio_regs(4), 329 audio_regs(5), 330 audio_regs(6), 331 }; 332 333 static const struct dce_audio_shift audio_shift = { 334 AUD_COMMON_MASK_SH_LIST(__SHIFT) 335 }; 336 337 static const struct dce_aduio_mask audio_mask = { 338 AUD_COMMON_MASK_SH_LIST(_MASK) 339 }; 340 341 #define clk_src_regs(id)\ 342 [id] = {\ 343 CS_COMMON_REG_LIST_DCE_80(id),\ 344 } 345 346 347 static const struct dce110_clk_src_regs clk_src_regs[] = { 348 clk_src_regs(0), 349 clk_src_regs(1), 350 clk_src_regs(2) 351 }; 352 353 static const struct dce110_clk_src_shift cs_shift = { 354 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 355 }; 356 357 static const struct dce110_clk_src_mask cs_mask = { 358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 359 }; 360 361 static const struct bios_registers bios_regs = { 362 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 363 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 364 }; 365 366 static const struct resource_caps res_cap = { 367 .num_timing_generator = 6, 368 .num_audio = 6, 369 .num_stream_encoder = 6, 370 .num_pll = 3, 371 .num_ddc = 6, 372 }; 373 374 static const struct resource_caps res_cap_81 = { 375 .num_timing_generator = 4, 376 .num_audio = 7, 377 .num_stream_encoder = 7, 378 .num_pll = 3, 379 .num_ddc = 6, 380 }; 381 382 static const struct resource_caps res_cap_83 = { 383 .num_timing_generator = 2, 384 .num_audio = 6, 385 .num_stream_encoder = 6, 386 .num_pll = 2, 387 .num_ddc = 2, 388 }; 389 390 static const struct dc_plane_cap plane_cap = { 391 .type = DC_PLANE_TYPE_DCE_RGB, 392 393 .pixel_format_support = { 394 .argb8888 = true, 395 .nv12 = false, 396 .fp16 = false 397 }, 398 399 .max_upscale_factor = { 400 .argb8888 = 16000, 401 .nv12 = 1, 402 .fp16 = 1 403 }, 404 405 .max_downscale_factor = { 406 .argb8888 = 250, 407 .nv12 = 1, 408 .fp16 = 1 409 } 410 }; 411 412 static const struct dce_dmcu_registers dmcu_regs = { 413 DMCU_DCE80_REG_LIST() 414 }; 415 416 static const struct dce_dmcu_shift dmcu_shift = { 417 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 418 }; 419 420 static const struct dce_dmcu_mask dmcu_mask = { 421 DMCU_MASK_SH_LIST_DCE80(_MASK) 422 }; 423 static const struct dce_abm_registers abm_regs = { 424 ABM_DCE110_COMMON_REG_LIST() 425 }; 426 427 static const struct dce_abm_shift abm_shift = { 428 ABM_MASK_SH_LIST_DCE110(__SHIFT) 429 }; 430 431 static const struct dce_abm_mask abm_mask = { 432 ABM_MASK_SH_LIST_DCE110(_MASK) 433 }; 434 435 #define CTX ctx 436 #define REG(reg) mm ## reg 437 438 #ifndef mmCC_DC_HDMI_STRAPS 439 #define mmCC_DC_HDMI_STRAPS 0x1918 440 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 441 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 442 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 443 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 444 #endif 445 446 static void read_dce_straps( 447 struct dc_context *ctx, 448 struct resource_straps *straps) 449 { 450 REG_GET_2(CC_DC_HDMI_STRAPS, 451 HDMI_DISABLE, &straps->hdmi_disable, 452 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 453 454 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 455 } 456 457 static struct audio *create_audio( 458 struct dc_context *ctx, unsigned int inst) 459 { 460 return dce_audio_create(ctx, inst, 461 &audio_regs[inst], &audio_shift, &audio_mask); 462 } 463 464 static struct timing_generator *dce80_timing_generator_create( 465 struct dc_context *ctx, 466 uint32_t instance, 467 const struct dce110_timing_generator_offsets *offsets) 468 { 469 struct dce110_timing_generator *tg110 = 470 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 471 472 if (!tg110) 473 return NULL; 474 475 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 476 return &tg110->base; 477 } 478 479 static struct output_pixel_processor *dce80_opp_create( 480 struct dc_context *ctx, 481 uint32_t inst) 482 { 483 struct dce110_opp *opp = 484 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 485 486 if (!opp) 487 return NULL; 488 489 dce110_opp_construct(opp, 490 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 491 return &opp->base; 492 } 493 494 struct dce_aux *dce80_aux_engine_create( 495 struct dc_context *ctx, 496 uint32_t inst) 497 { 498 struct aux_engine_dce110 *aux_engine = 499 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 500 501 if (!aux_engine) 502 return NULL; 503 504 dce110_aux_engine_construct(aux_engine, ctx, inst, 505 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 506 &aux_engine_regs[inst]); 507 508 return &aux_engine->base; 509 } 510 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 511 512 static const struct dce_i2c_registers i2c_hw_regs[] = { 513 i2c_inst_regs(1), 514 i2c_inst_regs(2), 515 i2c_inst_regs(3), 516 i2c_inst_regs(4), 517 i2c_inst_regs(5), 518 i2c_inst_regs(6), 519 }; 520 521 static const struct dce_i2c_shift i2c_shifts = { 522 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 523 }; 524 525 static const struct dce_i2c_mask i2c_masks = { 526 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 527 }; 528 529 struct dce_i2c_hw *dce80_i2c_hw_create( 530 struct dc_context *ctx, 531 uint32_t inst) 532 { 533 struct dce_i2c_hw *dce_i2c_hw = 534 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 535 536 if (!dce_i2c_hw) 537 return NULL; 538 539 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 540 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 541 542 return dce_i2c_hw; 543 } 544 545 struct dce_i2c_sw *dce80_i2c_sw_create( 546 struct dc_context *ctx) 547 { 548 struct dce_i2c_sw *dce_i2c_sw = 549 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 550 551 if (!dce_i2c_sw) 552 return NULL; 553 554 dce_i2c_sw_construct(dce_i2c_sw, ctx); 555 556 return dce_i2c_sw; 557 } 558 static struct stream_encoder *dce80_stream_encoder_create( 559 enum engine_id eng_id, 560 struct dc_context *ctx) 561 { 562 struct dce110_stream_encoder *enc110 = 563 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 564 565 if (!enc110) 566 return NULL; 567 568 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 569 &stream_enc_regs[eng_id], 570 &se_shift, &se_mask); 571 return &enc110->base; 572 } 573 574 #define SRII(reg_name, block, id)\ 575 .reg_name[id] = mm ## block ## id ## _ ## reg_name 576 577 static const struct dce_hwseq_registers hwseq_reg = { 578 HWSEQ_DCE8_REG_LIST() 579 }; 580 581 static const struct dce_hwseq_shift hwseq_shift = { 582 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 583 }; 584 585 static const struct dce_hwseq_mask hwseq_mask = { 586 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 587 }; 588 589 static struct dce_hwseq *dce80_hwseq_create( 590 struct dc_context *ctx) 591 { 592 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 593 594 if (hws) { 595 hws->ctx = ctx; 596 hws->regs = &hwseq_reg; 597 hws->shifts = &hwseq_shift; 598 hws->masks = &hwseq_mask; 599 } 600 return hws; 601 } 602 603 static const struct resource_create_funcs res_create_funcs = { 604 .read_dce_straps = read_dce_straps, 605 .create_audio = create_audio, 606 .create_stream_encoder = dce80_stream_encoder_create, 607 .create_hwseq = dce80_hwseq_create, 608 }; 609 610 #define mi_inst_regs(id) { \ 611 MI_DCE8_REG_LIST(id), \ 612 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 613 } 614 static const struct dce_mem_input_registers mi_regs[] = { 615 mi_inst_regs(0), 616 mi_inst_regs(1), 617 mi_inst_regs(2), 618 mi_inst_regs(3), 619 mi_inst_regs(4), 620 mi_inst_regs(5), 621 }; 622 623 static const struct dce_mem_input_shift mi_shifts = { 624 MI_DCE8_MASK_SH_LIST(__SHIFT), 625 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 626 }; 627 628 static const struct dce_mem_input_mask mi_masks = { 629 MI_DCE8_MASK_SH_LIST(_MASK), 630 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 631 }; 632 633 static struct mem_input *dce80_mem_input_create( 634 struct dc_context *ctx, 635 uint32_t inst) 636 { 637 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 638 GFP_KERNEL); 639 640 if (!dce_mi) { 641 BREAK_TO_DEBUGGER(); 642 return NULL; 643 } 644 645 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 646 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 647 return &dce_mi->base; 648 } 649 650 static void dce80_transform_destroy(struct transform **xfm) 651 { 652 kfree(TO_DCE_TRANSFORM(*xfm)); 653 *xfm = NULL; 654 } 655 656 static struct transform *dce80_transform_create( 657 struct dc_context *ctx, 658 uint32_t inst) 659 { 660 struct dce_transform *transform = 661 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 662 663 if (!transform) 664 return NULL; 665 666 dce_transform_construct(transform, ctx, inst, 667 &xfm_regs[inst], &xfm_shift, &xfm_mask); 668 transform->prescaler_on = false; 669 return &transform->base; 670 } 671 672 static const struct encoder_feature_support link_enc_feature = { 673 .max_hdmi_deep_color = COLOR_DEPTH_121212, 674 .max_hdmi_pixel_clock = 297000, 675 .flags.bits.IS_HBR2_CAPABLE = true, 676 .flags.bits.IS_TPS3_CAPABLE = true 677 }; 678 679 struct link_encoder *dce80_link_encoder_create( 680 const struct encoder_init_data *enc_init_data) 681 { 682 struct dce110_link_encoder *enc110 = 683 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 684 685 if (!enc110) 686 return NULL; 687 688 dce110_link_encoder_construct(enc110, 689 enc_init_data, 690 &link_enc_feature, 691 &link_enc_regs[enc_init_data->transmitter], 692 &link_enc_aux_regs[enc_init_data->channel - 1], 693 &link_enc_hpd_regs[enc_init_data->hpd_source]); 694 return &enc110->base; 695 } 696 697 struct clock_source *dce80_clock_source_create( 698 struct dc_context *ctx, 699 struct dc_bios *bios, 700 enum clock_source_id id, 701 const struct dce110_clk_src_regs *regs, 702 bool dp_clk_src) 703 { 704 struct dce110_clk_src *clk_src = 705 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 706 707 if (!clk_src) 708 return NULL; 709 710 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 711 regs, &cs_shift, &cs_mask)) { 712 clk_src->base.dp_clk_src = dp_clk_src; 713 return &clk_src->base; 714 } 715 716 BREAK_TO_DEBUGGER(); 717 return NULL; 718 } 719 720 void dce80_clock_source_destroy(struct clock_source **clk_src) 721 { 722 kfree(TO_DCE110_CLK_SRC(*clk_src)); 723 *clk_src = NULL; 724 } 725 726 static struct input_pixel_processor *dce80_ipp_create( 727 struct dc_context *ctx, uint32_t inst) 728 { 729 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 730 731 if (!ipp) { 732 BREAK_TO_DEBUGGER(); 733 return NULL; 734 } 735 736 dce_ipp_construct(ipp, ctx, inst, 737 &ipp_regs[inst], &ipp_shift, &ipp_mask); 738 return &ipp->base; 739 } 740 741 static void destruct(struct dce110_resource_pool *pool) 742 { 743 unsigned int i; 744 745 for (i = 0; i < pool->base.pipe_count; i++) { 746 if (pool->base.opps[i] != NULL) 747 dce110_opp_destroy(&pool->base.opps[i]); 748 749 if (pool->base.transforms[i] != NULL) 750 dce80_transform_destroy(&pool->base.transforms[i]); 751 752 if (pool->base.ipps[i] != NULL) 753 dce_ipp_destroy(&pool->base.ipps[i]); 754 755 if (pool->base.mis[i] != NULL) { 756 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 757 pool->base.mis[i] = NULL; 758 } 759 760 if (pool->base.timing_generators[i] != NULL) { 761 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 762 pool->base.timing_generators[i] = NULL; 763 } 764 } 765 766 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 767 if (pool->base.engines[i] != NULL) 768 dce110_engine_destroy(&pool->base.engines[i]); 769 if (pool->base.hw_i2cs[i] != NULL) { 770 kfree(pool->base.hw_i2cs[i]); 771 pool->base.hw_i2cs[i] = NULL; 772 } 773 if (pool->base.sw_i2cs[i] != NULL) { 774 kfree(pool->base.sw_i2cs[i]); 775 pool->base.sw_i2cs[i] = NULL; 776 } 777 } 778 779 for (i = 0; i < pool->base.stream_enc_count; i++) { 780 if (pool->base.stream_enc[i] != NULL) 781 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 782 } 783 784 for (i = 0; i < pool->base.clk_src_count; i++) { 785 if (pool->base.clock_sources[i] != NULL) { 786 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 787 } 788 } 789 790 if (pool->base.abm != NULL) 791 dce_abm_destroy(&pool->base.abm); 792 793 if (pool->base.dmcu != NULL) 794 dce_dmcu_destroy(&pool->base.dmcu); 795 796 if (pool->base.dp_clock_source != NULL) 797 dce80_clock_source_destroy(&pool->base.dp_clock_source); 798 799 for (i = 0; i < pool->base.audio_count; i++) { 800 if (pool->base.audios[i] != NULL) { 801 dce_aud_destroy(&pool->base.audios[i]); 802 } 803 } 804 805 if (pool->base.clk_mgr != NULL) 806 dce_clk_mgr_destroy(&pool->base.clk_mgr); 807 808 if (pool->base.irqs != NULL) { 809 dal_irq_service_destroy(&pool->base.irqs); 810 } 811 } 812 813 bool dce80_validate_bandwidth( 814 struct dc *dc, 815 struct dc_state *context, 816 bool fast_validate) 817 { 818 int i; 819 bool at_least_one_pipe = false; 820 821 for (i = 0; i < dc->res_pool->pipe_count; i++) { 822 if (context->res_ctx.pipe_ctx[i].stream) 823 at_least_one_pipe = true; 824 } 825 826 if (at_least_one_pipe) { 827 /* TODO implement when needed but for now hardcode max value*/ 828 context->bw_ctx.bw.dce.dispclk_khz = 681000; 829 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 830 } else { 831 context->bw_ctx.bw.dce.dispclk_khz = 0; 832 context->bw_ctx.bw.dce.yclk_khz = 0; 833 } 834 835 return true; 836 } 837 838 static bool dce80_validate_surface_sets( 839 struct dc_state *context) 840 { 841 int i; 842 843 for (i = 0; i < context->stream_count; i++) { 844 if (context->stream_status[i].plane_count == 0) 845 continue; 846 847 if (context->stream_status[i].plane_count > 1) 848 return false; 849 850 if (context->stream_status[i].plane_states[0]->format 851 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 852 return false; 853 } 854 855 return true; 856 } 857 858 enum dc_status dce80_validate_global( 859 struct dc *dc, 860 struct dc_state *context) 861 { 862 if (!dce80_validate_surface_sets(context)) 863 return DC_FAIL_SURFACE_VALIDATE; 864 865 return DC_OK; 866 } 867 868 static void dce80_destroy_resource_pool(struct resource_pool **pool) 869 { 870 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 871 872 destruct(dce110_pool); 873 kfree(dce110_pool); 874 *pool = NULL; 875 } 876 877 static const struct resource_funcs dce80_res_pool_funcs = { 878 .destroy = dce80_destroy_resource_pool, 879 .link_enc_create = dce80_link_encoder_create, 880 .validate_bandwidth = dce80_validate_bandwidth, 881 .validate_plane = dce100_validate_plane, 882 .add_stream_to_ctx = dce100_add_stream_to_ctx, 883 .validate_global = dce80_validate_global 884 }; 885 886 static bool dce80_construct( 887 uint8_t num_virtual_links, 888 struct dc *dc, 889 struct dce110_resource_pool *pool) 890 { 891 unsigned int i; 892 struct dc_context *ctx = dc->ctx; 893 struct dc_firmware_info info; 894 struct dc_bios *bp; 895 896 ctx->dc_bios->regs = &bios_regs; 897 898 pool->base.res_cap = &res_cap; 899 pool->base.funcs = &dce80_res_pool_funcs; 900 901 902 /************************************************* 903 * Resource + asic cap harcoding * 904 *************************************************/ 905 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 906 pool->base.pipe_count = res_cap.num_timing_generator; 907 pool->base.timing_generator_count = res_cap.num_timing_generator; 908 dc->caps.max_downscale_ratio = 200; 909 dc->caps.i2c_speed_in_khz = 40; 910 dc->caps.max_cursor_size = 128; 911 dc->caps.dual_link_dvi = true; 912 913 /************************************************* 914 * Create resources * 915 *************************************************/ 916 917 bp = ctx->dc_bios; 918 919 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 920 info.external_clock_source_frequency_for_dp != 0) { 921 pool->base.dp_clock_source = 922 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 923 924 pool->base.clock_sources[0] = 925 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 926 pool->base.clock_sources[1] = 927 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 928 pool->base.clock_sources[2] = 929 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 930 pool->base.clk_src_count = 3; 931 932 } else { 933 pool->base.dp_clock_source = 934 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 935 936 pool->base.clock_sources[0] = 937 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 938 pool->base.clock_sources[1] = 939 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 940 pool->base.clk_src_count = 2; 941 } 942 943 if (pool->base.dp_clock_source == NULL) { 944 dm_error("DC: failed to create dp clock source!\n"); 945 BREAK_TO_DEBUGGER(); 946 goto res_create_fail; 947 } 948 949 for (i = 0; i < pool->base.clk_src_count; i++) { 950 if (pool->base.clock_sources[i] == NULL) { 951 dm_error("DC: failed to create clock sources!\n"); 952 BREAK_TO_DEBUGGER(); 953 goto res_create_fail; 954 } 955 } 956 957 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 958 &disp_clk_regs, 959 &disp_clk_shift, 960 &disp_clk_mask); 961 if (pool->base.clk_mgr == NULL) { 962 dm_error("DC: failed to create display clock!\n"); 963 BREAK_TO_DEBUGGER(); 964 goto res_create_fail; 965 } 966 967 pool->base.dmcu = dce_dmcu_create(ctx, 968 &dmcu_regs, 969 &dmcu_shift, 970 &dmcu_mask); 971 if (pool->base.dmcu == NULL) { 972 dm_error("DC: failed to create dmcu!\n"); 973 BREAK_TO_DEBUGGER(); 974 goto res_create_fail; 975 } 976 977 pool->base.abm = dce_abm_create(ctx, 978 &abm_regs, 979 &abm_shift, 980 &abm_mask); 981 if (pool->base.abm == NULL) { 982 dm_error("DC: failed to create abm!\n"); 983 BREAK_TO_DEBUGGER(); 984 goto res_create_fail; 985 } 986 987 { 988 struct irq_service_init_data init_data; 989 init_data.ctx = dc->ctx; 990 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 991 if (!pool->base.irqs) 992 goto res_create_fail; 993 } 994 995 for (i = 0; i < pool->base.pipe_count; i++) { 996 pool->base.timing_generators[i] = dce80_timing_generator_create( 997 ctx, i, &dce80_tg_offsets[i]); 998 if (pool->base.timing_generators[i] == NULL) { 999 BREAK_TO_DEBUGGER(); 1000 dm_error("DC: failed to create tg!\n"); 1001 goto res_create_fail; 1002 } 1003 1004 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1005 if (pool->base.mis[i] == NULL) { 1006 BREAK_TO_DEBUGGER(); 1007 dm_error("DC: failed to create memory input!\n"); 1008 goto res_create_fail; 1009 } 1010 1011 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1012 if (pool->base.ipps[i] == NULL) { 1013 BREAK_TO_DEBUGGER(); 1014 dm_error("DC: failed to create input pixel processor!\n"); 1015 goto res_create_fail; 1016 } 1017 1018 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1019 if (pool->base.transforms[i] == NULL) { 1020 BREAK_TO_DEBUGGER(); 1021 dm_error("DC: failed to create transform!\n"); 1022 goto res_create_fail; 1023 } 1024 1025 pool->base.opps[i] = dce80_opp_create(ctx, i); 1026 if (pool->base.opps[i] == NULL) { 1027 BREAK_TO_DEBUGGER(); 1028 dm_error("DC: failed to create output pixel processor!\n"); 1029 goto res_create_fail; 1030 } 1031 } 1032 1033 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1034 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1035 if (pool->base.engines[i] == NULL) { 1036 BREAK_TO_DEBUGGER(); 1037 dm_error( 1038 "DC:failed to create aux engine!!\n"); 1039 goto res_create_fail; 1040 } 1041 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1042 if (pool->base.hw_i2cs[i] == NULL) { 1043 BREAK_TO_DEBUGGER(); 1044 dm_error( 1045 "DC:failed to create i2c engine!!\n"); 1046 goto res_create_fail; 1047 } 1048 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1049 if (pool->base.sw_i2cs[i] == NULL) { 1050 BREAK_TO_DEBUGGER(); 1051 dm_error( 1052 "DC:failed to create sw i2c!!\n"); 1053 goto res_create_fail; 1054 } 1055 } 1056 1057 dc->caps.max_planes = pool->base.pipe_count; 1058 1059 for (i = 0; i < dc->caps.max_planes; ++i) 1060 dc->caps.planes[i] = plane_cap; 1061 1062 dc->caps.disable_dp_clk_share = true; 1063 1064 if (!resource_construct(num_virtual_links, dc, &pool->base, 1065 &res_create_funcs)) 1066 goto res_create_fail; 1067 1068 /* Create hardware sequencer */ 1069 dce80_hw_sequencer_construct(dc); 1070 1071 return true; 1072 1073 res_create_fail: 1074 destruct(pool); 1075 return false; 1076 } 1077 1078 struct resource_pool *dce80_create_resource_pool( 1079 uint8_t num_virtual_links, 1080 struct dc *dc) 1081 { 1082 struct dce110_resource_pool *pool = 1083 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1084 1085 if (!pool) 1086 return NULL; 1087 1088 if (dce80_construct(num_virtual_links, dc, pool)) 1089 return &pool->base; 1090 1091 BREAK_TO_DEBUGGER(); 1092 return NULL; 1093 } 1094 1095 static bool dce81_construct( 1096 uint8_t num_virtual_links, 1097 struct dc *dc, 1098 struct dce110_resource_pool *pool) 1099 { 1100 unsigned int i; 1101 struct dc_context *ctx = dc->ctx; 1102 struct dc_firmware_info info; 1103 struct dc_bios *bp; 1104 1105 ctx->dc_bios->regs = &bios_regs; 1106 1107 pool->base.res_cap = &res_cap_81; 1108 pool->base.funcs = &dce80_res_pool_funcs; 1109 1110 1111 /************************************************* 1112 * Resource + asic cap harcoding * 1113 *************************************************/ 1114 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1115 pool->base.pipe_count = res_cap_81.num_timing_generator; 1116 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1117 dc->caps.max_downscale_ratio = 200; 1118 dc->caps.i2c_speed_in_khz = 40; 1119 dc->caps.max_cursor_size = 128; 1120 dc->caps.is_apu = true; 1121 1122 /************************************************* 1123 * Create resources * 1124 *************************************************/ 1125 1126 bp = ctx->dc_bios; 1127 1128 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1129 info.external_clock_source_frequency_for_dp != 0) { 1130 pool->base.dp_clock_source = 1131 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1132 1133 pool->base.clock_sources[0] = 1134 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1135 pool->base.clock_sources[1] = 1136 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1137 pool->base.clock_sources[2] = 1138 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1139 pool->base.clk_src_count = 3; 1140 1141 } else { 1142 pool->base.dp_clock_source = 1143 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1144 1145 pool->base.clock_sources[0] = 1146 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1147 pool->base.clock_sources[1] = 1148 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1149 pool->base.clk_src_count = 2; 1150 } 1151 1152 if (pool->base.dp_clock_source == NULL) { 1153 dm_error("DC: failed to create dp clock source!\n"); 1154 BREAK_TO_DEBUGGER(); 1155 goto res_create_fail; 1156 } 1157 1158 for (i = 0; i < pool->base.clk_src_count; i++) { 1159 if (pool->base.clock_sources[i] == NULL) { 1160 dm_error("DC: failed to create clock sources!\n"); 1161 BREAK_TO_DEBUGGER(); 1162 goto res_create_fail; 1163 } 1164 } 1165 1166 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 1167 &disp_clk_regs, 1168 &disp_clk_shift, 1169 &disp_clk_mask); 1170 if (pool->base.clk_mgr == NULL) { 1171 dm_error("DC: failed to create display clock!\n"); 1172 BREAK_TO_DEBUGGER(); 1173 goto res_create_fail; 1174 } 1175 1176 pool->base.dmcu = dce_dmcu_create(ctx, 1177 &dmcu_regs, 1178 &dmcu_shift, 1179 &dmcu_mask); 1180 if (pool->base.dmcu == NULL) { 1181 dm_error("DC: failed to create dmcu!\n"); 1182 BREAK_TO_DEBUGGER(); 1183 goto res_create_fail; 1184 } 1185 1186 pool->base.abm = dce_abm_create(ctx, 1187 &abm_regs, 1188 &abm_shift, 1189 &abm_mask); 1190 if (pool->base.abm == NULL) { 1191 dm_error("DC: failed to create abm!\n"); 1192 BREAK_TO_DEBUGGER(); 1193 goto res_create_fail; 1194 } 1195 1196 { 1197 struct irq_service_init_data init_data; 1198 init_data.ctx = dc->ctx; 1199 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1200 if (!pool->base.irqs) 1201 goto res_create_fail; 1202 } 1203 1204 for (i = 0; i < pool->base.pipe_count; i++) { 1205 pool->base.timing_generators[i] = dce80_timing_generator_create( 1206 ctx, i, &dce80_tg_offsets[i]); 1207 if (pool->base.timing_generators[i] == NULL) { 1208 BREAK_TO_DEBUGGER(); 1209 dm_error("DC: failed to create tg!\n"); 1210 goto res_create_fail; 1211 } 1212 1213 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1214 if (pool->base.mis[i] == NULL) { 1215 BREAK_TO_DEBUGGER(); 1216 dm_error("DC: failed to create memory input!\n"); 1217 goto res_create_fail; 1218 } 1219 1220 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1221 if (pool->base.ipps[i] == NULL) { 1222 BREAK_TO_DEBUGGER(); 1223 dm_error("DC: failed to create input pixel processor!\n"); 1224 goto res_create_fail; 1225 } 1226 1227 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1228 if (pool->base.transforms[i] == NULL) { 1229 BREAK_TO_DEBUGGER(); 1230 dm_error("DC: failed to create transform!\n"); 1231 goto res_create_fail; 1232 } 1233 1234 pool->base.opps[i] = dce80_opp_create(ctx, i); 1235 if (pool->base.opps[i] == NULL) { 1236 BREAK_TO_DEBUGGER(); 1237 dm_error("DC: failed to create output pixel processor!\n"); 1238 goto res_create_fail; 1239 } 1240 } 1241 1242 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1243 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1244 if (pool->base.engines[i] == NULL) { 1245 BREAK_TO_DEBUGGER(); 1246 dm_error( 1247 "DC:failed to create aux engine!!\n"); 1248 goto res_create_fail; 1249 } 1250 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1251 if (pool->base.hw_i2cs[i] == NULL) { 1252 BREAK_TO_DEBUGGER(); 1253 dm_error( 1254 "DC:failed to create i2c engine!!\n"); 1255 goto res_create_fail; 1256 } 1257 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1258 if (pool->base.sw_i2cs[i] == NULL) { 1259 BREAK_TO_DEBUGGER(); 1260 dm_error( 1261 "DC:failed to create sw i2c!!\n"); 1262 goto res_create_fail; 1263 } 1264 } 1265 1266 dc->caps.max_planes = pool->base.pipe_count; 1267 1268 for (i = 0; i < dc->caps.max_planes; ++i) 1269 dc->caps.planes[i] = plane_cap; 1270 1271 dc->caps.disable_dp_clk_share = true; 1272 1273 if (!resource_construct(num_virtual_links, dc, &pool->base, 1274 &res_create_funcs)) 1275 goto res_create_fail; 1276 1277 /* Create hardware sequencer */ 1278 dce80_hw_sequencer_construct(dc); 1279 1280 return true; 1281 1282 res_create_fail: 1283 destruct(pool); 1284 return false; 1285 } 1286 1287 struct resource_pool *dce81_create_resource_pool( 1288 uint8_t num_virtual_links, 1289 struct dc *dc) 1290 { 1291 struct dce110_resource_pool *pool = 1292 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1293 1294 if (!pool) 1295 return NULL; 1296 1297 if (dce81_construct(num_virtual_links, dc, pool)) 1298 return &pool->base; 1299 1300 BREAK_TO_DEBUGGER(); 1301 return NULL; 1302 } 1303 1304 static bool dce83_construct( 1305 uint8_t num_virtual_links, 1306 struct dc *dc, 1307 struct dce110_resource_pool *pool) 1308 { 1309 unsigned int i; 1310 struct dc_context *ctx = dc->ctx; 1311 struct dc_firmware_info info; 1312 struct dc_bios *bp; 1313 1314 ctx->dc_bios->regs = &bios_regs; 1315 1316 pool->base.res_cap = &res_cap_83; 1317 pool->base.funcs = &dce80_res_pool_funcs; 1318 1319 1320 /************************************************* 1321 * Resource + asic cap harcoding * 1322 *************************************************/ 1323 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1324 pool->base.pipe_count = res_cap_83.num_timing_generator; 1325 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1326 dc->caps.max_downscale_ratio = 200; 1327 dc->caps.i2c_speed_in_khz = 40; 1328 dc->caps.max_cursor_size = 128; 1329 dc->caps.is_apu = true; 1330 1331 /************************************************* 1332 * Create resources * 1333 *************************************************/ 1334 1335 bp = ctx->dc_bios; 1336 1337 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1338 info.external_clock_source_frequency_for_dp != 0) { 1339 pool->base.dp_clock_source = 1340 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1341 1342 pool->base.clock_sources[0] = 1343 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1344 pool->base.clock_sources[1] = 1345 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1346 pool->base.clk_src_count = 2; 1347 1348 } else { 1349 pool->base.dp_clock_source = 1350 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1351 1352 pool->base.clock_sources[0] = 1353 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1354 pool->base.clk_src_count = 1; 1355 } 1356 1357 if (pool->base.dp_clock_source == NULL) { 1358 dm_error("DC: failed to create dp clock source!\n"); 1359 BREAK_TO_DEBUGGER(); 1360 goto res_create_fail; 1361 } 1362 1363 for (i = 0; i < pool->base.clk_src_count; i++) { 1364 if (pool->base.clock_sources[i] == NULL) { 1365 dm_error("DC: failed to create clock sources!\n"); 1366 BREAK_TO_DEBUGGER(); 1367 goto res_create_fail; 1368 } 1369 } 1370 1371 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 1372 &disp_clk_regs, 1373 &disp_clk_shift, 1374 &disp_clk_mask); 1375 if (pool->base.clk_mgr == NULL) { 1376 dm_error("DC: failed to create display clock!\n"); 1377 BREAK_TO_DEBUGGER(); 1378 goto res_create_fail; 1379 } 1380 1381 pool->base.dmcu = dce_dmcu_create(ctx, 1382 &dmcu_regs, 1383 &dmcu_shift, 1384 &dmcu_mask); 1385 if (pool->base.dmcu == NULL) { 1386 dm_error("DC: failed to create dmcu!\n"); 1387 BREAK_TO_DEBUGGER(); 1388 goto res_create_fail; 1389 } 1390 1391 pool->base.abm = dce_abm_create(ctx, 1392 &abm_regs, 1393 &abm_shift, 1394 &abm_mask); 1395 if (pool->base.abm == NULL) { 1396 dm_error("DC: failed to create abm!\n"); 1397 BREAK_TO_DEBUGGER(); 1398 goto res_create_fail; 1399 } 1400 1401 { 1402 struct irq_service_init_data init_data; 1403 init_data.ctx = dc->ctx; 1404 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1405 if (!pool->base.irqs) 1406 goto res_create_fail; 1407 } 1408 1409 for (i = 0; i < pool->base.pipe_count; i++) { 1410 pool->base.timing_generators[i] = dce80_timing_generator_create( 1411 ctx, i, &dce80_tg_offsets[i]); 1412 if (pool->base.timing_generators[i] == NULL) { 1413 BREAK_TO_DEBUGGER(); 1414 dm_error("DC: failed to create tg!\n"); 1415 goto res_create_fail; 1416 } 1417 1418 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1419 if (pool->base.mis[i] == NULL) { 1420 BREAK_TO_DEBUGGER(); 1421 dm_error("DC: failed to create memory input!\n"); 1422 goto res_create_fail; 1423 } 1424 1425 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1426 if (pool->base.ipps[i] == NULL) { 1427 BREAK_TO_DEBUGGER(); 1428 dm_error("DC: failed to create input pixel processor!\n"); 1429 goto res_create_fail; 1430 } 1431 1432 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1433 if (pool->base.transforms[i] == NULL) { 1434 BREAK_TO_DEBUGGER(); 1435 dm_error("DC: failed to create transform!\n"); 1436 goto res_create_fail; 1437 } 1438 1439 pool->base.opps[i] = dce80_opp_create(ctx, i); 1440 if (pool->base.opps[i] == NULL) { 1441 BREAK_TO_DEBUGGER(); 1442 dm_error("DC: failed to create output pixel processor!\n"); 1443 goto res_create_fail; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1448 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1449 if (pool->base.engines[i] == NULL) { 1450 BREAK_TO_DEBUGGER(); 1451 dm_error( 1452 "DC:failed to create aux engine!!\n"); 1453 goto res_create_fail; 1454 } 1455 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1456 if (pool->base.hw_i2cs[i] == NULL) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error( 1459 "DC:failed to create i2c engine!!\n"); 1460 goto res_create_fail; 1461 } 1462 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1463 if (pool->base.sw_i2cs[i] == NULL) { 1464 BREAK_TO_DEBUGGER(); 1465 dm_error( 1466 "DC:failed to create sw i2c!!\n"); 1467 goto res_create_fail; 1468 } 1469 } 1470 1471 dc->caps.max_planes = pool->base.pipe_count; 1472 1473 for (i = 0; i < dc->caps.max_planes; ++i) 1474 dc->caps.planes[i] = plane_cap; 1475 1476 dc->caps.disable_dp_clk_share = true; 1477 1478 if (!resource_construct(num_virtual_links, dc, &pool->base, 1479 &res_create_funcs)) 1480 goto res_create_fail; 1481 1482 /* Create hardware sequencer */ 1483 dce80_hw_sequencer_construct(dc); 1484 1485 return true; 1486 1487 res_create_fail: 1488 destruct(pool); 1489 return false; 1490 } 1491 1492 struct resource_pool *dce83_create_resource_pool( 1493 uint8_t num_virtual_links, 1494 struct dc *dc) 1495 { 1496 struct dce110_resource_pool *pool = 1497 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1498 1499 if (!pool) 1500 return NULL; 1501 1502 if (dce83_construct(num_virtual_links, dc, pool)) 1503 return &pool->base; 1504 1505 BREAK_TO_DEBUGGER(); 1506 return NULL; 1507 } 1508