1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 /* TODO remove this include */ 57 58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 59 #include "gmc/gmc_7_1_d.h" 60 #include "gmc/gmc_7_1_sh_mask.h" 61 #endif 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 72 #endif 73 74 75 #ifndef mmBIOS_SCRATCH_2 76 #define mmBIOS_SCRATCH_2 0x05CB 77 #define mmBIOS_SCRATCH_6 0x05CF 78 #endif 79 80 #ifndef mmDP_DPHY_FAST_TRAINING 81 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 82 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 83 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 84 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 85 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 86 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 87 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 88 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 89 #endif 90 91 92 #ifndef mmHPD_DC_HPD_CONTROL 93 #define mmHPD_DC_HPD_CONTROL 0x189A 94 #define mmHPD0_DC_HPD_CONTROL 0x189A 95 #define mmHPD1_DC_HPD_CONTROL 0x18A2 96 #define mmHPD2_DC_HPD_CONTROL 0x18AA 97 #define mmHPD3_DC_HPD_CONTROL 0x18B2 98 #define mmHPD4_DC_HPD_CONTROL 0x18BA 99 #define mmHPD5_DC_HPD_CONTROL 0x18C2 100 #endif 101 102 #define DCE11_DIG_FE_CNTL 0x4a00 103 #define DCE11_DIG_BE_CNTL 0x4a47 104 #define DCE11_DP_SEC 0x4ac3 105 106 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 107 { 108 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 109 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 110 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 111 - mmDPG_WATERMARK_MASK_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 115 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 116 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 117 - mmDPG_WATERMARK_MASK_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 122 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 123 - mmDPG_WATERMARK_MASK_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 128 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 129 - mmDPG_WATERMARK_MASK_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 135 - mmDPG_WATERMARK_MASK_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 141 - mmDPG_WATERMARK_MASK_CONTROL), 142 } 143 }; 144 145 /* set register offset */ 146 #define SR(reg_name)\ 147 .reg_name = mm ## reg_name 148 149 /* set register offset with instance */ 150 #define SRI(reg_name, block, id)\ 151 .reg_name = mm ## block ## id ## _ ## reg_name 152 153 154 static const struct dce_disp_clk_registers disp_clk_regs = { 155 CLK_COMMON_REG_LIST_DCE_BASE() 156 }; 157 158 static const struct dce_disp_clk_shift disp_clk_shift = { 159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 160 }; 161 162 static const struct dce_disp_clk_mask disp_clk_mask = { 163 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 164 }; 165 166 #define ipp_regs(id)\ 167 [id] = {\ 168 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 169 } 170 171 static const struct dce_ipp_registers ipp_regs[] = { 172 ipp_regs(0), 173 ipp_regs(1), 174 ipp_regs(2), 175 ipp_regs(3), 176 ipp_regs(4), 177 ipp_regs(5) 178 }; 179 180 static const struct dce_ipp_shift ipp_shift = { 181 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 182 }; 183 184 static const struct dce_ipp_mask ipp_mask = { 185 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 186 }; 187 188 #define transform_regs(id)\ 189 [id] = {\ 190 XFM_COMMON_REG_LIST_DCE80(id)\ 191 } 192 193 static const struct dce_transform_registers xfm_regs[] = { 194 transform_regs(0), 195 transform_regs(1), 196 transform_regs(2), 197 transform_regs(3), 198 transform_regs(4), 199 transform_regs(5) 200 }; 201 202 static const struct dce_transform_shift xfm_shift = { 203 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 204 }; 205 206 static const struct dce_transform_mask xfm_mask = { 207 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 208 }; 209 210 #define aux_regs(id)\ 211 [id] = {\ 212 AUX_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 216 aux_regs(0), 217 aux_regs(1), 218 aux_regs(2), 219 aux_regs(3), 220 aux_regs(4), 221 aux_regs(5) 222 }; 223 224 #define hpd_regs(id)\ 225 [id] = {\ 226 HPD_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 230 hpd_regs(0), 231 hpd_regs(1), 232 hpd_regs(2), 233 hpd_regs(3), 234 hpd_regs(4), 235 hpd_regs(5) 236 }; 237 238 #define link_regs(id)\ 239 [id] = {\ 240 LE_DCE80_REG_LIST(id)\ 241 } 242 243 static const struct dce110_link_enc_registers link_enc_regs[] = { 244 link_regs(0), 245 link_regs(1), 246 link_regs(2), 247 link_regs(3), 248 link_regs(4), 249 link_regs(5), 250 link_regs(6), 251 }; 252 253 #define stream_enc_regs(id)\ 254 [id] = {\ 255 SE_COMMON_REG_LIST_DCE_BASE(id),\ 256 .AFMT_CNTL = 0,\ 257 } 258 259 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 260 stream_enc_regs(0), 261 stream_enc_regs(1), 262 stream_enc_regs(2), 263 stream_enc_regs(3), 264 stream_enc_regs(4), 265 stream_enc_regs(5), 266 stream_enc_regs(6) 267 }; 268 269 static const struct dce_stream_encoder_shift se_shift = { 270 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 271 }; 272 273 static const struct dce_stream_encoder_mask se_mask = { 274 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 275 }; 276 277 #define opp_regs(id)\ 278 [id] = {\ 279 OPP_DCE_80_REG_LIST(id),\ 280 } 281 282 static const struct dce_opp_registers opp_regs[] = { 283 opp_regs(0), 284 opp_regs(1), 285 opp_regs(2), 286 opp_regs(3), 287 opp_regs(4), 288 opp_regs(5) 289 }; 290 291 static const struct dce_opp_shift opp_shift = { 292 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 293 }; 294 295 static const struct dce_opp_mask opp_mask = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 297 }; 298 299 #define audio_regs(id)\ 300 [id] = {\ 301 AUD_COMMON_REG_LIST(id)\ 302 } 303 304 static const struct dce_audio_registers audio_regs[] = { 305 audio_regs(0), 306 audio_regs(1), 307 audio_regs(2), 308 audio_regs(3), 309 audio_regs(4), 310 audio_regs(5), 311 audio_regs(6), 312 }; 313 314 static const struct dce_audio_shift audio_shift = { 315 AUD_COMMON_MASK_SH_LIST(__SHIFT) 316 }; 317 318 static const struct dce_aduio_mask audio_mask = { 319 AUD_COMMON_MASK_SH_LIST(_MASK) 320 }; 321 322 #define clk_src_regs(id)\ 323 [id] = {\ 324 CS_COMMON_REG_LIST_DCE_80(id),\ 325 } 326 327 328 static const struct dce110_clk_src_regs clk_src_regs[] = { 329 clk_src_regs(0), 330 clk_src_regs(1), 331 clk_src_regs(2) 332 }; 333 334 static const struct dce110_clk_src_shift cs_shift = { 335 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 336 }; 337 338 static const struct dce110_clk_src_mask cs_mask = { 339 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 340 }; 341 342 static const struct bios_registers bios_regs = { 343 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 344 }; 345 346 static const struct resource_caps res_cap = { 347 .num_timing_generator = 6, 348 .num_audio = 6, 349 .num_stream_encoder = 6, 350 .num_pll = 3, 351 }; 352 353 static const struct resource_caps res_cap_81 = { 354 .num_timing_generator = 4, 355 .num_audio = 7, 356 .num_stream_encoder = 7, 357 .num_pll = 3, 358 }; 359 360 static const struct resource_caps res_cap_83 = { 361 .num_timing_generator = 2, 362 .num_audio = 6, 363 .num_stream_encoder = 6, 364 .num_pll = 2, 365 }; 366 367 #define CTX ctx 368 #define REG(reg) mm ## reg 369 370 #ifndef mmCC_DC_HDMI_STRAPS 371 #define mmCC_DC_HDMI_STRAPS 0x1918 372 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 373 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 374 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 375 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 376 #endif 377 378 static void read_dce_straps( 379 struct dc_context *ctx, 380 struct resource_straps *straps) 381 { 382 REG_GET_2(CC_DC_HDMI_STRAPS, 383 HDMI_DISABLE, &straps->hdmi_disable, 384 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 385 386 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 387 } 388 389 static struct audio *create_audio( 390 struct dc_context *ctx, unsigned int inst) 391 { 392 return dce_audio_create(ctx, inst, 393 &audio_regs[inst], &audio_shift, &audio_mask); 394 } 395 396 static struct timing_generator *dce80_timing_generator_create( 397 struct dc_context *ctx, 398 uint32_t instance, 399 const struct dce110_timing_generator_offsets *offsets) 400 { 401 struct dce110_timing_generator *tg110 = 402 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 403 404 if (!tg110) 405 return NULL; 406 407 if (dce80_timing_generator_construct(tg110, ctx, instance, offsets)) 408 return &tg110->base; 409 410 BREAK_TO_DEBUGGER(); 411 kfree(tg110); 412 return NULL; 413 } 414 415 static struct output_pixel_processor *dce80_opp_create( 416 struct dc_context *ctx, 417 uint32_t inst) 418 { 419 struct dce110_opp *opp = 420 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 421 422 if (!opp) 423 return NULL; 424 425 if (dce110_opp_construct(opp, 426 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 427 return &opp->base; 428 429 BREAK_TO_DEBUGGER(); 430 kfree(opp); 431 return NULL; 432 } 433 434 static struct stream_encoder *dce80_stream_encoder_create( 435 enum engine_id eng_id, 436 struct dc_context *ctx) 437 { 438 struct dce110_stream_encoder *enc110 = 439 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 440 441 if (!enc110) 442 return NULL; 443 444 if (dce110_stream_encoder_construct( 445 enc110, ctx, ctx->dc_bios, eng_id, 446 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 447 return &enc110->base; 448 449 BREAK_TO_DEBUGGER(); 450 kfree(enc110); 451 return NULL; 452 } 453 454 #define SRII(reg_name, block, id)\ 455 .reg_name[id] = mm ## block ## id ## _ ## reg_name 456 457 static const struct dce_hwseq_registers hwseq_reg = { 458 HWSEQ_DCE8_REG_LIST() 459 }; 460 461 static const struct dce_hwseq_shift hwseq_shift = { 462 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 463 }; 464 465 static const struct dce_hwseq_mask hwseq_mask = { 466 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 467 }; 468 469 static struct dce_hwseq *dce80_hwseq_create( 470 struct dc_context *ctx) 471 { 472 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 473 474 if (hws) { 475 hws->ctx = ctx; 476 hws->regs = &hwseq_reg; 477 hws->shifts = &hwseq_shift; 478 hws->masks = &hwseq_mask; 479 } 480 return hws; 481 } 482 483 static const struct resource_create_funcs res_create_funcs = { 484 .read_dce_straps = read_dce_straps, 485 .create_audio = create_audio, 486 .create_stream_encoder = dce80_stream_encoder_create, 487 .create_hwseq = dce80_hwseq_create, 488 }; 489 490 #define mi_inst_regs(id) { \ 491 MI_DCE8_REG_LIST(id), \ 492 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 493 } 494 static const struct dce_mem_input_registers mi_regs[] = { 495 mi_inst_regs(0), 496 mi_inst_regs(1), 497 mi_inst_regs(2), 498 mi_inst_regs(3), 499 mi_inst_regs(4), 500 mi_inst_regs(5), 501 }; 502 503 static const struct dce_mem_input_shift mi_shifts = { 504 MI_DCE8_MASK_SH_LIST(__SHIFT), 505 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 506 }; 507 508 static const struct dce_mem_input_mask mi_masks = { 509 MI_DCE8_MASK_SH_LIST(_MASK), 510 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 511 }; 512 513 static struct mem_input *dce80_mem_input_create( 514 struct dc_context *ctx, 515 uint32_t inst) 516 { 517 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 518 GFP_KERNEL); 519 520 if (!dce_mi) { 521 BREAK_TO_DEBUGGER(); 522 return NULL; 523 } 524 525 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 526 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 527 return &dce_mi->base; 528 } 529 530 static void dce80_transform_destroy(struct transform **xfm) 531 { 532 kfree(TO_DCE_TRANSFORM(*xfm)); 533 *xfm = NULL; 534 } 535 536 static struct transform *dce80_transform_create( 537 struct dc_context *ctx, 538 uint32_t inst) 539 { 540 struct dce_transform *transform = 541 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 542 543 if (!transform) 544 return NULL; 545 546 if (dce_transform_construct(transform, ctx, inst, 547 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 548 transform->prescaler_on = false; 549 return &transform->base; 550 } 551 552 BREAK_TO_DEBUGGER(); 553 kfree(transform); 554 return NULL; 555 } 556 557 static const struct encoder_feature_support link_enc_feature = { 558 .max_hdmi_deep_color = COLOR_DEPTH_121212, 559 .max_hdmi_pixel_clock = 297000, 560 .flags.bits.IS_HBR2_CAPABLE = true, 561 .flags.bits.IS_TPS3_CAPABLE = true, 562 .flags.bits.IS_YCBCR_CAPABLE = true 563 }; 564 565 struct link_encoder *dce80_link_encoder_create( 566 const struct encoder_init_data *enc_init_data) 567 { 568 struct dce110_link_encoder *enc110 = 569 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 570 571 if (!enc110) 572 return NULL; 573 574 if (dce110_link_encoder_construct( 575 enc110, 576 enc_init_data, 577 &link_enc_feature, 578 &link_enc_regs[enc_init_data->transmitter], 579 &link_enc_aux_regs[enc_init_data->channel - 1], 580 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 581 582 return &enc110->base; 583 } 584 585 BREAK_TO_DEBUGGER(); 586 kfree(enc110); 587 return NULL; 588 } 589 590 struct clock_source *dce80_clock_source_create( 591 struct dc_context *ctx, 592 struct dc_bios *bios, 593 enum clock_source_id id, 594 const struct dce110_clk_src_regs *regs, 595 bool dp_clk_src) 596 { 597 struct dce110_clk_src *clk_src = 598 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 599 600 if (!clk_src) 601 return NULL; 602 603 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 604 regs, &cs_shift, &cs_mask)) { 605 clk_src->base.dp_clk_src = dp_clk_src; 606 return &clk_src->base; 607 } 608 609 BREAK_TO_DEBUGGER(); 610 return NULL; 611 } 612 613 void dce80_clock_source_destroy(struct clock_source **clk_src) 614 { 615 kfree(TO_DCE110_CLK_SRC(*clk_src)); 616 *clk_src = NULL; 617 } 618 619 static struct input_pixel_processor *dce80_ipp_create( 620 struct dc_context *ctx, uint32_t inst) 621 { 622 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 623 624 if (!ipp) { 625 BREAK_TO_DEBUGGER(); 626 return NULL; 627 } 628 629 dce_ipp_construct(ipp, ctx, inst, 630 &ipp_regs[inst], &ipp_shift, &ipp_mask); 631 return &ipp->base; 632 } 633 634 static void destruct(struct dce110_resource_pool *pool) 635 { 636 unsigned int i; 637 638 for (i = 0; i < pool->base.pipe_count; i++) { 639 if (pool->base.opps[i] != NULL) 640 dce110_opp_destroy(&pool->base.opps[i]); 641 642 if (pool->base.transforms[i] != NULL) 643 dce80_transform_destroy(&pool->base.transforms[i]); 644 645 if (pool->base.ipps[i] != NULL) 646 dce_ipp_destroy(&pool->base.ipps[i]); 647 648 if (pool->base.mis[i] != NULL) { 649 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 650 pool->base.mis[i] = NULL; 651 } 652 653 if (pool->base.timing_generators[i] != NULL) { 654 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 655 pool->base.timing_generators[i] = NULL; 656 } 657 } 658 659 for (i = 0; i < pool->base.stream_enc_count; i++) { 660 if (pool->base.stream_enc[i] != NULL) 661 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 662 } 663 664 for (i = 0; i < pool->base.clk_src_count; i++) { 665 if (pool->base.clock_sources[i] != NULL) { 666 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 667 } 668 } 669 670 if (pool->base.dp_clock_source != NULL) 671 dce80_clock_source_destroy(&pool->base.dp_clock_source); 672 673 for (i = 0; i < pool->base.audio_count; i++) { 674 if (pool->base.audios[i] != NULL) { 675 dce_aud_destroy(&pool->base.audios[i]); 676 } 677 } 678 679 if (pool->base.display_clock != NULL) 680 dce_disp_clk_destroy(&pool->base.display_clock); 681 682 if (pool->base.irqs != NULL) { 683 dal_irq_service_destroy(&pool->base.irqs); 684 } 685 } 686 687 static enum dc_status build_mapped_resource( 688 const struct dc *dc, 689 struct dc_state *context, 690 struct dc_stream_state *stream) 691 { 692 enum dc_status status = DC_OK; 693 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 694 695 if (!pipe_ctx) 696 return DC_ERROR_UNEXPECTED; 697 698 status = dce110_resource_build_pipe_hw_param(pipe_ctx); 699 700 if (status != DC_OK) 701 return status; 702 703 resource_build_info_frame(pipe_ctx); 704 705 return DC_OK; 706 } 707 708 bool dce80_validate_bandwidth( 709 struct dc *dc, 710 struct dc_state *context) 711 { 712 /* TODO implement when needed but for now hardcode max value*/ 713 context->bw.dce.dispclk_khz = 681000; 714 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 715 716 return true; 717 } 718 719 static bool dce80_validate_surface_sets( 720 struct dc_state *context) 721 { 722 int i; 723 724 for (i = 0; i < context->stream_count; i++) { 725 if (context->stream_status[i].plane_count == 0) 726 continue; 727 728 if (context->stream_status[i].plane_count > 1) 729 return false; 730 731 if (context->stream_status[i].plane_states[0]->format 732 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 733 return false; 734 } 735 736 return true; 737 } 738 739 enum dc_status dce80_validate_global( 740 struct dc *dc, 741 struct dc_state *context) 742 { 743 if (!dce80_validate_surface_sets(context)) 744 return DC_FAIL_SURFACE_VALIDATE; 745 746 return DC_OK; 747 } 748 749 enum dc_status dce80_validate_guaranteed( 750 struct dc *dc, 751 struct dc_stream_state *dc_stream, 752 struct dc_state *context) 753 { 754 enum dc_status result = DC_ERROR_UNEXPECTED; 755 756 context->streams[0] = dc_stream; 757 dc_stream_retain(context->streams[0]); 758 context->stream_count++; 759 760 result = resource_map_pool_resources(dc, context, dc_stream); 761 762 if (result == DC_OK) 763 result = resource_map_clock_resources(dc, context, dc_stream); 764 765 if (result == DC_OK) 766 result = build_mapped_resource(dc, context, dc_stream); 767 768 if (result == DC_OK) { 769 validate_guaranteed_copy_streams( 770 context, dc->caps.max_streams); 771 result = resource_build_scaling_params_for_context(dc, context); 772 } 773 774 if (result == DC_OK) 775 result = dce80_validate_bandwidth(dc, context); 776 777 return result; 778 } 779 780 static void dce80_destroy_resource_pool(struct resource_pool **pool) 781 { 782 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 783 784 destruct(dce110_pool); 785 kfree(dce110_pool); 786 *pool = NULL; 787 } 788 789 static const struct resource_funcs dce80_res_pool_funcs = { 790 .destroy = dce80_destroy_resource_pool, 791 .link_enc_create = dce80_link_encoder_create, 792 .validate_guaranteed = dce80_validate_guaranteed, 793 .validate_bandwidth = dce80_validate_bandwidth, 794 .validate_plane = dce100_validate_plane, 795 .add_stream_to_ctx = dce100_add_stream_to_ctx, 796 .validate_global = dce80_validate_global 797 }; 798 799 static bool dce80_construct( 800 uint8_t num_virtual_links, 801 struct dc *dc, 802 struct dce110_resource_pool *pool) 803 { 804 unsigned int i; 805 struct dc_context *ctx = dc->ctx; 806 struct dc_firmware_info info; 807 struct dc_bios *bp; 808 struct dm_pp_static_clock_info static_clk_info = {0}; 809 810 ctx->dc_bios->regs = &bios_regs; 811 812 pool->base.res_cap = &res_cap; 813 pool->base.funcs = &dce80_res_pool_funcs; 814 815 816 /************************************************* 817 * Resource + asic cap harcoding * 818 *************************************************/ 819 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 820 pool->base.pipe_count = res_cap.num_timing_generator; 821 dc->caps.max_downscale_ratio = 200; 822 dc->caps.i2c_speed_in_khz = 40; 823 dc->caps.max_cursor_size = 128; 824 825 /************************************************* 826 * Create resources * 827 *************************************************/ 828 829 bp = ctx->dc_bios; 830 831 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 832 info.external_clock_source_frequency_for_dp != 0) { 833 pool->base.dp_clock_source = 834 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 835 836 pool->base.clock_sources[0] = 837 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 838 pool->base.clock_sources[1] = 839 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 840 pool->base.clock_sources[2] = 841 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 842 pool->base.clk_src_count = 3; 843 844 } else { 845 pool->base.dp_clock_source = 846 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 847 848 pool->base.clock_sources[0] = 849 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 850 pool->base.clock_sources[1] = 851 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 852 pool->base.clk_src_count = 2; 853 } 854 855 if (pool->base.dp_clock_source == NULL) { 856 dm_error("DC: failed to create dp clock source!\n"); 857 BREAK_TO_DEBUGGER(); 858 goto res_create_fail; 859 } 860 861 for (i = 0; i < pool->base.clk_src_count; i++) { 862 if (pool->base.clock_sources[i] == NULL) { 863 dm_error("DC: failed to create clock sources!\n"); 864 BREAK_TO_DEBUGGER(); 865 goto res_create_fail; 866 } 867 } 868 869 pool->base.display_clock = dce_disp_clk_create(ctx, 870 &disp_clk_regs, 871 &disp_clk_shift, 872 &disp_clk_mask); 873 if (pool->base.display_clock == NULL) { 874 dm_error("DC: failed to create display clock!\n"); 875 BREAK_TO_DEBUGGER(); 876 goto res_create_fail; 877 } 878 879 880 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 881 pool->base.display_clock->max_clks_state = 882 static_clk_info.max_clocks_state; 883 884 { 885 struct irq_service_init_data init_data; 886 init_data.ctx = dc->ctx; 887 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 888 if (!pool->base.irqs) 889 goto res_create_fail; 890 } 891 892 for (i = 0; i < pool->base.pipe_count; i++) { 893 pool->base.timing_generators[i] = dce80_timing_generator_create( 894 ctx, i, &dce80_tg_offsets[i]); 895 if (pool->base.timing_generators[i] == NULL) { 896 BREAK_TO_DEBUGGER(); 897 dm_error("DC: failed to create tg!\n"); 898 goto res_create_fail; 899 } 900 901 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 902 if (pool->base.mis[i] == NULL) { 903 BREAK_TO_DEBUGGER(); 904 dm_error("DC: failed to create memory input!\n"); 905 goto res_create_fail; 906 } 907 908 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 909 if (pool->base.ipps[i] == NULL) { 910 BREAK_TO_DEBUGGER(); 911 dm_error("DC: failed to create input pixel processor!\n"); 912 goto res_create_fail; 913 } 914 915 pool->base.transforms[i] = dce80_transform_create(ctx, i); 916 if (pool->base.transforms[i] == NULL) { 917 BREAK_TO_DEBUGGER(); 918 dm_error("DC: failed to create transform!\n"); 919 goto res_create_fail; 920 } 921 922 pool->base.opps[i] = dce80_opp_create(ctx, i); 923 if (pool->base.opps[i] == NULL) { 924 BREAK_TO_DEBUGGER(); 925 dm_error("DC: failed to create output pixel processor!\n"); 926 goto res_create_fail; 927 } 928 } 929 930 dc->caps.max_planes = pool->base.pipe_count; 931 932 if (!resource_construct(num_virtual_links, dc, &pool->base, 933 &res_create_funcs)) 934 goto res_create_fail; 935 936 /* Create hardware sequencer */ 937 if (!dce80_hw_sequencer_construct(dc)) 938 goto res_create_fail; 939 940 return true; 941 942 res_create_fail: 943 destruct(pool); 944 return false; 945 } 946 947 struct resource_pool *dce80_create_resource_pool( 948 uint8_t num_virtual_links, 949 struct dc *dc) 950 { 951 struct dce110_resource_pool *pool = 952 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 953 954 if (!pool) 955 return NULL; 956 957 if (dce80_construct(num_virtual_links, dc, pool)) 958 return &pool->base; 959 960 BREAK_TO_DEBUGGER(); 961 return NULL; 962 } 963 964 static bool dce81_construct( 965 uint8_t num_virtual_links, 966 struct dc *dc, 967 struct dce110_resource_pool *pool) 968 { 969 unsigned int i; 970 struct dc_context *ctx = dc->ctx; 971 struct dc_firmware_info info; 972 struct dc_bios *bp; 973 struct dm_pp_static_clock_info static_clk_info = {0}; 974 975 ctx->dc_bios->regs = &bios_regs; 976 977 pool->base.res_cap = &res_cap_81; 978 pool->base.funcs = &dce80_res_pool_funcs; 979 980 981 /************************************************* 982 * Resource + asic cap harcoding * 983 *************************************************/ 984 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 985 pool->base.pipe_count = res_cap_81.num_timing_generator; 986 dc->caps.max_downscale_ratio = 200; 987 dc->caps.i2c_speed_in_khz = 40; 988 dc->caps.max_cursor_size = 128; 989 990 /************************************************* 991 * Create resources * 992 *************************************************/ 993 994 bp = ctx->dc_bios; 995 996 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 997 info.external_clock_source_frequency_for_dp != 0) { 998 pool->base.dp_clock_source = 999 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1000 1001 pool->base.clock_sources[0] = 1002 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1003 pool->base.clock_sources[1] = 1004 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1005 pool->base.clock_sources[2] = 1006 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1007 pool->base.clk_src_count = 3; 1008 1009 } else { 1010 pool->base.dp_clock_source = 1011 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1012 1013 pool->base.clock_sources[0] = 1014 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1015 pool->base.clock_sources[1] = 1016 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1017 pool->base.clk_src_count = 2; 1018 } 1019 1020 if (pool->base.dp_clock_source == NULL) { 1021 dm_error("DC: failed to create dp clock source!\n"); 1022 BREAK_TO_DEBUGGER(); 1023 goto res_create_fail; 1024 } 1025 1026 for (i = 0; i < pool->base.clk_src_count; i++) { 1027 if (pool->base.clock_sources[i] == NULL) { 1028 dm_error("DC: failed to create clock sources!\n"); 1029 BREAK_TO_DEBUGGER(); 1030 goto res_create_fail; 1031 } 1032 } 1033 1034 pool->base.display_clock = dce_disp_clk_create(ctx, 1035 &disp_clk_regs, 1036 &disp_clk_shift, 1037 &disp_clk_mask); 1038 if (pool->base.display_clock == NULL) { 1039 dm_error("DC: failed to create display clock!\n"); 1040 BREAK_TO_DEBUGGER(); 1041 goto res_create_fail; 1042 } 1043 1044 1045 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1046 pool->base.display_clock->max_clks_state = 1047 static_clk_info.max_clocks_state; 1048 1049 { 1050 struct irq_service_init_data init_data; 1051 init_data.ctx = dc->ctx; 1052 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1053 if (!pool->base.irqs) 1054 goto res_create_fail; 1055 } 1056 1057 for (i = 0; i < pool->base.pipe_count; i++) { 1058 pool->base.timing_generators[i] = dce80_timing_generator_create( 1059 ctx, i, &dce80_tg_offsets[i]); 1060 if (pool->base.timing_generators[i] == NULL) { 1061 BREAK_TO_DEBUGGER(); 1062 dm_error("DC: failed to create tg!\n"); 1063 goto res_create_fail; 1064 } 1065 1066 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1067 if (pool->base.mis[i] == NULL) { 1068 BREAK_TO_DEBUGGER(); 1069 dm_error("DC: failed to create memory input!\n"); 1070 goto res_create_fail; 1071 } 1072 1073 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1074 if (pool->base.ipps[i] == NULL) { 1075 BREAK_TO_DEBUGGER(); 1076 dm_error("DC: failed to create input pixel processor!\n"); 1077 goto res_create_fail; 1078 } 1079 1080 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1081 if (pool->base.transforms[i] == NULL) { 1082 BREAK_TO_DEBUGGER(); 1083 dm_error("DC: failed to create transform!\n"); 1084 goto res_create_fail; 1085 } 1086 1087 pool->base.opps[i] = dce80_opp_create(ctx, i); 1088 if (pool->base.opps[i] == NULL) { 1089 BREAK_TO_DEBUGGER(); 1090 dm_error("DC: failed to create output pixel processor!\n"); 1091 goto res_create_fail; 1092 } 1093 } 1094 1095 dc->caps.max_planes = pool->base.pipe_count; 1096 1097 if (!resource_construct(num_virtual_links, dc, &pool->base, 1098 &res_create_funcs)) 1099 goto res_create_fail; 1100 1101 /* Create hardware sequencer */ 1102 if (!dce80_hw_sequencer_construct(dc)) 1103 goto res_create_fail; 1104 1105 return true; 1106 1107 res_create_fail: 1108 destruct(pool); 1109 return false; 1110 } 1111 1112 struct resource_pool *dce81_create_resource_pool( 1113 uint8_t num_virtual_links, 1114 struct dc *dc) 1115 { 1116 struct dce110_resource_pool *pool = 1117 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1118 1119 if (!pool) 1120 return NULL; 1121 1122 if (dce81_construct(num_virtual_links, dc, pool)) 1123 return &pool->base; 1124 1125 BREAK_TO_DEBUGGER(); 1126 return NULL; 1127 } 1128 1129 static bool dce83_construct( 1130 uint8_t num_virtual_links, 1131 struct dc *dc, 1132 struct dce110_resource_pool *pool) 1133 { 1134 unsigned int i; 1135 struct dc_context *ctx = dc->ctx; 1136 struct dc_firmware_info info; 1137 struct dc_bios *bp; 1138 struct dm_pp_static_clock_info static_clk_info = {0}; 1139 1140 ctx->dc_bios->regs = &bios_regs; 1141 1142 pool->base.res_cap = &res_cap_83; 1143 pool->base.funcs = &dce80_res_pool_funcs; 1144 1145 1146 /************************************************* 1147 * Resource + asic cap harcoding * 1148 *************************************************/ 1149 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1150 pool->base.pipe_count = res_cap_83.num_timing_generator; 1151 dc->caps.max_downscale_ratio = 200; 1152 dc->caps.i2c_speed_in_khz = 40; 1153 dc->caps.max_cursor_size = 128; 1154 1155 /************************************************* 1156 * Create resources * 1157 *************************************************/ 1158 1159 bp = ctx->dc_bios; 1160 1161 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1162 info.external_clock_source_frequency_for_dp != 0) { 1163 pool->base.dp_clock_source = 1164 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1165 1166 pool->base.clock_sources[0] = 1167 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1168 pool->base.clock_sources[1] = 1169 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1170 pool->base.clk_src_count = 2; 1171 1172 } else { 1173 pool->base.dp_clock_source = 1174 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1175 1176 pool->base.clock_sources[0] = 1177 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1178 pool->base.clk_src_count = 1; 1179 } 1180 1181 if (pool->base.dp_clock_source == NULL) { 1182 dm_error("DC: failed to create dp clock source!\n"); 1183 BREAK_TO_DEBUGGER(); 1184 goto res_create_fail; 1185 } 1186 1187 for (i = 0; i < pool->base.clk_src_count; i++) { 1188 if (pool->base.clock_sources[i] == NULL) { 1189 dm_error("DC: failed to create clock sources!\n"); 1190 BREAK_TO_DEBUGGER(); 1191 goto res_create_fail; 1192 } 1193 } 1194 1195 pool->base.display_clock = dce_disp_clk_create(ctx, 1196 &disp_clk_regs, 1197 &disp_clk_shift, 1198 &disp_clk_mask); 1199 if (pool->base.display_clock == NULL) { 1200 dm_error("DC: failed to create display clock!\n"); 1201 BREAK_TO_DEBUGGER(); 1202 goto res_create_fail; 1203 } 1204 1205 1206 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1207 pool->base.display_clock->max_clks_state = 1208 static_clk_info.max_clocks_state; 1209 1210 { 1211 struct irq_service_init_data init_data; 1212 init_data.ctx = dc->ctx; 1213 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1214 if (!pool->base.irqs) 1215 goto res_create_fail; 1216 } 1217 1218 for (i = 0; i < pool->base.pipe_count; i++) { 1219 pool->base.timing_generators[i] = dce80_timing_generator_create( 1220 ctx, i, &dce80_tg_offsets[i]); 1221 if (pool->base.timing_generators[i] == NULL) { 1222 BREAK_TO_DEBUGGER(); 1223 dm_error("DC: failed to create tg!\n"); 1224 goto res_create_fail; 1225 } 1226 1227 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1228 if (pool->base.mis[i] == NULL) { 1229 BREAK_TO_DEBUGGER(); 1230 dm_error("DC: failed to create memory input!\n"); 1231 goto res_create_fail; 1232 } 1233 1234 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1235 if (pool->base.ipps[i] == NULL) { 1236 BREAK_TO_DEBUGGER(); 1237 dm_error("DC: failed to create input pixel processor!\n"); 1238 goto res_create_fail; 1239 } 1240 1241 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1242 if (pool->base.transforms[i] == NULL) { 1243 BREAK_TO_DEBUGGER(); 1244 dm_error("DC: failed to create transform!\n"); 1245 goto res_create_fail; 1246 } 1247 1248 pool->base.opps[i] = dce80_opp_create(ctx, i); 1249 if (pool->base.opps[i] == NULL) { 1250 BREAK_TO_DEBUGGER(); 1251 dm_error("DC: failed to create output pixel processor!\n"); 1252 goto res_create_fail; 1253 } 1254 } 1255 1256 dc->caps.max_planes = pool->base.pipe_count; 1257 1258 if (!resource_construct(num_virtual_links, dc, &pool->base, 1259 &res_create_funcs)) 1260 goto res_create_fail; 1261 1262 /* Create hardware sequencer */ 1263 if (!dce80_hw_sequencer_construct(dc)) 1264 goto res_create_fail; 1265 1266 return true; 1267 1268 res_create_fail: 1269 destruct(pool); 1270 return false; 1271 } 1272 1273 struct resource_pool *dce83_create_resource_pool( 1274 uint8_t num_virtual_links, 1275 struct dc *dc) 1276 { 1277 struct dce110_resource_pool *pool = 1278 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1279 1280 if (!pool) 1281 return NULL; 1282 1283 if (dce83_construct(num_virtual_links, dc, pool)) 1284 return &pool->base; 1285 1286 BREAK_TO_DEBUGGER(); 1287 return NULL; 1288 } 1289