1 /* 2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_6_0_d.h" 29 #include "dce/dce_6_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "include/irq_service_interface.h" 38 #include "irq/dce60/irq_service_dce60.h" 39 #include "dce110/dce110_timing_generator.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce60/dce60_timing_generator.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce/dce_link_encoder.h" 44 #include "dce/dce_stream_encoder.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_transform.h" 47 #include "dce/dce_opp.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce60/dce60_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 #include "dce/dce_panel_cntl.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_dmcu.h" 58 #include "dce/dce_aux.h" 59 #include "dce/dce_abm.h" 60 #include "dce/dce_i2c.h" 61 /* TODO remove this include */ 62 63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 64 #include "gmc/gmc_6_0_d.h" 65 #include "gmc/gmc_6_0_sh_mask.h" 66 #endif 67 68 #ifndef mmDP_DPHY_INTERNAL_CTRL 69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #endif 94 95 96 #ifndef mmHPD_DC_HPD_CONTROL 97 #define mmHPD_DC_HPD_CONTROL 0x189A 98 #define mmHPD0_DC_HPD_CONTROL 0x189A 99 #define mmHPD1_DC_HPD_CONTROL 0x18A2 100 #define mmHPD2_DC_HPD_CONTROL 0x18AA 101 #define mmHPD3_DC_HPD_CONTROL 0x18B2 102 #define mmHPD4_DC_HPD_CONTROL 0x18BA 103 #define mmHPD5_DC_HPD_CONTROL 0x18C2 104 #endif 105 106 #define DCE11_DIG_FE_CNTL 0x4a00 107 #define DCE11_DIG_BE_CNTL 0x4a47 108 #define DCE11_DP_SEC 0x4ac3 109 110 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = { 111 { 112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 114 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 115 - mmDPG_PIPE_ARBITRATION_CONTROL3), 116 }, 117 { 118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 120 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 121 - mmDPG_PIPE_ARBITRATION_CONTROL3), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 127 - mmDPG_PIPE_ARBITRATION_CONTROL3), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 133 - mmDPG_PIPE_ARBITRATION_CONTROL3), 134 }, 135 { 136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 138 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 139 - mmDPG_PIPE_ARBITRATION_CONTROL3), 140 }, 141 { 142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 144 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 145 - mmDPG_PIPE_ARBITRATION_CONTROL3), 146 } 147 }; 148 149 /* set register offset */ 150 #define SR(reg_name)\ 151 .reg_name = mm ## reg_name 152 153 /* set register offset with instance */ 154 #define SRI(reg_name, block, id)\ 155 .reg_name = mm ## block ## id ## _ ## reg_name 156 157 #define ipp_regs(id)\ 158 [id] = {\ 159 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 160 } 161 162 static const struct dce_ipp_registers ipp_regs[] = { 163 ipp_regs(0), 164 ipp_regs(1), 165 ipp_regs(2), 166 ipp_regs(3), 167 ipp_regs(4), 168 ipp_regs(5) 169 }; 170 171 static const struct dce_ipp_shift ipp_shift = { 172 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 173 }; 174 175 static const struct dce_ipp_mask ipp_mask = { 176 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 177 }; 178 179 #define transform_regs(id)\ 180 [id] = {\ 181 XFM_COMMON_REG_LIST_DCE60(id)\ 182 } 183 184 static const struct dce_transform_registers xfm_regs[] = { 185 transform_regs(0), 186 transform_regs(1), 187 transform_regs(2), 188 transform_regs(3), 189 transform_regs(4), 190 transform_regs(5) 191 }; 192 193 static const struct dce_transform_shift xfm_shift = { 194 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT) 195 }; 196 197 static const struct dce_transform_mask xfm_mask = { 198 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK) 199 }; 200 201 #define aux_regs(id)\ 202 [id] = {\ 203 AUX_REG_LIST(id)\ 204 } 205 206 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 207 aux_regs(0), 208 aux_regs(1), 209 aux_regs(2), 210 aux_regs(3), 211 aux_regs(4), 212 aux_regs(5) 213 }; 214 215 #define hpd_regs(id)\ 216 [id] = {\ 217 HPD_REG_LIST(id)\ 218 } 219 220 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 221 hpd_regs(0), 222 hpd_regs(1), 223 hpd_regs(2), 224 hpd_regs(3), 225 hpd_regs(4), 226 hpd_regs(5) 227 }; 228 229 #define link_regs(id)\ 230 [id] = {\ 231 LE_DCE60_REG_LIST(id)\ 232 } 233 234 static const struct dce110_link_enc_registers link_enc_regs[] = { 235 link_regs(0), 236 link_regs(1), 237 link_regs(2), 238 link_regs(3), 239 link_regs(4), 240 link_regs(5) 241 }; 242 243 #define stream_enc_regs(id)\ 244 [id] = {\ 245 SE_COMMON_REG_LIST_DCE_BASE(id),\ 246 .AFMT_CNTL = 0,\ 247 } 248 249 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 250 stream_enc_regs(0), 251 stream_enc_regs(1), 252 stream_enc_regs(2), 253 stream_enc_regs(3), 254 stream_enc_regs(4), 255 stream_enc_regs(5) 256 }; 257 258 static const struct dce_stream_encoder_shift se_shift = { 259 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 260 }; 261 262 static const struct dce_stream_encoder_mask se_mask = { 263 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 264 }; 265 266 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 267 { DCE_PANEL_CNTL_REG_LIST() } 268 }; 269 270 static const struct dce_panel_cntl_shift panel_cntl_shift = { 271 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_panel_cntl_mask panel_cntl_mask = { 275 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_60_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK) 298 }; 299 300 static const struct dce110_aux_registers_shift aux_shift = { 301 DCE10_AUX_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dce110_aux_registers_mask aux_mask = { 305 DCE10_AUX_MASK_SH_LIST(_MASK) 306 }; 307 308 #define aux_engine_regs(id)\ 309 [id] = {\ 310 AUX_COMMON_REG_LIST(id), \ 311 .AUX_RESET_MASK = 0 \ 312 } 313 314 static const struct dce110_aux_registers aux_engine_regs[] = { 315 aux_engine_regs(0), 316 aux_engine_regs(1), 317 aux_engine_regs(2), 318 aux_engine_regs(3), 319 aux_engine_regs(4), 320 aux_engine_regs(5) 321 }; 322 323 #define audio_regs(id)\ 324 [id] = {\ 325 AUD_COMMON_REG_LIST(id)\ 326 } 327 328 static const struct dce_audio_registers audio_regs[] = { 329 audio_regs(0), 330 audio_regs(1), 331 audio_regs(2), 332 audio_regs(3), 333 audio_regs(4), 334 audio_regs(5), 335 }; 336 337 static const struct dce_audio_shift audio_shift = { 338 AUD_DCE60_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dce_audio_mask audio_mask = { 342 AUD_DCE60_MASK_SH_LIST(_MASK) 343 }; 344 345 #define clk_src_regs(id)\ 346 [id] = {\ 347 CS_COMMON_REG_LIST_DCE_80(id),\ 348 } 349 350 351 static const struct dce110_clk_src_regs clk_src_regs[] = { 352 clk_src_regs(0), 353 clk_src_regs(1), 354 clk_src_regs(2) 355 }; 356 357 static const struct dce110_clk_src_shift cs_shift = { 358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 359 }; 360 361 static const struct dce110_clk_src_mask cs_mask = { 362 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 363 }; 364 365 static const struct bios_registers bios_regs = { 366 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 367 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 368 }; 369 370 static const struct resource_caps res_cap = { 371 .num_timing_generator = 6, 372 .num_audio = 6, 373 .num_stream_encoder = 6, 374 .num_pll = 2, 375 .num_ddc = 6, 376 }; 377 378 static const struct resource_caps res_cap_61 = { 379 .num_timing_generator = 4, 380 .num_audio = 6, 381 .num_stream_encoder = 6, 382 .num_pll = 3, 383 .num_ddc = 6, 384 }; 385 386 static const struct resource_caps res_cap_64 = { 387 .num_timing_generator = 2, 388 .num_audio = 2, 389 .num_stream_encoder = 2, 390 .num_pll = 2, 391 .num_ddc = 2, 392 }; 393 394 static const struct dc_plane_cap plane_cap = { 395 .type = DC_PLANE_TYPE_DCE_RGB, 396 397 .pixel_format_support = { 398 .argb8888 = true, 399 .nv12 = false, 400 .fp16 = false 401 }, 402 403 .max_upscale_factor = { 404 .argb8888 = 16000, 405 .nv12 = 1, 406 .fp16 = 1 407 }, 408 409 .max_downscale_factor = { 410 .argb8888 = 250, 411 .nv12 = 1, 412 .fp16 = 1 413 } 414 }; 415 416 static const struct dce_dmcu_registers dmcu_regs = { 417 DMCU_DCE60_REG_LIST() 418 }; 419 420 static const struct dce_dmcu_shift dmcu_shift = { 421 DMCU_MASK_SH_LIST_DCE60(__SHIFT) 422 }; 423 424 static const struct dce_dmcu_mask dmcu_mask = { 425 DMCU_MASK_SH_LIST_DCE60(_MASK) 426 }; 427 static const struct dce_abm_registers abm_regs = { 428 ABM_DCE110_COMMON_REG_LIST() 429 }; 430 431 static const struct dce_abm_shift abm_shift = { 432 ABM_MASK_SH_LIST_DCE110(__SHIFT) 433 }; 434 435 static const struct dce_abm_mask abm_mask = { 436 ABM_MASK_SH_LIST_DCE110(_MASK) 437 }; 438 439 #define CTX ctx 440 #define REG(reg) mm ## reg 441 442 #ifndef mmCC_DC_HDMI_STRAPS 443 #define mmCC_DC_HDMI_STRAPS 0x1918 444 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 446 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 448 #endif 449 450 static int map_transmitter_id_to_phy_instance( 451 enum transmitter transmitter) 452 { 453 switch (transmitter) { 454 case TRANSMITTER_UNIPHY_A: 455 return 0; 456 break; 457 case TRANSMITTER_UNIPHY_B: 458 return 1; 459 break; 460 case TRANSMITTER_UNIPHY_C: 461 return 2; 462 break; 463 case TRANSMITTER_UNIPHY_D: 464 return 3; 465 break; 466 case TRANSMITTER_UNIPHY_E: 467 return 4; 468 break; 469 case TRANSMITTER_UNIPHY_F: 470 return 5; 471 break; 472 case TRANSMITTER_UNIPHY_G: 473 return 6; 474 break; 475 default: 476 ASSERT(0); 477 return 0; 478 } 479 } 480 481 static void read_dce_straps( 482 struct dc_context *ctx, 483 struct resource_straps *straps) 484 { 485 REG_GET_2(CC_DC_HDMI_STRAPS, 486 HDMI_DISABLE, &straps->hdmi_disable, 487 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 488 489 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 490 } 491 492 static struct audio *create_audio( 493 struct dc_context *ctx, unsigned int inst) 494 { 495 return dce60_audio_create(ctx, inst, 496 &audio_regs[inst], &audio_shift, &audio_mask); 497 } 498 499 static struct timing_generator *dce60_timing_generator_create( 500 struct dc_context *ctx, 501 uint32_t instance, 502 const struct dce110_timing_generator_offsets *offsets) 503 { 504 struct dce110_timing_generator *tg110 = 505 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 506 507 if (!tg110) 508 return NULL; 509 510 dce60_timing_generator_construct(tg110, ctx, instance, offsets); 511 return &tg110->base; 512 } 513 514 static struct output_pixel_processor *dce60_opp_create( 515 struct dc_context *ctx, 516 uint32_t inst) 517 { 518 struct dce110_opp *opp = 519 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 520 521 if (!opp) 522 return NULL; 523 524 dce60_opp_construct(opp, 525 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 526 return &opp->base; 527 } 528 529 struct dce_aux *dce60_aux_engine_create( 530 struct dc_context *ctx, 531 uint32_t inst) 532 { 533 struct aux_engine_dce110 *aux_engine = 534 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 535 536 if (!aux_engine) 537 return NULL; 538 539 dce110_aux_engine_construct(aux_engine, ctx, inst, 540 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 541 &aux_engine_regs[inst], 542 &aux_mask, 543 &aux_shift, 544 ctx->dc->caps.extended_aux_timeout_support); 545 546 return &aux_engine->base; 547 } 548 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 549 550 static const struct dce_i2c_registers i2c_hw_regs[] = { 551 i2c_inst_regs(1), 552 i2c_inst_regs(2), 553 i2c_inst_regs(3), 554 i2c_inst_regs(4), 555 i2c_inst_regs(5), 556 i2c_inst_regs(6), 557 }; 558 559 static const struct dce_i2c_shift i2c_shifts = { 560 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 561 }; 562 563 static const struct dce_i2c_mask i2c_masks = { 564 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 565 }; 566 567 struct dce_i2c_hw *dce60_i2c_hw_create( 568 struct dc_context *ctx, 569 uint32_t inst) 570 { 571 struct dce_i2c_hw *dce_i2c_hw = 572 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 573 574 if (!dce_i2c_hw) 575 return NULL; 576 577 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 578 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 579 580 return dce_i2c_hw; 581 } 582 583 struct dce_i2c_sw *dce60_i2c_sw_create( 584 struct dc_context *ctx) 585 { 586 struct dce_i2c_sw *dce_i2c_sw = 587 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 588 589 if (!dce_i2c_sw) 590 return NULL; 591 592 dce_i2c_sw_construct(dce_i2c_sw, ctx); 593 594 return dce_i2c_sw; 595 } 596 static struct stream_encoder *dce60_stream_encoder_create( 597 enum engine_id eng_id, 598 struct dc_context *ctx) 599 { 600 struct dce110_stream_encoder *enc110 = 601 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 602 603 if (!enc110) 604 return NULL; 605 606 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 607 &stream_enc_regs[eng_id], 608 &se_shift, &se_mask); 609 return &enc110->base; 610 } 611 612 #define SRII(reg_name, block, id)\ 613 .reg_name[id] = mm ## block ## id ## _ ## reg_name 614 615 static const struct dce_hwseq_registers hwseq_reg = { 616 HWSEQ_DCE6_REG_LIST() 617 }; 618 619 static const struct dce_hwseq_shift hwseq_shift = { 620 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT) 621 }; 622 623 static const struct dce_hwseq_mask hwseq_mask = { 624 HWSEQ_DCE6_MASK_SH_LIST(_MASK) 625 }; 626 627 static struct dce_hwseq *dce60_hwseq_create( 628 struct dc_context *ctx) 629 { 630 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 631 632 if (hws) { 633 hws->ctx = ctx; 634 hws->regs = &hwseq_reg; 635 hws->shifts = &hwseq_shift; 636 hws->masks = &hwseq_mask; 637 } 638 return hws; 639 } 640 641 static const struct resource_create_funcs res_create_funcs = { 642 .read_dce_straps = read_dce_straps, 643 .create_audio = create_audio, 644 .create_stream_encoder = dce60_stream_encoder_create, 645 .create_hwseq = dce60_hwseq_create, 646 }; 647 648 #define mi_inst_regs(id) { \ 649 MI_DCE6_REG_LIST(id), \ 650 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 651 } 652 static const struct dce_mem_input_registers mi_regs[] = { 653 mi_inst_regs(0), 654 mi_inst_regs(1), 655 mi_inst_regs(2), 656 mi_inst_regs(3), 657 mi_inst_regs(4), 658 mi_inst_regs(5), 659 }; 660 661 static const struct dce_mem_input_shift mi_shifts = { 662 MI_DCE6_MASK_SH_LIST(__SHIFT), 663 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 664 }; 665 666 static const struct dce_mem_input_mask mi_masks = { 667 MI_DCE6_MASK_SH_LIST(_MASK), 668 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 669 }; 670 671 static struct mem_input *dce60_mem_input_create( 672 struct dc_context *ctx, 673 uint32_t inst) 674 { 675 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 676 GFP_KERNEL); 677 678 if (!dce_mi) { 679 BREAK_TO_DEBUGGER(); 680 return NULL; 681 } 682 683 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 684 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 685 return &dce_mi->base; 686 } 687 688 static void dce60_transform_destroy(struct transform **xfm) 689 { 690 kfree(TO_DCE_TRANSFORM(*xfm)); 691 *xfm = NULL; 692 } 693 694 static struct transform *dce60_transform_create( 695 struct dc_context *ctx, 696 uint32_t inst) 697 { 698 struct dce_transform *transform = 699 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 700 701 if (!transform) 702 return NULL; 703 704 dce60_transform_construct(transform, ctx, inst, 705 &xfm_regs[inst], &xfm_shift, &xfm_mask); 706 transform->prescaler_on = false; 707 return &transform->base; 708 } 709 710 static const struct encoder_feature_support link_enc_feature = { 711 .max_hdmi_deep_color = COLOR_DEPTH_121212, 712 .max_hdmi_pixel_clock = 297000, 713 .flags.bits.IS_HBR2_CAPABLE = true, 714 .flags.bits.IS_TPS3_CAPABLE = true 715 }; 716 717 struct link_encoder *dce60_link_encoder_create( 718 const struct encoder_init_data *enc_init_data) 719 { 720 struct dce110_link_encoder *enc110 = 721 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 722 int link_regs_id; 723 724 if (!enc110) 725 return NULL; 726 727 link_regs_id = 728 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 729 730 dce60_link_encoder_construct(enc110, 731 enc_init_data, 732 &link_enc_feature, 733 &link_enc_regs[link_regs_id], 734 &link_enc_aux_regs[enc_init_data->channel - 1], 735 &link_enc_hpd_regs[enc_init_data->hpd_source]); 736 return &enc110->base; 737 } 738 739 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data) 740 { 741 struct dce_panel_cntl *panel_cntl = 742 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 743 744 if (!panel_cntl) 745 return NULL; 746 747 dce_panel_cntl_construct(panel_cntl, 748 init_data, 749 &panel_cntl_regs[init_data->inst], 750 &panel_cntl_shift, 751 &panel_cntl_mask); 752 753 return &panel_cntl->base; 754 } 755 756 struct clock_source *dce60_clock_source_create( 757 struct dc_context *ctx, 758 struct dc_bios *bios, 759 enum clock_source_id id, 760 const struct dce110_clk_src_regs *regs, 761 bool dp_clk_src) 762 { 763 struct dce110_clk_src *clk_src = 764 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 765 766 if (!clk_src) 767 return NULL; 768 769 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 770 regs, &cs_shift, &cs_mask)) { 771 clk_src->base.dp_clk_src = dp_clk_src; 772 return &clk_src->base; 773 } 774 775 kfree(clk_src); 776 BREAK_TO_DEBUGGER(); 777 return NULL; 778 } 779 780 void dce60_clock_source_destroy(struct clock_source **clk_src) 781 { 782 kfree(TO_DCE110_CLK_SRC(*clk_src)); 783 *clk_src = NULL; 784 } 785 786 static struct input_pixel_processor *dce60_ipp_create( 787 struct dc_context *ctx, uint32_t inst) 788 { 789 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 790 791 if (!ipp) { 792 BREAK_TO_DEBUGGER(); 793 return NULL; 794 } 795 796 dce60_ipp_construct(ipp, ctx, inst, 797 &ipp_regs[inst], &ipp_shift, &ipp_mask); 798 return &ipp->base; 799 } 800 801 static void dce60_resource_destruct(struct dce110_resource_pool *pool) 802 { 803 unsigned int i; 804 805 for (i = 0; i < pool->base.pipe_count; i++) { 806 if (pool->base.opps[i] != NULL) 807 dce110_opp_destroy(&pool->base.opps[i]); 808 809 if (pool->base.transforms[i] != NULL) 810 dce60_transform_destroy(&pool->base.transforms[i]); 811 812 if (pool->base.ipps[i] != NULL) 813 dce_ipp_destroy(&pool->base.ipps[i]); 814 815 if (pool->base.mis[i] != NULL) { 816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 817 pool->base.mis[i] = NULL; 818 } 819 820 if (pool->base.timing_generators[i] != NULL) { 821 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 822 pool->base.timing_generators[i] = NULL; 823 } 824 } 825 826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 827 if (pool->base.engines[i] != NULL) 828 dce110_engine_destroy(&pool->base.engines[i]); 829 if (pool->base.hw_i2cs[i] != NULL) { 830 kfree(pool->base.hw_i2cs[i]); 831 pool->base.hw_i2cs[i] = NULL; 832 } 833 if (pool->base.sw_i2cs[i] != NULL) { 834 kfree(pool->base.sw_i2cs[i]); 835 pool->base.sw_i2cs[i] = NULL; 836 } 837 } 838 839 for (i = 0; i < pool->base.stream_enc_count; i++) { 840 if (pool->base.stream_enc[i] != NULL) 841 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 842 } 843 844 for (i = 0; i < pool->base.clk_src_count; i++) { 845 if (pool->base.clock_sources[i] != NULL) { 846 dce60_clock_source_destroy(&pool->base.clock_sources[i]); 847 } 848 } 849 850 if (pool->base.abm != NULL) 851 dce_abm_destroy(&pool->base.abm); 852 853 if (pool->base.dmcu != NULL) 854 dce_dmcu_destroy(&pool->base.dmcu); 855 856 if (pool->base.dp_clock_source != NULL) 857 dce60_clock_source_destroy(&pool->base.dp_clock_source); 858 859 for (i = 0; i < pool->base.audio_count; i++) { 860 if (pool->base.audios[i] != NULL) { 861 dce_aud_destroy(&pool->base.audios[i]); 862 } 863 } 864 865 if (pool->base.irqs != NULL) { 866 dal_irq_service_destroy(&pool->base.irqs); 867 } 868 } 869 870 bool dce60_validate_bandwidth( 871 struct dc *dc, 872 struct dc_state *context, 873 bool fast_validate) 874 { 875 int i; 876 bool at_least_one_pipe = false; 877 878 for (i = 0; i < dc->res_pool->pipe_count; i++) { 879 if (context->res_ctx.pipe_ctx[i].stream) 880 at_least_one_pipe = true; 881 } 882 883 if (at_least_one_pipe) { 884 /* TODO implement when needed but for now hardcode max value*/ 885 context->bw_ctx.bw.dce.dispclk_khz = 681000; 886 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 887 } else { 888 context->bw_ctx.bw.dce.dispclk_khz = 0; 889 context->bw_ctx.bw.dce.yclk_khz = 0; 890 } 891 892 return true; 893 } 894 895 static bool dce60_validate_surface_sets( 896 struct dc_state *context) 897 { 898 int i; 899 900 for (i = 0; i < context->stream_count; i++) { 901 if (context->stream_status[i].plane_count == 0) 902 continue; 903 904 if (context->stream_status[i].plane_count > 1) 905 return false; 906 907 if (context->stream_status[i].plane_states[0]->format 908 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 909 return false; 910 } 911 912 return true; 913 } 914 915 enum dc_status dce60_validate_global( 916 struct dc *dc, 917 struct dc_state *context) 918 { 919 if (!dce60_validate_surface_sets(context)) 920 return DC_FAIL_SURFACE_VALIDATE; 921 922 return DC_OK; 923 } 924 925 static void dce60_destroy_resource_pool(struct resource_pool **pool) 926 { 927 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 928 929 dce60_resource_destruct(dce110_pool); 930 kfree(dce110_pool); 931 *pool = NULL; 932 } 933 934 static const struct resource_funcs dce60_res_pool_funcs = { 935 .destroy = dce60_destroy_resource_pool, 936 .link_enc_create = dce60_link_encoder_create, 937 .panel_cntl_create = dce60_panel_cntl_create, 938 .validate_bandwidth = dce60_validate_bandwidth, 939 .validate_plane = dce100_validate_plane, 940 .add_stream_to_ctx = dce100_add_stream_to_ctx, 941 .validate_global = dce60_validate_global, 942 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 943 }; 944 945 static bool dce60_construct( 946 uint8_t num_virtual_links, 947 struct dc *dc, 948 struct dce110_resource_pool *pool) 949 { 950 unsigned int i; 951 struct dc_context *ctx = dc->ctx; 952 struct dc_bios *bp; 953 954 ctx->dc_bios->regs = &bios_regs; 955 956 pool->base.res_cap = &res_cap; 957 pool->base.funcs = &dce60_res_pool_funcs; 958 959 960 /************************************************* 961 * Resource + asic cap harcoding * 962 *************************************************/ 963 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 964 pool->base.pipe_count = res_cap.num_timing_generator; 965 pool->base.timing_generator_count = res_cap.num_timing_generator; 966 dc->caps.max_downscale_ratio = 200; 967 dc->caps.i2c_speed_in_khz = 40; 968 dc->caps.max_cursor_size = 64; 969 dc->caps.dual_link_dvi = true; 970 dc->caps.extended_aux_timeout_support = false; 971 972 /************************************************* 973 * Create resources * 974 *************************************************/ 975 976 bp = ctx->dc_bios; 977 978 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 979 pool->base.dp_clock_source = 980 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 981 982 pool->base.clock_sources[0] = 983 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 984 pool->base.clock_sources[1] = 985 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 986 pool->base.clk_src_count = 2; 987 988 } else { 989 pool->base.dp_clock_source = 990 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 991 992 pool->base.clock_sources[0] = 993 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 994 pool->base.clk_src_count = 1; 995 } 996 997 if (pool->base.dp_clock_source == NULL) { 998 dm_error("DC: failed to create dp clock source!\n"); 999 BREAK_TO_DEBUGGER(); 1000 goto res_create_fail; 1001 } 1002 1003 for (i = 0; i < pool->base.clk_src_count; i++) { 1004 if (pool->base.clock_sources[i] == NULL) { 1005 dm_error("DC: failed to create clock sources!\n"); 1006 BREAK_TO_DEBUGGER(); 1007 goto res_create_fail; 1008 } 1009 } 1010 1011 pool->base.dmcu = dce_dmcu_create(ctx, 1012 &dmcu_regs, 1013 &dmcu_shift, 1014 &dmcu_mask); 1015 if (pool->base.dmcu == NULL) { 1016 dm_error("DC: failed to create dmcu!\n"); 1017 BREAK_TO_DEBUGGER(); 1018 goto res_create_fail; 1019 } 1020 1021 pool->base.abm = dce_abm_create(ctx, 1022 &abm_regs, 1023 &abm_shift, 1024 &abm_mask); 1025 if (pool->base.abm == NULL) { 1026 dm_error("DC: failed to create abm!\n"); 1027 BREAK_TO_DEBUGGER(); 1028 goto res_create_fail; 1029 } 1030 1031 { 1032 struct irq_service_init_data init_data; 1033 init_data.ctx = dc->ctx; 1034 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1035 if (!pool->base.irqs) 1036 goto res_create_fail; 1037 } 1038 1039 for (i = 0; i < pool->base.pipe_count; i++) { 1040 pool->base.timing_generators[i] = dce60_timing_generator_create( 1041 ctx, i, &dce60_tg_offsets[i]); 1042 if (pool->base.timing_generators[i] == NULL) { 1043 BREAK_TO_DEBUGGER(); 1044 dm_error("DC: failed to create tg!\n"); 1045 goto res_create_fail; 1046 } 1047 1048 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1049 if (pool->base.mis[i] == NULL) { 1050 BREAK_TO_DEBUGGER(); 1051 dm_error("DC: failed to create memory input!\n"); 1052 goto res_create_fail; 1053 } 1054 1055 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1056 if (pool->base.ipps[i] == NULL) { 1057 BREAK_TO_DEBUGGER(); 1058 dm_error("DC: failed to create input pixel processor!\n"); 1059 goto res_create_fail; 1060 } 1061 1062 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1063 if (pool->base.transforms[i] == NULL) { 1064 BREAK_TO_DEBUGGER(); 1065 dm_error("DC: failed to create transform!\n"); 1066 goto res_create_fail; 1067 } 1068 1069 pool->base.opps[i] = dce60_opp_create(ctx, i); 1070 if (pool->base.opps[i] == NULL) { 1071 BREAK_TO_DEBUGGER(); 1072 dm_error("DC: failed to create output pixel processor!\n"); 1073 goto res_create_fail; 1074 } 1075 } 1076 1077 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1078 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1079 if (pool->base.engines[i] == NULL) { 1080 BREAK_TO_DEBUGGER(); 1081 dm_error( 1082 "DC:failed to create aux engine!!\n"); 1083 goto res_create_fail; 1084 } 1085 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1086 if (pool->base.hw_i2cs[i] == NULL) { 1087 BREAK_TO_DEBUGGER(); 1088 dm_error( 1089 "DC:failed to create i2c engine!!\n"); 1090 goto res_create_fail; 1091 } 1092 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1093 if (pool->base.sw_i2cs[i] == NULL) { 1094 BREAK_TO_DEBUGGER(); 1095 dm_error( 1096 "DC:failed to create sw i2c!!\n"); 1097 goto res_create_fail; 1098 } 1099 } 1100 1101 dc->caps.max_planes = pool->base.pipe_count; 1102 1103 for (i = 0; i < dc->caps.max_planes; ++i) 1104 dc->caps.planes[i] = plane_cap; 1105 1106 dc->caps.disable_dp_clk_share = true; 1107 1108 if (!resource_construct(num_virtual_links, dc, &pool->base, 1109 &res_create_funcs)) 1110 goto res_create_fail; 1111 1112 /* Create hardware sequencer */ 1113 dce60_hw_sequencer_construct(dc); 1114 1115 return true; 1116 1117 res_create_fail: 1118 dce60_resource_destruct(pool); 1119 return false; 1120 } 1121 1122 struct resource_pool *dce60_create_resource_pool( 1123 uint8_t num_virtual_links, 1124 struct dc *dc) 1125 { 1126 struct dce110_resource_pool *pool = 1127 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1128 1129 if (!pool) 1130 return NULL; 1131 1132 if (dce60_construct(num_virtual_links, dc, pool)) 1133 return &pool->base; 1134 1135 BREAK_TO_DEBUGGER(); 1136 return NULL; 1137 } 1138 1139 static bool dce61_construct( 1140 uint8_t num_virtual_links, 1141 struct dc *dc, 1142 struct dce110_resource_pool *pool) 1143 { 1144 unsigned int i; 1145 struct dc_context *ctx = dc->ctx; 1146 struct dc_bios *bp; 1147 1148 ctx->dc_bios->regs = &bios_regs; 1149 1150 pool->base.res_cap = &res_cap_61; 1151 pool->base.funcs = &dce60_res_pool_funcs; 1152 1153 1154 /************************************************* 1155 * Resource + asic cap harcoding * 1156 *************************************************/ 1157 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1158 pool->base.pipe_count = res_cap_61.num_timing_generator; 1159 pool->base.timing_generator_count = res_cap_61.num_timing_generator; 1160 dc->caps.max_downscale_ratio = 200; 1161 dc->caps.i2c_speed_in_khz = 40; 1162 dc->caps.max_cursor_size = 64; 1163 dc->caps.is_apu = true; 1164 1165 /************************************************* 1166 * Create resources * 1167 *************************************************/ 1168 1169 bp = ctx->dc_bios; 1170 1171 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1172 pool->base.dp_clock_source = 1173 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1174 1175 pool->base.clock_sources[0] = 1176 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1177 pool->base.clock_sources[1] = 1178 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1179 pool->base.clock_sources[2] = 1180 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1181 pool->base.clk_src_count = 3; 1182 1183 } else { 1184 pool->base.dp_clock_source = 1185 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1186 1187 pool->base.clock_sources[0] = 1188 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1189 pool->base.clock_sources[1] = 1190 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1191 pool->base.clk_src_count = 2; 1192 } 1193 1194 if (pool->base.dp_clock_source == NULL) { 1195 dm_error("DC: failed to create dp clock source!\n"); 1196 BREAK_TO_DEBUGGER(); 1197 goto res_create_fail; 1198 } 1199 1200 for (i = 0; i < pool->base.clk_src_count; i++) { 1201 if (pool->base.clock_sources[i] == NULL) { 1202 dm_error("DC: failed to create clock sources!\n"); 1203 BREAK_TO_DEBUGGER(); 1204 goto res_create_fail; 1205 } 1206 } 1207 1208 pool->base.dmcu = dce_dmcu_create(ctx, 1209 &dmcu_regs, 1210 &dmcu_shift, 1211 &dmcu_mask); 1212 if (pool->base.dmcu == NULL) { 1213 dm_error("DC: failed to create dmcu!\n"); 1214 BREAK_TO_DEBUGGER(); 1215 goto res_create_fail; 1216 } 1217 1218 pool->base.abm = dce_abm_create(ctx, 1219 &abm_regs, 1220 &abm_shift, 1221 &abm_mask); 1222 if (pool->base.abm == NULL) { 1223 dm_error("DC: failed to create abm!\n"); 1224 BREAK_TO_DEBUGGER(); 1225 goto res_create_fail; 1226 } 1227 1228 { 1229 struct irq_service_init_data init_data; 1230 init_data.ctx = dc->ctx; 1231 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1232 if (!pool->base.irqs) 1233 goto res_create_fail; 1234 } 1235 1236 for (i = 0; i < pool->base.pipe_count; i++) { 1237 pool->base.timing_generators[i] = dce60_timing_generator_create( 1238 ctx, i, &dce60_tg_offsets[i]); 1239 if (pool->base.timing_generators[i] == NULL) { 1240 BREAK_TO_DEBUGGER(); 1241 dm_error("DC: failed to create tg!\n"); 1242 goto res_create_fail; 1243 } 1244 1245 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1246 if (pool->base.mis[i] == NULL) { 1247 BREAK_TO_DEBUGGER(); 1248 dm_error("DC: failed to create memory input!\n"); 1249 goto res_create_fail; 1250 } 1251 1252 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1253 if (pool->base.ipps[i] == NULL) { 1254 BREAK_TO_DEBUGGER(); 1255 dm_error("DC: failed to create input pixel processor!\n"); 1256 goto res_create_fail; 1257 } 1258 1259 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1260 if (pool->base.transforms[i] == NULL) { 1261 BREAK_TO_DEBUGGER(); 1262 dm_error("DC: failed to create transform!\n"); 1263 goto res_create_fail; 1264 } 1265 1266 pool->base.opps[i] = dce60_opp_create(ctx, i); 1267 if (pool->base.opps[i] == NULL) { 1268 BREAK_TO_DEBUGGER(); 1269 dm_error("DC: failed to create output pixel processor!\n"); 1270 goto res_create_fail; 1271 } 1272 } 1273 1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1275 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1276 if (pool->base.engines[i] == NULL) { 1277 BREAK_TO_DEBUGGER(); 1278 dm_error( 1279 "DC:failed to create aux engine!!\n"); 1280 goto res_create_fail; 1281 } 1282 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1283 if (pool->base.hw_i2cs[i] == NULL) { 1284 BREAK_TO_DEBUGGER(); 1285 dm_error( 1286 "DC:failed to create i2c engine!!\n"); 1287 goto res_create_fail; 1288 } 1289 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1290 if (pool->base.sw_i2cs[i] == NULL) { 1291 BREAK_TO_DEBUGGER(); 1292 dm_error( 1293 "DC:failed to create sw i2c!!\n"); 1294 goto res_create_fail; 1295 } 1296 } 1297 1298 dc->caps.max_planes = pool->base.pipe_count; 1299 1300 for (i = 0; i < dc->caps.max_planes; ++i) 1301 dc->caps.planes[i] = plane_cap; 1302 1303 dc->caps.disable_dp_clk_share = true; 1304 1305 if (!resource_construct(num_virtual_links, dc, &pool->base, 1306 &res_create_funcs)) 1307 goto res_create_fail; 1308 1309 /* Create hardware sequencer */ 1310 dce60_hw_sequencer_construct(dc); 1311 1312 return true; 1313 1314 res_create_fail: 1315 dce60_resource_destruct(pool); 1316 return false; 1317 } 1318 1319 struct resource_pool *dce61_create_resource_pool( 1320 uint8_t num_virtual_links, 1321 struct dc *dc) 1322 { 1323 struct dce110_resource_pool *pool = 1324 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1325 1326 if (!pool) 1327 return NULL; 1328 1329 if (dce61_construct(num_virtual_links, dc, pool)) 1330 return &pool->base; 1331 1332 BREAK_TO_DEBUGGER(); 1333 return NULL; 1334 } 1335 1336 static bool dce64_construct( 1337 uint8_t num_virtual_links, 1338 struct dc *dc, 1339 struct dce110_resource_pool *pool) 1340 { 1341 unsigned int i; 1342 struct dc_context *ctx = dc->ctx; 1343 struct dc_bios *bp; 1344 1345 ctx->dc_bios->regs = &bios_regs; 1346 1347 pool->base.res_cap = &res_cap_64; 1348 pool->base.funcs = &dce60_res_pool_funcs; 1349 1350 1351 /************************************************* 1352 * Resource + asic cap harcoding * 1353 *************************************************/ 1354 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1355 pool->base.pipe_count = res_cap_64.num_timing_generator; 1356 pool->base.timing_generator_count = res_cap_64.num_timing_generator; 1357 dc->caps.max_downscale_ratio = 200; 1358 dc->caps.i2c_speed_in_khz = 40; 1359 dc->caps.max_cursor_size = 64; 1360 dc->caps.is_apu = true; 1361 1362 /************************************************* 1363 * Create resources * 1364 *************************************************/ 1365 1366 bp = ctx->dc_bios; 1367 1368 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1369 pool->base.dp_clock_source = 1370 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1371 1372 pool->base.clock_sources[0] = 1373 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1374 pool->base.clock_sources[1] = 1375 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1376 pool->base.clk_src_count = 2; 1377 1378 } else { 1379 pool->base.dp_clock_source = 1380 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1381 1382 pool->base.clock_sources[0] = 1383 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1384 pool->base.clk_src_count = 1; 1385 } 1386 1387 if (pool->base.dp_clock_source == NULL) { 1388 dm_error("DC: failed to create dp clock source!\n"); 1389 BREAK_TO_DEBUGGER(); 1390 goto res_create_fail; 1391 } 1392 1393 for (i = 0; i < pool->base.clk_src_count; i++) { 1394 if (pool->base.clock_sources[i] == NULL) { 1395 dm_error("DC: failed to create clock sources!\n"); 1396 BREAK_TO_DEBUGGER(); 1397 goto res_create_fail; 1398 } 1399 } 1400 1401 pool->base.dmcu = dce_dmcu_create(ctx, 1402 &dmcu_regs, 1403 &dmcu_shift, 1404 &dmcu_mask); 1405 if (pool->base.dmcu == NULL) { 1406 dm_error("DC: failed to create dmcu!\n"); 1407 BREAK_TO_DEBUGGER(); 1408 goto res_create_fail; 1409 } 1410 1411 pool->base.abm = dce_abm_create(ctx, 1412 &abm_regs, 1413 &abm_shift, 1414 &abm_mask); 1415 if (pool->base.abm == NULL) { 1416 dm_error("DC: failed to create abm!\n"); 1417 BREAK_TO_DEBUGGER(); 1418 goto res_create_fail; 1419 } 1420 1421 { 1422 struct irq_service_init_data init_data; 1423 init_data.ctx = dc->ctx; 1424 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1425 if (!pool->base.irqs) 1426 goto res_create_fail; 1427 } 1428 1429 for (i = 0; i < pool->base.pipe_count; i++) { 1430 pool->base.timing_generators[i] = dce60_timing_generator_create( 1431 ctx, i, &dce60_tg_offsets[i]); 1432 if (pool->base.timing_generators[i] == NULL) { 1433 BREAK_TO_DEBUGGER(); 1434 dm_error("DC: failed to create tg!\n"); 1435 goto res_create_fail; 1436 } 1437 1438 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1439 if (pool->base.mis[i] == NULL) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create memory input!\n"); 1442 goto res_create_fail; 1443 } 1444 1445 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1446 if (pool->base.ipps[i] == NULL) { 1447 BREAK_TO_DEBUGGER(); 1448 dm_error("DC: failed to create input pixel processor!\n"); 1449 goto res_create_fail; 1450 } 1451 1452 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1453 if (pool->base.transforms[i] == NULL) { 1454 BREAK_TO_DEBUGGER(); 1455 dm_error("DC: failed to create transform!\n"); 1456 goto res_create_fail; 1457 } 1458 1459 pool->base.opps[i] = dce60_opp_create(ctx, i); 1460 if (pool->base.opps[i] == NULL) { 1461 BREAK_TO_DEBUGGER(); 1462 dm_error("DC: failed to create output pixel processor!\n"); 1463 goto res_create_fail; 1464 } 1465 } 1466 1467 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1468 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1469 if (pool->base.engines[i] == NULL) { 1470 BREAK_TO_DEBUGGER(); 1471 dm_error( 1472 "DC:failed to create aux engine!!\n"); 1473 goto res_create_fail; 1474 } 1475 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1476 if (pool->base.hw_i2cs[i] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error( 1479 "DC:failed to create i2c engine!!\n"); 1480 goto res_create_fail; 1481 } 1482 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1483 if (pool->base.sw_i2cs[i] == NULL) { 1484 BREAK_TO_DEBUGGER(); 1485 dm_error( 1486 "DC:failed to create sw i2c!!\n"); 1487 goto res_create_fail; 1488 } 1489 } 1490 1491 dc->caps.max_planes = pool->base.pipe_count; 1492 1493 for (i = 0; i < dc->caps.max_planes; ++i) 1494 dc->caps.planes[i] = plane_cap; 1495 1496 dc->caps.disable_dp_clk_share = true; 1497 1498 if (!resource_construct(num_virtual_links, dc, &pool->base, 1499 &res_create_funcs)) 1500 goto res_create_fail; 1501 1502 /* Create hardware sequencer */ 1503 dce60_hw_sequencer_construct(dc); 1504 1505 return true; 1506 1507 res_create_fail: 1508 dce60_resource_destruct(pool); 1509 return false; 1510 } 1511 1512 struct resource_pool *dce64_create_resource_pool( 1513 uint8_t num_virtual_links, 1514 struct dc *dc) 1515 { 1516 struct dce110_resource_pool *pool = 1517 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1518 1519 if (!pool) 1520 return NULL; 1521 1522 if (dce64_construct(num_virtual_links, dc, pool)) 1523 return &pool->base; 1524 1525 BREAK_TO_DEBUGGER(); 1526 return NULL; 1527 } 1528