1 /* 2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_6_0_d.h" 29 #include "dce/dce_6_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "include/irq_service_interface.h" 38 #include "irq/dce60/irq_service_dce60.h" 39 #include "dce110/dce110_timing_generator.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce60/dce60_timing_generator.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce/dce_link_encoder.h" 44 #include "dce/dce_stream_encoder.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_transform.h" 47 #include "dce/dce_opp.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce60/dce60_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 #include "dce/dce_panel_cntl.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_dmcu.h" 58 #include "dce/dce_aux.h" 59 #include "dce/dce_abm.h" 60 #include "dce/dce_i2c.h" 61 /* TODO remove this include */ 62 63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 64 #include "gmc/gmc_6_0_d.h" 65 #include "gmc/gmc_6_0_sh_mask.h" 66 #endif 67 68 #ifndef mmDP_DPHY_INTERNAL_CTRL 69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #endif 94 95 96 #ifndef mmHPD_DC_HPD_CONTROL 97 #define mmHPD_DC_HPD_CONTROL 0x189A 98 #define mmHPD0_DC_HPD_CONTROL 0x189A 99 #define mmHPD1_DC_HPD_CONTROL 0x18A2 100 #define mmHPD2_DC_HPD_CONTROL 0x18AA 101 #define mmHPD3_DC_HPD_CONTROL 0x18B2 102 #define mmHPD4_DC_HPD_CONTROL 0x18BA 103 #define mmHPD5_DC_HPD_CONTROL 0x18C2 104 #endif 105 106 #define DCE11_DIG_FE_CNTL 0x4a00 107 #define DCE11_DIG_BE_CNTL 0x4a47 108 #define DCE11_DP_SEC 0x4ac3 109 110 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = { 111 { 112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 114 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 115 - mmDPG_PIPE_ARBITRATION_CONTROL3), 116 }, 117 { 118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 120 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 121 - mmDPG_PIPE_ARBITRATION_CONTROL3), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 127 - mmDPG_PIPE_ARBITRATION_CONTROL3), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 133 - mmDPG_PIPE_ARBITRATION_CONTROL3), 134 }, 135 { 136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 138 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 139 - mmDPG_PIPE_ARBITRATION_CONTROL3), 140 }, 141 { 142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 144 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 145 - mmDPG_PIPE_ARBITRATION_CONTROL3), 146 } 147 }; 148 149 /* set register offset */ 150 #define SR(reg_name)\ 151 .reg_name = mm ## reg_name 152 153 /* set register offset with instance */ 154 #define SRI(reg_name, block, id)\ 155 .reg_name = mm ## block ## id ## _ ## reg_name 156 157 #define ipp_regs(id)\ 158 [id] = {\ 159 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 160 } 161 162 static const struct dce_ipp_registers ipp_regs[] = { 163 ipp_regs(0), 164 ipp_regs(1), 165 ipp_regs(2), 166 ipp_regs(3), 167 ipp_regs(4), 168 ipp_regs(5) 169 }; 170 171 static const struct dce_ipp_shift ipp_shift = { 172 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 173 }; 174 175 static const struct dce_ipp_mask ipp_mask = { 176 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 177 }; 178 179 #define transform_regs(id)\ 180 [id] = {\ 181 XFM_COMMON_REG_LIST_DCE60(id)\ 182 } 183 184 static const struct dce_transform_registers xfm_regs[] = { 185 transform_regs(0), 186 transform_regs(1), 187 transform_regs(2), 188 transform_regs(3), 189 transform_regs(4), 190 transform_regs(5) 191 }; 192 193 static const struct dce_transform_shift xfm_shift = { 194 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT) 195 }; 196 197 static const struct dce_transform_mask xfm_mask = { 198 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK) 199 }; 200 201 #define aux_regs(id)\ 202 [id] = {\ 203 AUX_REG_LIST(id)\ 204 } 205 206 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 207 aux_regs(0), 208 aux_regs(1), 209 aux_regs(2), 210 aux_regs(3), 211 aux_regs(4), 212 aux_regs(5) 213 }; 214 215 #define hpd_regs(id)\ 216 [id] = {\ 217 HPD_REG_LIST(id)\ 218 } 219 220 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 221 hpd_regs(0), 222 hpd_regs(1), 223 hpd_regs(2), 224 hpd_regs(3), 225 hpd_regs(4), 226 hpd_regs(5) 227 }; 228 229 #define link_regs(id)\ 230 [id] = {\ 231 LE_DCE60_REG_LIST(id)\ 232 } 233 234 static const struct dce110_link_enc_registers link_enc_regs[] = { 235 link_regs(0), 236 link_regs(1), 237 link_regs(2), 238 link_regs(3), 239 link_regs(4), 240 link_regs(5) 241 }; 242 243 #define stream_enc_regs(id)\ 244 [id] = {\ 245 SE_COMMON_REG_LIST_DCE_BASE(id),\ 246 .AFMT_CNTL = 0,\ 247 } 248 249 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 250 stream_enc_regs(0), 251 stream_enc_regs(1), 252 stream_enc_regs(2), 253 stream_enc_regs(3), 254 stream_enc_regs(4), 255 stream_enc_regs(5) 256 }; 257 258 static const struct dce_stream_encoder_shift se_shift = { 259 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 260 }; 261 262 static const struct dce_stream_encoder_mask se_mask = { 263 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 264 }; 265 266 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 267 { DCE_PANEL_CNTL_REG_LIST() } 268 }; 269 270 static const struct dce_panel_cntl_shift panel_cntl_shift = { 271 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_panel_cntl_mask panel_cntl_mask = { 275 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_60_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK) 298 }; 299 300 static const struct dce110_aux_registers_shift aux_shift = { 301 DCE10_AUX_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dce110_aux_registers_mask aux_mask = { 305 DCE10_AUX_MASK_SH_LIST(_MASK) 306 }; 307 308 #define aux_engine_regs(id)\ 309 [id] = {\ 310 AUX_COMMON_REG_LIST(id), \ 311 .AUX_RESET_MASK = 0 \ 312 } 313 314 static const struct dce110_aux_registers aux_engine_regs[] = { 315 aux_engine_regs(0), 316 aux_engine_regs(1), 317 aux_engine_regs(2), 318 aux_engine_regs(3), 319 aux_engine_regs(4), 320 aux_engine_regs(5) 321 }; 322 323 #define audio_regs(id)\ 324 [id] = {\ 325 AUD_COMMON_REG_LIST(id)\ 326 } 327 328 static const struct dce_audio_registers audio_regs[] = { 329 audio_regs(0), 330 audio_regs(1), 331 audio_regs(2), 332 audio_regs(3), 333 audio_regs(4), 334 audio_regs(5), 335 }; 336 337 static const struct dce_audio_shift audio_shift = { 338 AUD_DCE60_MASK_SH_LIST(__SHIFT) 339 }; 340 341 static const struct dce_audio_mask audio_mask = { 342 AUD_DCE60_MASK_SH_LIST(_MASK) 343 }; 344 345 #define clk_src_regs(id)\ 346 [id] = {\ 347 CS_COMMON_REG_LIST_DCE_80(id),\ 348 } 349 350 351 static const struct dce110_clk_src_regs clk_src_regs[] = { 352 clk_src_regs(0), 353 clk_src_regs(1), 354 clk_src_regs(2) 355 }; 356 357 static const struct dce110_clk_src_shift cs_shift = { 358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 359 }; 360 361 static const struct dce110_clk_src_mask cs_mask = { 362 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 363 }; 364 365 static const struct bios_registers bios_regs = { 366 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 367 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 368 }; 369 370 static const struct resource_caps res_cap = { 371 .num_timing_generator = 6, 372 .num_audio = 6, 373 .num_stream_encoder = 6, 374 .num_pll = 2, 375 .num_ddc = 6, 376 }; 377 378 static const struct resource_caps res_cap_61 = { 379 .num_timing_generator = 4, 380 .num_audio = 6, 381 .num_stream_encoder = 6, 382 .num_pll = 3, 383 .num_ddc = 6, 384 }; 385 386 static const struct resource_caps res_cap_64 = { 387 .num_timing_generator = 2, 388 .num_audio = 2, 389 .num_stream_encoder = 2, 390 .num_pll = 2, 391 .num_ddc = 2, 392 }; 393 394 static const struct dc_plane_cap plane_cap = { 395 .type = DC_PLANE_TYPE_DCE_RGB, 396 397 .pixel_format_support = { 398 .argb8888 = true, 399 .nv12 = false, 400 .fp16 = false 401 }, 402 403 .max_upscale_factor = { 404 .argb8888 = 16000, 405 .nv12 = 1, 406 .fp16 = 1 407 }, 408 409 .max_downscale_factor = { 410 .argb8888 = 250, 411 .nv12 = 1, 412 .fp16 = 1 413 } 414 }; 415 416 static const struct dce_dmcu_registers dmcu_regs = { 417 DMCU_DCE60_REG_LIST() 418 }; 419 420 static const struct dce_dmcu_shift dmcu_shift = { 421 DMCU_MASK_SH_LIST_DCE60(__SHIFT) 422 }; 423 424 static const struct dce_dmcu_mask dmcu_mask = { 425 DMCU_MASK_SH_LIST_DCE60(_MASK) 426 }; 427 static const struct dce_abm_registers abm_regs = { 428 ABM_DCE110_COMMON_REG_LIST() 429 }; 430 431 static const struct dce_abm_shift abm_shift = { 432 ABM_MASK_SH_LIST_DCE110(__SHIFT) 433 }; 434 435 static const struct dce_abm_mask abm_mask = { 436 ABM_MASK_SH_LIST_DCE110(_MASK) 437 }; 438 439 #define CTX ctx 440 #define REG(reg) mm ## reg 441 442 #ifndef mmCC_DC_HDMI_STRAPS 443 #define mmCC_DC_HDMI_STRAPS 0x1918 444 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 446 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 448 #endif 449 450 static int map_transmitter_id_to_phy_instance( 451 enum transmitter transmitter) 452 { 453 switch (transmitter) { 454 case TRANSMITTER_UNIPHY_A: 455 return 0; 456 case TRANSMITTER_UNIPHY_B: 457 return 1; 458 case TRANSMITTER_UNIPHY_C: 459 return 2; 460 case TRANSMITTER_UNIPHY_D: 461 return 3; 462 case TRANSMITTER_UNIPHY_E: 463 return 4; 464 case TRANSMITTER_UNIPHY_F: 465 return 5; 466 case TRANSMITTER_UNIPHY_G: 467 return 6; 468 default: 469 ASSERT(0); 470 return 0; 471 } 472 } 473 474 static void read_dce_straps( 475 struct dc_context *ctx, 476 struct resource_straps *straps) 477 { 478 REG_GET_2(CC_DC_HDMI_STRAPS, 479 HDMI_DISABLE, &straps->hdmi_disable, 480 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 481 482 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 483 } 484 485 static struct audio *create_audio( 486 struct dc_context *ctx, unsigned int inst) 487 { 488 return dce60_audio_create(ctx, inst, 489 &audio_regs[inst], &audio_shift, &audio_mask); 490 } 491 492 static struct timing_generator *dce60_timing_generator_create( 493 struct dc_context *ctx, 494 uint32_t instance, 495 const struct dce110_timing_generator_offsets *offsets) 496 { 497 struct dce110_timing_generator *tg110 = 498 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 499 500 if (!tg110) 501 return NULL; 502 503 dce60_timing_generator_construct(tg110, ctx, instance, offsets); 504 return &tg110->base; 505 } 506 507 static struct output_pixel_processor *dce60_opp_create( 508 struct dc_context *ctx, 509 uint32_t inst) 510 { 511 struct dce110_opp *opp = 512 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 513 514 if (!opp) 515 return NULL; 516 517 dce60_opp_construct(opp, 518 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 519 return &opp->base; 520 } 521 522 struct dce_aux *dce60_aux_engine_create( 523 struct dc_context *ctx, 524 uint32_t inst) 525 { 526 struct aux_engine_dce110 *aux_engine = 527 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 528 529 if (!aux_engine) 530 return NULL; 531 532 dce110_aux_engine_construct(aux_engine, ctx, inst, 533 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 534 &aux_engine_regs[inst], 535 &aux_mask, 536 &aux_shift, 537 ctx->dc->caps.extended_aux_timeout_support); 538 539 return &aux_engine->base; 540 } 541 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 542 543 static const struct dce_i2c_registers i2c_hw_regs[] = { 544 i2c_inst_regs(1), 545 i2c_inst_regs(2), 546 i2c_inst_regs(3), 547 i2c_inst_regs(4), 548 i2c_inst_regs(5), 549 i2c_inst_regs(6), 550 }; 551 552 static const struct dce_i2c_shift i2c_shifts = { 553 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 554 }; 555 556 static const struct dce_i2c_mask i2c_masks = { 557 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 558 }; 559 560 struct dce_i2c_hw *dce60_i2c_hw_create( 561 struct dc_context *ctx, 562 uint32_t inst) 563 { 564 struct dce_i2c_hw *dce_i2c_hw = 565 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 566 567 if (!dce_i2c_hw) 568 return NULL; 569 570 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 571 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 572 573 return dce_i2c_hw; 574 } 575 576 struct dce_i2c_sw *dce60_i2c_sw_create( 577 struct dc_context *ctx) 578 { 579 struct dce_i2c_sw *dce_i2c_sw = 580 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 581 582 if (!dce_i2c_sw) 583 return NULL; 584 585 dce_i2c_sw_construct(dce_i2c_sw, ctx); 586 587 return dce_i2c_sw; 588 } 589 static struct stream_encoder *dce60_stream_encoder_create( 590 enum engine_id eng_id, 591 struct dc_context *ctx) 592 { 593 struct dce110_stream_encoder *enc110 = 594 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 595 596 if (!enc110) 597 return NULL; 598 599 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 600 &stream_enc_regs[eng_id], 601 &se_shift, &se_mask); 602 return &enc110->base; 603 } 604 605 #define SRII(reg_name, block, id)\ 606 .reg_name[id] = mm ## block ## id ## _ ## reg_name 607 608 static const struct dce_hwseq_registers hwseq_reg = { 609 HWSEQ_DCE6_REG_LIST() 610 }; 611 612 static const struct dce_hwseq_shift hwseq_shift = { 613 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT) 614 }; 615 616 static const struct dce_hwseq_mask hwseq_mask = { 617 HWSEQ_DCE6_MASK_SH_LIST(_MASK) 618 }; 619 620 static struct dce_hwseq *dce60_hwseq_create( 621 struct dc_context *ctx) 622 { 623 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 624 625 if (hws) { 626 hws->ctx = ctx; 627 hws->regs = &hwseq_reg; 628 hws->shifts = &hwseq_shift; 629 hws->masks = &hwseq_mask; 630 } 631 return hws; 632 } 633 634 static const struct resource_create_funcs res_create_funcs = { 635 .read_dce_straps = read_dce_straps, 636 .create_audio = create_audio, 637 .create_stream_encoder = dce60_stream_encoder_create, 638 .create_hwseq = dce60_hwseq_create, 639 }; 640 641 #define mi_inst_regs(id) { \ 642 MI_DCE6_REG_LIST(id), \ 643 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 644 } 645 static const struct dce_mem_input_registers mi_regs[] = { 646 mi_inst_regs(0), 647 mi_inst_regs(1), 648 mi_inst_regs(2), 649 mi_inst_regs(3), 650 mi_inst_regs(4), 651 mi_inst_regs(5), 652 }; 653 654 static const struct dce_mem_input_shift mi_shifts = { 655 MI_DCE6_MASK_SH_LIST(__SHIFT), 656 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 657 }; 658 659 static const struct dce_mem_input_mask mi_masks = { 660 MI_DCE6_MASK_SH_LIST(_MASK), 661 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 662 }; 663 664 static struct mem_input *dce60_mem_input_create( 665 struct dc_context *ctx, 666 uint32_t inst) 667 { 668 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 669 GFP_KERNEL); 670 671 if (!dce_mi) { 672 BREAK_TO_DEBUGGER(); 673 return NULL; 674 } 675 676 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 677 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 678 return &dce_mi->base; 679 } 680 681 static void dce60_transform_destroy(struct transform **xfm) 682 { 683 kfree(TO_DCE_TRANSFORM(*xfm)); 684 *xfm = NULL; 685 } 686 687 static struct transform *dce60_transform_create( 688 struct dc_context *ctx, 689 uint32_t inst) 690 { 691 struct dce_transform *transform = 692 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 693 694 if (!transform) 695 return NULL; 696 697 dce60_transform_construct(transform, ctx, inst, 698 &xfm_regs[inst], &xfm_shift, &xfm_mask); 699 transform->prescaler_on = false; 700 return &transform->base; 701 } 702 703 static const struct encoder_feature_support link_enc_feature = { 704 .max_hdmi_deep_color = COLOR_DEPTH_121212, 705 .max_hdmi_pixel_clock = 297000, 706 .flags.bits.IS_HBR2_CAPABLE = true, 707 .flags.bits.IS_TPS3_CAPABLE = true 708 }; 709 710 struct link_encoder *dce60_link_encoder_create( 711 const struct encoder_init_data *enc_init_data) 712 { 713 struct dce110_link_encoder *enc110 = 714 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 715 int link_regs_id; 716 717 if (!enc110) 718 return NULL; 719 720 link_regs_id = 721 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 722 723 dce60_link_encoder_construct(enc110, 724 enc_init_data, 725 &link_enc_feature, 726 &link_enc_regs[link_regs_id], 727 &link_enc_aux_regs[enc_init_data->channel - 1], 728 &link_enc_hpd_regs[enc_init_data->hpd_source]); 729 return &enc110->base; 730 } 731 732 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data) 733 { 734 struct dce_panel_cntl *panel_cntl = 735 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 736 737 if (!panel_cntl) 738 return NULL; 739 740 dce_panel_cntl_construct(panel_cntl, 741 init_data, 742 &panel_cntl_regs[init_data->inst], 743 &panel_cntl_shift, 744 &panel_cntl_mask); 745 746 return &panel_cntl->base; 747 } 748 749 struct clock_source *dce60_clock_source_create( 750 struct dc_context *ctx, 751 struct dc_bios *bios, 752 enum clock_source_id id, 753 const struct dce110_clk_src_regs *regs, 754 bool dp_clk_src) 755 { 756 struct dce110_clk_src *clk_src = 757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 758 759 if (!clk_src) 760 return NULL; 761 762 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 763 regs, &cs_shift, &cs_mask)) { 764 clk_src->base.dp_clk_src = dp_clk_src; 765 return &clk_src->base; 766 } 767 768 kfree(clk_src); 769 BREAK_TO_DEBUGGER(); 770 return NULL; 771 } 772 773 void dce60_clock_source_destroy(struct clock_source **clk_src) 774 { 775 kfree(TO_DCE110_CLK_SRC(*clk_src)); 776 *clk_src = NULL; 777 } 778 779 static struct input_pixel_processor *dce60_ipp_create( 780 struct dc_context *ctx, uint32_t inst) 781 { 782 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 783 784 if (!ipp) { 785 BREAK_TO_DEBUGGER(); 786 return NULL; 787 } 788 789 dce60_ipp_construct(ipp, ctx, inst, 790 &ipp_regs[inst], &ipp_shift, &ipp_mask); 791 return &ipp->base; 792 } 793 794 static void dce60_resource_destruct(struct dce110_resource_pool *pool) 795 { 796 unsigned int i; 797 798 for (i = 0; i < pool->base.pipe_count; i++) { 799 if (pool->base.opps[i] != NULL) 800 dce110_opp_destroy(&pool->base.opps[i]); 801 802 if (pool->base.transforms[i] != NULL) 803 dce60_transform_destroy(&pool->base.transforms[i]); 804 805 if (pool->base.ipps[i] != NULL) 806 dce_ipp_destroy(&pool->base.ipps[i]); 807 808 if (pool->base.mis[i] != NULL) { 809 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 810 pool->base.mis[i] = NULL; 811 } 812 813 if (pool->base.timing_generators[i] != NULL) { 814 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 815 pool->base.timing_generators[i] = NULL; 816 } 817 } 818 819 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 820 if (pool->base.engines[i] != NULL) 821 dce110_engine_destroy(&pool->base.engines[i]); 822 if (pool->base.hw_i2cs[i] != NULL) { 823 kfree(pool->base.hw_i2cs[i]); 824 pool->base.hw_i2cs[i] = NULL; 825 } 826 if (pool->base.sw_i2cs[i] != NULL) { 827 kfree(pool->base.sw_i2cs[i]); 828 pool->base.sw_i2cs[i] = NULL; 829 } 830 } 831 832 for (i = 0; i < pool->base.stream_enc_count; i++) { 833 if (pool->base.stream_enc[i] != NULL) 834 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 835 } 836 837 for (i = 0; i < pool->base.clk_src_count; i++) { 838 if (pool->base.clock_sources[i] != NULL) { 839 dce60_clock_source_destroy(&pool->base.clock_sources[i]); 840 } 841 } 842 843 if (pool->base.abm != NULL) 844 dce_abm_destroy(&pool->base.abm); 845 846 if (pool->base.dmcu != NULL) 847 dce_dmcu_destroy(&pool->base.dmcu); 848 849 if (pool->base.dp_clock_source != NULL) 850 dce60_clock_source_destroy(&pool->base.dp_clock_source); 851 852 for (i = 0; i < pool->base.audio_count; i++) { 853 if (pool->base.audios[i] != NULL) { 854 dce_aud_destroy(&pool->base.audios[i]); 855 } 856 } 857 858 if (pool->base.irqs != NULL) { 859 dal_irq_service_destroy(&pool->base.irqs); 860 } 861 } 862 863 bool dce60_validate_bandwidth( 864 struct dc *dc, 865 struct dc_state *context, 866 bool fast_validate) 867 { 868 int i; 869 bool at_least_one_pipe = false; 870 871 for (i = 0; i < dc->res_pool->pipe_count; i++) { 872 if (context->res_ctx.pipe_ctx[i].stream) 873 at_least_one_pipe = true; 874 } 875 876 if (at_least_one_pipe) { 877 /* TODO implement when needed but for now hardcode max value*/ 878 context->bw_ctx.bw.dce.dispclk_khz = 681000; 879 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 880 } else { 881 context->bw_ctx.bw.dce.dispclk_khz = 0; 882 context->bw_ctx.bw.dce.yclk_khz = 0; 883 } 884 885 return true; 886 } 887 888 static bool dce60_validate_surface_sets( 889 struct dc_state *context) 890 { 891 int i; 892 893 for (i = 0; i < context->stream_count; i++) { 894 if (context->stream_status[i].plane_count == 0) 895 continue; 896 897 if (context->stream_status[i].plane_count > 1) 898 return false; 899 900 if (context->stream_status[i].plane_states[0]->format 901 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 902 return false; 903 } 904 905 return true; 906 } 907 908 enum dc_status dce60_validate_global( 909 struct dc *dc, 910 struct dc_state *context) 911 { 912 if (!dce60_validate_surface_sets(context)) 913 return DC_FAIL_SURFACE_VALIDATE; 914 915 return DC_OK; 916 } 917 918 static void dce60_destroy_resource_pool(struct resource_pool **pool) 919 { 920 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 921 922 dce60_resource_destruct(dce110_pool); 923 kfree(dce110_pool); 924 *pool = NULL; 925 } 926 927 static const struct resource_funcs dce60_res_pool_funcs = { 928 .destroy = dce60_destroy_resource_pool, 929 .link_enc_create = dce60_link_encoder_create, 930 .panel_cntl_create = dce60_panel_cntl_create, 931 .validate_bandwidth = dce60_validate_bandwidth, 932 .validate_plane = dce100_validate_plane, 933 .add_stream_to_ctx = dce100_add_stream_to_ctx, 934 .validate_global = dce60_validate_global, 935 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 936 }; 937 938 static bool dce60_construct( 939 uint8_t num_virtual_links, 940 struct dc *dc, 941 struct dce110_resource_pool *pool) 942 { 943 unsigned int i; 944 struct dc_context *ctx = dc->ctx; 945 struct dc_bios *bp; 946 947 ctx->dc_bios->regs = &bios_regs; 948 949 pool->base.res_cap = &res_cap; 950 pool->base.funcs = &dce60_res_pool_funcs; 951 952 953 /************************************************* 954 * Resource + asic cap harcoding * 955 *************************************************/ 956 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 957 pool->base.pipe_count = res_cap.num_timing_generator; 958 pool->base.timing_generator_count = res_cap.num_timing_generator; 959 dc->caps.max_downscale_ratio = 200; 960 dc->caps.i2c_speed_in_khz = 40; 961 dc->caps.max_cursor_size = 64; 962 dc->caps.dual_link_dvi = true; 963 dc->caps.extended_aux_timeout_support = false; 964 965 /************************************************* 966 * Create resources * 967 *************************************************/ 968 969 bp = ctx->dc_bios; 970 971 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 972 pool->base.dp_clock_source = 973 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 974 975 pool->base.clock_sources[0] = 976 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 977 pool->base.clock_sources[1] = 978 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 979 pool->base.clk_src_count = 2; 980 981 } else { 982 pool->base.dp_clock_source = 983 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 984 985 pool->base.clock_sources[0] = 986 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 987 pool->base.clk_src_count = 1; 988 } 989 990 if (pool->base.dp_clock_source == NULL) { 991 dm_error("DC: failed to create dp clock source!\n"); 992 BREAK_TO_DEBUGGER(); 993 goto res_create_fail; 994 } 995 996 for (i = 0; i < pool->base.clk_src_count; i++) { 997 if (pool->base.clock_sources[i] == NULL) { 998 dm_error("DC: failed to create clock sources!\n"); 999 BREAK_TO_DEBUGGER(); 1000 goto res_create_fail; 1001 } 1002 } 1003 1004 pool->base.dmcu = dce_dmcu_create(ctx, 1005 &dmcu_regs, 1006 &dmcu_shift, 1007 &dmcu_mask); 1008 if (pool->base.dmcu == NULL) { 1009 dm_error("DC: failed to create dmcu!\n"); 1010 BREAK_TO_DEBUGGER(); 1011 goto res_create_fail; 1012 } 1013 1014 pool->base.abm = dce_abm_create(ctx, 1015 &abm_regs, 1016 &abm_shift, 1017 &abm_mask); 1018 if (pool->base.abm == NULL) { 1019 dm_error("DC: failed to create abm!\n"); 1020 BREAK_TO_DEBUGGER(); 1021 goto res_create_fail; 1022 } 1023 1024 { 1025 struct irq_service_init_data init_data; 1026 init_data.ctx = dc->ctx; 1027 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1028 if (!pool->base.irqs) 1029 goto res_create_fail; 1030 } 1031 1032 for (i = 0; i < pool->base.pipe_count; i++) { 1033 pool->base.timing_generators[i] = dce60_timing_generator_create( 1034 ctx, i, &dce60_tg_offsets[i]); 1035 if (pool->base.timing_generators[i] == NULL) { 1036 BREAK_TO_DEBUGGER(); 1037 dm_error("DC: failed to create tg!\n"); 1038 goto res_create_fail; 1039 } 1040 1041 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1042 if (pool->base.mis[i] == NULL) { 1043 BREAK_TO_DEBUGGER(); 1044 dm_error("DC: failed to create memory input!\n"); 1045 goto res_create_fail; 1046 } 1047 1048 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1049 if (pool->base.ipps[i] == NULL) { 1050 BREAK_TO_DEBUGGER(); 1051 dm_error("DC: failed to create input pixel processor!\n"); 1052 goto res_create_fail; 1053 } 1054 1055 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1056 if (pool->base.transforms[i] == NULL) { 1057 BREAK_TO_DEBUGGER(); 1058 dm_error("DC: failed to create transform!\n"); 1059 goto res_create_fail; 1060 } 1061 1062 pool->base.opps[i] = dce60_opp_create(ctx, i); 1063 if (pool->base.opps[i] == NULL) { 1064 BREAK_TO_DEBUGGER(); 1065 dm_error("DC: failed to create output pixel processor!\n"); 1066 goto res_create_fail; 1067 } 1068 } 1069 1070 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1071 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1072 if (pool->base.engines[i] == NULL) { 1073 BREAK_TO_DEBUGGER(); 1074 dm_error( 1075 "DC:failed to create aux engine!!\n"); 1076 goto res_create_fail; 1077 } 1078 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1079 if (pool->base.hw_i2cs[i] == NULL) { 1080 BREAK_TO_DEBUGGER(); 1081 dm_error( 1082 "DC:failed to create i2c engine!!\n"); 1083 goto res_create_fail; 1084 } 1085 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1086 if (pool->base.sw_i2cs[i] == NULL) { 1087 BREAK_TO_DEBUGGER(); 1088 dm_error( 1089 "DC:failed to create sw i2c!!\n"); 1090 goto res_create_fail; 1091 } 1092 } 1093 1094 dc->caps.max_planes = pool->base.pipe_count; 1095 1096 for (i = 0; i < dc->caps.max_planes; ++i) 1097 dc->caps.planes[i] = plane_cap; 1098 1099 dc->caps.disable_dp_clk_share = true; 1100 1101 if (!resource_construct(num_virtual_links, dc, &pool->base, 1102 &res_create_funcs)) 1103 goto res_create_fail; 1104 1105 /* Create hardware sequencer */ 1106 dce60_hw_sequencer_construct(dc); 1107 1108 return true; 1109 1110 res_create_fail: 1111 dce60_resource_destruct(pool); 1112 return false; 1113 } 1114 1115 struct resource_pool *dce60_create_resource_pool( 1116 uint8_t num_virtual_links, 1117 struct dc *dc) 1118 { 1119 struct dce110_resource_pool *pool = 1120 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1121 1122 if (!pool) 1123 return NULL; 1124 1125 if (dce60_construct(num_virtual_links, dc, pool)) 1126 return &pool->base; 1127 1128 BREAK_TO_DEBUGGER(); 1129 return NULL; 1130 } 1131 1132 static bool dce61_construct( 1133 uint8_t num_virtual_links, 1134 struct dc *dc, 1135 struct dce110_resource_pool *pool) 1136 { 1137 unsigned int i; 1138 struct dc_context *ctx = dc->ctx; 1139 struct dc_bios *bp; 1140 1141 ctx->dc_bios->regs = &bios_regs; 1142 1143 pool->base.res_cap = &res_cap_61; 1144 pool->base.funcs = &dce60_res_pool_funcs; 1145 1146 1147 /************************************************* 1148 * Resource + asic cap harcoding * 1149 *************************************************/ 1150 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1151 pool->base.pipe_count = res_cap_61.num_timing_generator; 1152 pool->base.timing_generator_count = res_cap_61.num_timing_generator; 1153 dc->caps.max_downscale_ratio = 200; 1154 dc->caps.i2c_speed_in_khz = 40; 1155 dc->caps.max_cursor_size = 64; 1156 dc->caps.is_apu = true; 1157 1158 /************************************************* 1159 * Create resources * 1160 *************************************************/ 1161 1162 bp = ctx->dc_bios; 1163 1164 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1165 pool->base.dp_clock_source = 1166 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1167 1168 pool->base.clock_sources[0] = 1169 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1170 pool->base.clock_sources[1] = 1171 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1172 pool->base.clock_sources[2] = 1173 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1174 pool->base.clk_src_count = 3; 1175 1176 } else { 1177 pool->base.dp_clock_source = 1178 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1179 1180 pool->base.clock_sources[0] = 1181 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1182 pool->base.clock_sources[1] = 1183 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1184 pool->base.clk_src_count = 2; 1185 } 1186 1187 if (pool->base.dp_clock_source == NULL) { 1188 dm_error("DC: failed to create dp clock source!\n"); 1189 BREAK_TO_DEBUGGER(); 1190 goto res_create_fail; 1191 } 1192 1193 for (i = 0; i < pool->base.clk_src_count; i++) { 1194 if (pool->base.clock_sources[i] == NULL) { 1195 dm_error("DC: failed to create clock sources!\n"); 1196 BREAK_TO_DEBUGGER(); 1197 goto res_create_fail; 1198 } 1199 } 1200 1201 pool->base.dmcu = dce_dmcu_create(ctx, 1202 &dmcu_regs, 1203 &dmcu_shift, 1204 &dmcu_mask); 1205 if (pool->base.dmcu == NULL) { 1206 dm_error("DC: failed to create dmcu!\n"); 1207 BREAK_TO_DEBUGGER(); 1208 goto res_create_fail; 1209 } 1210 1211 pool->base.abm = dce_abm_create(ctx, 1212 &abm_regs, 1213 &abm_shift, 1214 &abm_mask); 1215 if (pool->base.abm == NULL) { 1216 dm_error("DC: failed to create abm!\n"); 1217 BREAK_TO_DEBUGGER(); 1218 goto res_create_fail; 1219 } 1220 1221 { 1222 struct irq_service_init_data init_data; 1223 init_data.ctx = dc->ctx; 1224 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1225 if (!pool->base.irqs) 1226 goto res_create_fail; 1227 } 1228 1229 for (i = 0; i < pool->base.pipe_count; i++) { 1230 pool->base.timing_generators[i] = dce60_timing_generator_create( 1231 ctx, i, &dce60_tg_offsets[i]); 1232 if (pool->base.timing_generators[i] == NULL) { 1233 BREAK_TO_DEBUGGER(); 1234 dm_error("DC: failed to create tg!\n"); 1235 goto res_create_fail; 1236 } 1237 1238 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1239 if (pool->base.mis[i] == NULL) { 1240 BREAK_TO_DEBUGGER(); 1241 dm_error("DC: failed to create memory input!\n"); 1242 goto res_create_fail; 1243 } 1244 1245 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1246 if (pool->base.ipps[i] == NULL) { 1247 BREAK_TO_DEBUGGER(); 1248 dm_error("DC: failed to create input pixel processor!\n"); 1249 goto res_create_fail; 1250 } 1251 1252 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1253 if (pool->base.transforms[i] == NULL) { 1254 BREAK_TO_DEBUGGER(); 1255 dm_error("DC: failed to create transform!\n"); 1256 goto res_create_fail; 1257 } 1258 1259 pool->base.opps[i] = dce60_opp_create(ctx, i); 1260 if (pool->base.opps[i] == NULL) { 1261 BREAK_TO_DEBUGGER(); 1262 dm_error("DC: failed to create output pixel processor!\n"); 1263 goto res_create_fail; 1264 } 1265 } 1266 1267 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1268 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1269 if (pool->base.engines[i] == NULL) { 1270 BREAK_TO_DEBUGGER(); 1271 dm_error( 1272 "DC:failed to create aux engine!!\n"); 1273 goto res_create_fail; 1274 } 1275 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1276 if (pool->base.hw_i2cs[i] == NULL) { 1277 BREAK_TO_DEBUGGER(); 1278 dm_error( 1279 "DC:failed to create i2c engine!!\n"); 1280 goto res_create_fail; 1281 } 1282 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1283 if (pool->base.sw_i2cs[i] == NULL) { 1284 BREAK_TO_DEBUGGER(); 1285 dm_error( 1286 "DC:failed to create sw i2c!!\n"); 1287 goto res_create_fail; 1288 } 1289 } 1290 1291 dc->caps.max_planes = pool->base.pipe_count; 1292 1293 for (i = 0; i < dc->caps.max_planes; ++i) 1294 dc->caps.planes[i] = plane_cap; 1295 1296 dc->caps.disable_dp_clk_share = true; 1297 1298 if (!resource_construct(num_virtual_links, dc, &pool->base, 1299 &res_create_funcs)) 1300 goto res_create_fail; 1301 1302 /* Create hardware sequencer */ 1303 dce60_hw_sequencer_construct(dc); 1304 1305 return true; 1306 1307 res_create_fail: 1308 dce60_resource_destruct(pool); 1309 return false; 1310 } 1311 1312 struct resource_pool *dce61_create_resource_pool( 1313 uint8_t num_virtual_links, 1314 struct dc *dc) 1315 { 1316 struct dce110_resource_pool *pool = 1317 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1318 1319 if (!pool) 1320 return NULL; 1321 1322 if (dce61_construct(num_virtual_links, dc, pool)) 1323 return &pool->base; 1324 1325 BREAK_TO_DEBUGGER(); 1326 return NULL; 1327 } 1328 1329 static bool dce64_construct( 1330 uint8_t num_virtual_links, 1331 struct dc *dc, 1332 struct dce110_resource_pool *pool) 1333 { 1334 unsigned int i; 1335 struct dc_context *ctx = dc->ctx; 1336 struct dc_bios *bp; 1337 1338 ctx->dc_bios->regs = &bios_regs; 1339 1340 pool->base.res_cap = &res_cap_64; 1341 pool->base.funcs = &dce60_res_pool_funcs; 1342 1343 1344 /************************************************* 1345 * Resource + asic cap harcoding * 1346 *************************************************/ 1347 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1348 pool->base.pipe_count = res_cap_64.num_timing_generator; 1349 pool->base.timing_generator_count = res_cap_64.num_timing_generator; 1350 dc->caps.max_downscale_ratio = 200; 1351 dc->caps.i2c_speed_in_khz = 40; 1352 dc->caps.max_cursor_size = 64; 1353 dc->caps.is_apu = true; 1354 1355 /************************************************* 1356 * Create resources * 1357 *************************************************/ 1358 1359 bp = ctx->dc_bios; 1360 1361 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1362 pool->base.dp_clock_source = 1363 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1364 1365 pool->base.clock_sources[0] = 1366 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1367 pool->base.clock_sources[1] = 1368 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1369 pool->base.clk_src_count = 2; 1370 1371 } else { 1372 pool->base.dp_clock_source = 1373 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1374 1375 pool->base.clock_sources[0] = 1376 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1377 pool->base.clk_src_count = 1; 1378 } 1379 1380 if (pool->base.dp_clock_source == NULL) { 1381 dm_error("DC: failed to create dp clock source!\n"); 1382 BREAK_TO_DEBUGGER(); 1383 goto res_create_fail; 1384 } 1385 1386 for (i = 0; i < pool->base.clk_src_count; i++) { 1387 if (pool->base.clock_sources[i] == NULL) { 1388 dm_error("DC: failed to create clock sources!\n"); 1389 BREAK_TO_DEBUGGER(); 1390 goto res_create_fail; 1391 } 1392 } 1393 1394 pool->base.dmcu = dce_dmcu_create(ctx, 1395 &dmcu_regs, 1396 &dmcu_shift, 1397 &dmcu_mask); 1398 if (pool->base.dmcu == NULL) { 1399 dm_error("DC: failed to create dmcu!\n"); 1400 BREAK_TO_DEBUGGER(); 1401 goto res_create_fail; 1402 } 1403 1404 pool->base.abm = dce_abm_create(ctx, 1405 &abm_regs, 1406 &abm_shift, 1407 &abm_mask); 1408 if (pool->base.abm == NULL) { 1409 dm_error("DC: failed to create abm!\n"); 1410 BREAK_TO_DEBUGGER(); 1411 goto res_create_fail; 1412 } 1413 1414 { 1415 struct irq_service_init_data init_data; 1416 init_data.ctx = dc->ctx; 1417 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1418 if (!pool->base.irqs) 1419 goto res_create_fail; 1420 } 1421 1422 for (i = 0; i < pool->base.pipe_count; i++) { 1423 pool->base.timing_generators[i] = dce60_timing_generator_create( 1424 ctx, i, &dce60_tg_offsets[i]); 1425 if (pool->base.timing_generators[i] == NULL) { 1426 BREAK_TO_DEBUGGER(); 1427 dm_error("DC: failed to create tg!\n"); 1428 goto res_create_fail; 1429 } 1430 1431 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1432 if (pool->base.mis[i] == NULL) { 1433 BREAK_TO_DEBUGGER(); 1434 dm_error("DC: failed to create memory input!\n"); 1435 goto res_create_fail; 1436 } 1437 1438 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1439 if (pool->base.ipps[i] == NULL) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create input pixel processor!\n"); 1442 goto res_create_fail; 1443 } 1444 1445 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1446 if (pool->base.transforms[i] == NULL) { 1447 BREAK_TO_DEBUGGER(); 1448 dm_error("DC: failed to create transform!\n"); 1449 goto res_create_fail; 1450 } 1451 1452 pool->base.opps[i] = dce60_opp_create(ctx, i); 1453 if (pool->base.opps[i] == NULL) { 1454 BREAK_TO_DEBUGGER(); 1455 dm_error("DC: failed to create output pixel processor!\n"); 1456 goto res_create_fail; 1457 } 1458 } 1459 1460 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1461 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1462 if (pool->base.engines[i] == NULL) { 1463 BREAK_TO_DEBUGGER(); 1464 dm_error( 1465 "DC:failed to create aux engine!!\n"); 1466 goto res_create_fail; 1467 } 1468 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1469 if (pool->base.hw_i2cs[i] == NULL) { 1470 BREAK_TO_DEBUGGER(); 1471 dm_error( 1472 "DC:failed to create i2c engine!!\n"); 1473 goto res_create_fail; 1474 } 1475 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1476 if (pool->base.sw_i2cs[i] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error( 1479 "DC:failed to create sw i2c!!\n"); 1480 goto res_create_fail; 1481 } 1482 } 1483 1484 dc->caps.max_planes = pool->base.pipe_count; 1485 1486 for (i = 0; i < dc->caps.max_planes; ++i) 1487 dc->caps.planes[i] = plane_cap; 1488 1489 dc->caps.disable_dp_clk_share = true; 1490 1491 if (!resource_construct(num_virtual_links, dc, &pool->base, 1492 &res_create_funcs)) 1493 goto res_create_fail; 1494 1495 /* Create hardware sequencer */ 1496 dce60_hw_sequencer_construct(dc); 1497 1498 return true; 1499 1500 res_create_fail: 1501 dce60_resource_destruct(pool); 1502 return false; 1503 } 1504 1505 struct resource_pool *dce64_create_resource_pool( 1506 uint8_t num_virtual_links, 1507 struct dc *dc) 1508 { 1509 struct dce110_resource_pool *pool = 1510 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1511 1512 if (!pool) 1513 return NULL; 1514 1515 if (dce64_construct(num_virtual_links, dc, pool)) 1516 return &pool->base; 1517 1518 BREAK_TO_DEBUGGER(); 1519 return NULL; 1520 } 1521