1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 #include "clk_mgr.h" 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_i2c.h" 58 59 #include "dce/dce_12_0_offset.h" 60 #include "dce/dce_12_0_sh_mask.h" 61 #include "soc15_hw_ip.h" 62 #include "vega10_ip_offset.h" 63 #include "nbio/nbio_6_1_offset.h" 64 #include "mmhub/mmhub_9_4_0_offset.h" 65 #include "mmhub/mmhub_9_4_0_sh_mask.h" 66 #include "reg_helper.h" 67 68 #include "dce100/dce100_resource.h" 69 70 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 71 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 83 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 85 #endif 86 87 enum dce120_clk_src_array_id { 88 DCE120_CLK_SRC_PLL0, 89 DCE120_CLK_SRC_PLL1, 90 DCE120_CLK_SRC_PLL2, 91 DCE120_CLK_SRC_PLL3, 92 DCE120_CLK_SRC_PLL4, 93 DCE120_CLK_SRC_PLL5, 94 95 DCE120_CLK_SRC_TOTAL 96 }; 97 98 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 99 { 100 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 101 }, 102 { 103 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 104 }, 105 { 106 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 113 }, 114 { 115 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 116 } 117 }; 118 119 /* begin ********************* 120 * macros to expend register list macro defined in HW object header file */ 121 122 #define BASE_INNER(seg) \ 123 DCE_BASE__INST0_SEG ## seg 124 125 #define NBIO_BASE_INNER(seg) \ 126 NBIF_BASE__INST0_SEG ## seg 127 128 #define NBIO_BASE(seg) \ 129 NBIO_BASE_INNER(seg) 130 131 /* compile time expand base address. */ 132 #define BASE(seg) \ 133 BASE_INNER(seg) 134 135 #define SR(reg_name)\ 136 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 137 mm ## reg_name 138 139 #define SRI(reg_name, block, id)\ 140 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 mm ## block ## id ## _ ## reg_name 142 143 /* MMHUB */ 144 #define MMHUB_BASE_INNER(seg) \ 145 MMHUB_BASE__INST0_SEG ## seg 146 147 #define MMHUB_BASE(seg) \ 148 MMHUB_BASE_INNER(seg) 149 150 #define MMHUB_SR(reg_name)\ 151 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 152 mm ## reg_name 153 154 /* macros to expend register list macro defined in HW object header file 155 * end *********************/ 156 157 158 static const struct dce_dmcu_registers dmcu_regs = { 159 DMCU_DCE110_COMMON_REG_LIST() 160 }; 161 162 static const struct dce_dmcu_shift dmcu_shift = { 163 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 164 }; 165 166 static const struct dce_dmcu_mask dmcu_mask = { 167 DMCU_MASK_SH_LIST_DCE110(_MASK) 168 }; 169 170 static const struct dce_abm_registers abm_regs = { 171 ABM_DCE110_COMMON_REG_LIST() 172 }; 173 174 static const struct dce_abm_shift abm_shift = { 175 ABM_MASK_SH_LIST_DCE110(__SHIFT) 176 }; 177 178 static const struct dce_abm_mask abm_mask = { 179 ABM_MASK_SH_LIST_DCE110(_MASK) 180 }; 181 182 #define ipp_regs(id)\ 183 [id] = {\ 184 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 185 } 186 187 static const struct dce_ipp_registers ipp_regs[] = { 188 ipp_regs(0), 189 ipp_regs(1), 190 ipp_regs(2), 191 ipp_regs(3), 192 ipp_regs(4), 193 ipp_regs(5) 194 }; 195 196 static const struct dce_ipp_shift ipp_shift = { 197 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 198 }; 199 200 static const struct dce_ipp_mask ipp_mask = { 201 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 202 }; 203 204 #define transform_regs(id)\ 205 [id] = {\ 206 XFM_COMMON_REG_LIST_DCE110(id)\ 207 } 208 209 static const struct dce_transform_registers xfm_regs[] = { 210 transform_regs(0), 211 transform_regs(1), 212 transform_regs(2), 213 transform_regs(3), 214 transform_regs(4), 215 transform_regs(5) 216 }; 217 218 static const struct dce_transform_shift xfm_shift = { 219 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 220 }; 221 222 static const struct dce_transform_mask xfm_mask = { 223 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 224 }; 225 226 #define aux_regs(id)\ 227 [id] = {\ 228 AUX_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 232 aux_regs(0), 233 aux_regs(1), 234 aux_regs(2), 235 aux_regs(3), 236 aux_regs(4), 237 aux_regs(5) 238 }; 239 240 #define hpd_regs(id)\ 241 [id] = {\ 242 HPD_REG_LIST(id)\ 243 } 244 245 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 246 hpd_regs(0), 247 hpd_regs(1), 248 hpd_regs(2), 249 hpd_regs(3), 250 hpd_regs(4), 251 hpd_regs(5) 252 }; 253 254 #define link_regs(id)\ 255 [id] = {\ 256 LE_DCE120_REG_LIST(id), \ 257 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 271 #define stream_enc_regs(id)\ 272 [id] = {\ 273 SE_COMMON_REG_LIST(id),\ 274 .TMDS_CNTL = 0,\ 275 } 276 277 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 278 stream_enc_regs(0), 279 stream_enc_regs(1), 280 stream_enc_regs(2), 281 stream_enc_regs(3), 282 stream_enc_regs(4), 283 stream_enc_regs(5) 284 }; 285 286 static const struct dce_stream_encoder_shift se_shift = { 287 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 288 }; 289 290 static const struct dce_stream_encoder_mask se_mask = { 291 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 292 }; 293 294 #define opp_regs(id)\ 295 [id] = {\ 296 OPP_DCE_120_REG_LIST(id),\ 297 } 298 299 static const struct dce_opp_registers opp_regs[] = { 300 opp_regs(0), 301 opp_regs(1), 302 opp_regs(2), 303 opp_regs(3), 304 opp_regs(4), 305 opp_regs(5) 306 }; 307 308 static const struct dce_opp_shift opp_shift = { 309 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 310 }; 311 312 static const struct dce_opp_mask opp_mask = { 313 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 314 }; 315 #define aux_engine_regs(id)\ 316 [id] = {\ 317 AUX_COMMON_REG_LIST(id), \ 318 .AUX_RESET_MASK = 0 \ 319 } 320 321 static const struct dce110_aux_registers aux_engine_regs[] = { 322 aux_engine_regs(0), 323 aux_engine_regs(1), 324 aux_engine_regs(2), 325 aux_engine_regs(3), 326 aux_engine_regs(4), 327 aux_engine_regs(5) 328 }; 329 330 #define audio_regs(id)\ 331 [id] = {\ 332 AUD_COMMON_REG_LIST(id)\ 333 } 334 335 static const struct dce_audio_registers audio_regs[] = { 336 audio_regs(0), 337 audio_regs(1), 338 audio_regs(2), 339 audio_regs(3), 340 audio_regs(4), 341 audio_regs(5) 342 }; 343 344 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 345 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 347 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 348 349 static const struct dce_audio_shift audio_shift = { 350 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_aduio_mask audio_mask = { 354 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 #define clk_src_regs(index, id)\ 358 [index] = {\ 359 CS_COMMON_REG_LIST_DCE_112(id),\ 360 } 361 362 static const struct dce110_clk_src_regs clk_src_regs[] = { 363 clk_src_regs(0, A), 364 clk_src_regs(1, B), 365 clk_src_regs(2, C), 366 clk_src_regs(3, D), 367 clk_src_regs(4, E), 368 clk_src_regs(5, F) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 377 }; 378 379 struct output_pixel_processor *dce120_opp_create( 380 struct dc_context *ctx, 381 uint32_t inst) 382 { 383 struct dce110_opp *opp = 384 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 385 386 if (!opp) 387 return NULL; 388 389 dce110_opp_construct(opp, 390 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 391 return &opp->base; 392 } 393 struct dce_aux *dce120_aux_engine_create( 394 struct dc_context *ctx, 395 uint32_t inst) 396 { 397 struct aux_engine_dce110 *aux_engine = 398 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 399 400 if (!aux_engine) 401 return NULL; 402 403 dce110_aux_engine_construct(aux_engine, ctx, inst, 404 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 405 &aux_engine_regs[inst]); 406 407 return &aux_engine->base; 408 } 409 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 410 411 static const struct dce_i2c_registers i2c_hw_regs[] = { 412 i2c_inst_regs(1), 413 i2c_inst_regs(2), 414 i2c_inst_regs(3), 415 i2c_inst_regs(4), 416 i2c_inst_regs(5), 417 i2c_inst_regs(6), 418 }; 419 420 static const struct dce_i2c_shift i2c_shifts = { 421 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 422 }; 423 424 static const struct dce_i2c_mask i2c_masks = { 425 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 426 }; 427 428 struct dce_i2c_hw *dce120_i2c_hw_create( 429 struct dc_context *ctx, 430 uint32_t inst) 431 { 432 struct dce_i2c_hw *dce_i2c_hw = 433 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 434 435 if (!dce_i2c_hw) 436 return NULL; 437 438 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 439 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 440 441 return dce_i2c_hw; 442 } 443 static const struct bios_registers bios_regs = { 444 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 445 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 446 }; 447 448 static const struct resource_caps res_cap = { 449 .num_timing_generator = 6, 450 .num_audio = 7, 451 .num_stream_encoder = 6, 452 .num_pll = 6, 453 .num_ddc = 6, 454 }; 455 456 static const struct dc_plane_cap plane_cap = { 457 .type = DC_PLANE_TYPE_DCE_RGB, 458 459 .pixel_format_support = { 460 .argb8888 = true, 461 .nv12 = false, 462 .fp16 = false 463 }, 464 465 .max_upscale_factor = { 466 .argb8888 = 16000, 467 .nv12 = 1, 468 .fp16 = 1 469 }, 470 471 .max_downscale_factor = { 472 .argb8888 = 250, 473 .nv12 = 1, 474 .fp16 = 1 475 } 476 }; 477 478 static const struct dc_debug_options debug_defaults = { 479 .disable_clock_gate = true, 480 }; 481 482 static struct clock_source *dce120_clock_source_create( 483 struct dc_context *ctx, 484 struct dc_bios *bios, 485 enum clock_source_id id, 486 const struct dce110_clk_src_regs *regs, 487 bool dp_clk_src) 488 { 489 struct dce110_clk_src *clk_src = 490 kzalloc(sizeof(*clk_src), GFP_KERNEL); 491 492 if (!clk_src) 493 return NULL; 494 495 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 496 regs, &cs_shift, &cs_mask)) { 497 clk_src->base.dp_clk_src = dp_clk_src; 498 return &clk_src->base; 499 } 500 501 BREAK_TO_DEBUGGER(); 502 return NULL; 503 } 504 505 static void dce120_clock_source_destroy(struct clock_source **clk_src) 506 { 507 kfree(TO_DCE110_CLK_SRC(*clk_src)); 508 *clk_src = NULL; 509 } 510 511 512 static bool dce120_hw_sequencer_create(struct dc *dc) 513 { 514 /* All registers used by dce11.2 match those in dce11 in offset and 515 * structure 516 */ 517 dce120_hw_sequencer_construct(dc); 518 519 /*TODO Move to separate file and Override what is needed */ 520 521 return true; 522 } 523 524 static struct timing_generator *dce120_timing_generator_create( 525 struct dc_context *ctx, 526 uint32_t instance, 527 const struct dce110_timing_generator_offsets *offsets) 528 { 529 struct dce110_timing_generator *tg110 = 530 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 531 532 if (!tg110) 533 return NULL; 534 535 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 536 return &tg110->base; 537 } 538 539 static void dce120_transform_destroy(struct transform **xfm) 540 { 541 kfree(TO_DCE_TRANSFORM(*xfm)); 542 *xfm = NULL; 543 } 544 545 static void destruct(struct dce110_resource_pool *pool) 546 { 547 unsigned int i; 548 549 for (i = 0; i < pool->base.pipe_count; i++) { 550 if (pool->base.opps[i] != NULL) 551 dce110_opp_destroy(&pool->base.opps[i]); 552 553 if (pool->base.transforms[i] != NULL) 554 dce120_transform_destroy(&pool->base.transforms[i]); 555 556 if (pool->base.ipps[i] != NULL) 557 dce_ipp_destroy(&pool->base.ipps[i]); 558 559 if (pool->base.mis[i] != NULL) { 560 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 561 pool->base.mis[i] = NULL; 562 } 563 564 if (pool->base.irqs != NULL) { 565 dal_irq_service_destroy(&pool->base.irqs); 566 } 567 568 if (pool->base.timing_generators[i] != NULL) { 569 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 570 pool->base.timing_generators[i] = NULL; 571 } 572 } 573 574 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 575 if (pool->base.engines[i] != NULL) 576 dce110_engine_destroy(&pool->base.engines[i]); 577 if (pool->base.hw_i2cs[i] != NULL) { 578 kfree(pool->base.hw_i2cs[i]); 579 pool->base.hw_i2cs[i] = NULL; 580 } 581 if (pool->base.sw_i2cs[i] != NULL) { 582 kfree(pool->base.sw_i2cs[i]); 583 pool->base.sw_i2cs[i] = NULL; 584 } 585 } 586 587 for (i = 0; i < pool->base.audio_count; i++) { 588 if (pool->base.audios[i]) 589 dce_aud_destroy(&pool->base.audios[i]); 590 } 591 592 for (i = 0; i < pool->base.stream_enc_count; i++) { 593 if (pool->base.stream_enc[i] != NULL) 594 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 595 } 596 597 for (i = 0; i < pool->base.clk_src_count; i++) { 598 if (pool->base.clock_sources[i] != NULL) 599 dce120_clock_source_destroy( 600 &pool->base.clock_sources[i]); 601 } 602 603 if (pool->base.dp_clock_source != NULL) 604 dce120_clock_source_destroy(&pool->base.dp_clock_source); 605 606 if (pool->base.abm != NULL) 607 dce_abm_destroy(&pool->base.abm); 608 609 if (pool->base.dmcu != NULL) 610 dce_dmcu_destroy(&pool->base.dmcu); 611 } 612 613 static void read_dce_straps( 614 struct dc_context *ctx, 615 struct resource_straps *straps) 616 { 617 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 618 619 straps->audio_stream_number = get_reg_field_value(reg_val, 620 CC_DC_MISC_STRAPS, 621 AUDIO_STREAM_NUMBER); 622 straps->hdmi_disable = get_reg_field_value(reg_val, 623 CC_DC_MISC_STRAPS, 624 HDMI_DISABLE); 625 626 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 627 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 628 DC_PINSTRAPS, 629 DC_PINSTRAPS_AUDIO); 630 } 631 632 static struct audio *create_audio( 633 struct dc_context *ctx, unsigned int inst) 634 { 635 return dce_audio_create(ctx, inst, 636 &audio_regs[inst], &audio_shift, &audio_mask); 637 } 638 639 static const struct encoder_feature_support link_enc_feature = { 640 .max_hdmi_deep_color = COLOR_DEPTH_121212, 641 .max_hdmi_pixel_clock = 600000, 642 .hdmi_ycbcr420_supported = true, 643 .dp_ycbcr420_supported = false, 644 .flags.bits.IS_HBR2_CAPABLE = true, 645 .flags.bits.IS_HBR3_CAPABLE = true, 646 .flags.bits.IS_TPS3_CAPABLE = true, 647 .flags.bits.IS_TPS4_CAPABLE = true, 648 }; 649 650 static struct link_encoder *dce120_link_encoder_create( 651 const struct encoder_init_data *enc_init_data) 652 { 653 struct dce110_link_encoder *enc110 = 654 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 655 656 if (!enc110) 657 return NULL; 658 659 dce110_link_encoder_construct(enc110, 660 enc_init_data, 661 &link_enc_feature, 662 &link_enc_regs[enc_init_data->transmitter], 663 &link_enc_aux_regs[enc_init_data->channel - 1], 664 &link_enc_hpd_regs[enc_init_data->hpd_source]); 665 666 return &enc110->base; 667 } 668 669 static struct input_pixel_processor *dce120_ipp_create( 670 struct dc_context *ctx, uint32_t inst) 671 { 672 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 673 674 if (!ipp) { 675 BREAK_TO_DEBUGGER(); 676 return NULL; 677 } 678 679 dce_ipp_construct(ipp, ctx, inst, 680 &ipp_regs[inst], &ipp_shift, &ipp_mask); 681 return &ipp->base; 682 } 683 684 static struct stream_encoder *dce120_stream_encoder_create( 685 enum engine_id eng_id, 686 struct dc_context *ctx) 687 { 688 struct dce110_stream_encoder *enc110 = 689 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 690 691 if (!enc110) 692 return NULL; 693 694 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 695 &stream_enc_regs[eng_id], 696 &se_shift, &se_mask); 697 return &enc110->base; 698 } 699 700 #define SRII(reg_name, block, id)\ 701 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 702 mm ## block ## id ## _ ## reg_name 703 704 static const struct dce_hwseq_registers hwseq_reg = { 705 HWSEQ_DCE120_REG_LIST() 706 }; 707 708 static const struct dce_hwseq_shift hwseq_shift = { 709 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 710 }; 711 712 static const struct dce_hwseq_mask hwseq_mask = { 713 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 714 }; 715 716 /* HWSEQ regs for VG20 */ 717 static const struct dce_hwseq_registers dce121_hwseq_reg = { 718 HWSEQ_VG20_REG_LIST() 719 }; 720 721 static const struct dce_hwseq_shift dce121_hwseq_shift = { 722 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 723 }; 724 725 static const struct dce_hwseq_mask dce121_hwseq_mask = { 726 HWSEQ_VG20_MASK_SH_LIST(_MASK) 727 }; 728 729 static struct dce_hwseq *dce120_hwseq_create( 730 struct dc_context *ctx) 731 { 732 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 733 734 if (hws) { 735 hws->ctx = ctx; 736 hws->regs = &hwseq_reg; 737 hws->shifts = &hwseq_shift; 738 hws->masks = &hwseq_mask; 739 } 740 return hws; 741 } 742 743 static struct dce_hwseq *dce121_hwseq_create( 744 struct dc_context *ctx) 745 { 746 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 747 748 if (hws) { 749 hws->ctx = ctx; 750 hws->regs = &dce121_hwseq_reg; 751 hws->shifts = &dce121_hwseq_shift; 752 hws->masks = &dce121_hwseq_mask; 753 } 754 return hws; 755 } 756 757 static const struct resource_create_funcs res_create_funcs = { 758 .read_dce_straps = read_dce_straps, 759 .create_audio = create_audio, 760 .create_stream_encoder = dce120_stream_encoder_create, 761 .create_hwseq = dce120_hwseq_create, 762 }; 763 764 static const struct resource_create_funcs dce121_res_create_funcs = { 765 .read_dce_straps = read_dce_straps, 766 .create_audio = create_audio, 767 .create_stream_encoder = dce120_stream_encoder_create, 768 .create_hwseq = dce121_hwseq_create, 769 }; 770 771 772 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 773 static const struct dce_mem_input_registers mi_regs[] = { 774 mi_inst_regs(0), 775 mi_inst_regs(1), 776 mi_inst_regs(2), 777 mi_inst_regs(3), 778 mi_inst_regs(4), 779 mi_inst_regs(5), 780 }; 781 782 static const struct dce_mem_input_shift mi_shifts = { 783 MI_DCE12_MASK_SH_LIST(__SHIFT) 784 }; 785 786 static const struct dce_mem_input_mask mi_masks = { 787 MI_DCE12_MASK_SH_LIST(_MASK) 788 }; 789 790 static struct mem_input *dce120_mem_input_create( 791 struct dc_context *ctx, 792 uint32_t inst) 793 { 794 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 795 GFP_KERNEL); 796 797 if (!dce_mi) { 798 BREAK_TO_DEBUGGER(); 799 return NULL; 800 } 801 802 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 803 return &dce_mi->base; 804 } 805 806 static struct transform *dce120_transform_create( 807 struct dc_context *ctx, 808 uint32_t inst) 809 { 810 struct dce_transform *transform = 811 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 812 813 if (!transform) 814 return NULL; 815 816 dce_transform_construct(transform, ctx, inst, 817 &xfm_regs[inst], &xfm_shift, &xfm_mask); 818 transform->lb_memory_size = 0x1404; /*5124*/ 819 return &transform->base; 820 } 821 822 static void dce120_destroy_resource_pool(struct resource_pool **pool) 823 { 824 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 825 826 destruct(dce110_pool); 827 kfree(dce110_pool); 828 *pool = NULL; 829 } 830 831 static const struct resource_funcs dce120_res_pool_funcs = { 832 .destroy = dce120_destroy_resource_pool, 833 .link_enc_create = dce120_link_encoder_create, 834 .validate_bandwidth = dce112_validate_bandwidth, 835 .validate_plane = dce100_validate_plane, 836 .add_stream_to_ctx = dce112_add_stream_to_ctx, 837 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 838 }; 839 840 static void bw_calcs_data_update_from_pplib(struct dc *dc) 841 { 842 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 843 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 844 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 845 int i; 846 unsigned int clk; 847 unsigned int latency; 848 849 /*do system clock*/ 850 if (!dm_pp_get_clock_levels_by_type_with_latency( 851 dc->ctx, 852 DM_PP_CLOCK_TYPE_ENGINE_CLK, 853 &eng_clks) || eng_clks.num_levels == 0) { 854 855 eng_clks.num_levels = 8; 856 clk = 300000; 857 858 for (i = 0; i < eng_clks.num_levels; i++) { 859 eng_clks.data[i].clocks_in_khz = clk; 860 clk += 100000; 861 } 862 } 863 864 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 865 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 866 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 867 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 868 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 869 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 870 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 871 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 872 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 873 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 874 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 875 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 876 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 877 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 878 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 879 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 880 eng_clks.data[0].clocks_in_khz, 1000); 881 882 /*do memory clock*/ 883 if (!dm_pp_get_clock_levels_by_type_with_latency( 884 dc->ctx, 885 DM_PP_CLOCK_TYPE_MEMORY_CLK, 886 &mem_clks) || mem_clks.num_levels == 0) { 887 888 mem_clks.num_levels = 3; 889 clk = 250000; 890 latency = 45; 891 892 for (i = 0; i < eng_clks.num_levels; i++) { 893 mem_clks.data[i].clocks_in_khz = clk; 894 mem_clks.data[i].latency_in_us = latency; 895 clk += 500000; 896 latency -= 5; 897 } 898 899 } 900 901 /* we don't need to call PPLIB for validation clock since they 902 * also give us the highest sclk and highest mclk (UMA clock). 903 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 904 * YCLK = UMACLK*m_memoryTypeMultiplier 905 */ 906 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 907 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 908 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 909 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 910 1000); 911 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 912 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 913 1000); 914 915 /* Now notify PPLib/SMU about which Watermarks sets they should select 916 * depending on DPM state they are in. And update BW MGR GFX Engine and 917 * Memory clock member variables for Watermarks calculations for each 918 * Watermark Set 919 */ 920 clk_ranges.num_wm_sets = 4; 921 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 922 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 923 eng_clks.data[0].clocks_in_khz; 924 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 925 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 926 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 927 mem_clks.data[0].clocks_in_khz; 928 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 929 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 930 931 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 932 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 933 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 934 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 935 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 936 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 937 mem_clks.data[0].clocks_in_khz; 938 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 939 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 940 941 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 942 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 943 eng_clks.data[0].clocks_in_khz; 944 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 945 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 946 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 947 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 948 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 949 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 950 951 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 952 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 953 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 954 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 955 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 956 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 957 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 958 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 959 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 960 961 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 962 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 963 } 964 965 static uint32_t read_pipe_fuses(struct dc_context *ctx) 966 { 967 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 968 /* VG20 support max 6 pipes */ 969 value = value & 0x3f; 970 return value; 971 } 972 973 static bool construct( 974 uint8_t num_virtual_links, 975 struct dc *dc, 976 struct dce110_resource_pool *pool) 977 { 978 unsigned int i; 979 int j; 980 struct dc_context *ctx = dc->ctx; 981 struct irq_service_init_data irq_init_data; 982 static const struct resource_create_funcs *res_funcs; 983 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 984 uint32_t pipe_fuses; 985 986 ctx->dc_bios->regs = &bios_regs; 987 988 pool->base.res_cap = &res_cap; 989 pool->base.funcs = &dce120_res_pool_funcs; 990 991 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 992 pool->base.pipe_count = res_cap.num_timing_generator; 993 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 994 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 995 996 dc->caps.max_downscale_ratio = 200; 997 dc->caps.i2c_speed_in_khz = 100; 998 dc->caps.max_cursor_size = 128; 999 dc->caps.dual_link_dvi = true; 1000 dc->caps.psp_setup_panel_mode = true; 1001 1002 dc->debug = debug_defaults; 1003 1004 /************************************************* 1005 * Create resources * 1006 *************************************************/ 1007 1008 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1009 dce120_clock_source_create(ctx, ctx->dc_bios, 1010 CLOCK_SOURCE_COMBO_PHY_PLL0, 1011 &clk_src_regs[0], false); 1012 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1013 dce120_clock_source_create(ctx, ctx->dc_bios, 1014 CLOCK_SOURCE_COMBO_PHY_PLL1, 1015 &clk_src_regs[1], false); 1016 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1017 dce120_clock_source_create(ctx, ctx->dc_bios, 1018 CLOCK_SOURCE_COMBO_PHY_PLL2, 1019 &clk_src_regs[2], false); 1020 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1021 dce120_clock_source_create(ctx, ctx->dc_bios, 1022 CLOCK_SOURCE_COMBO_PHY_PLL3, 1023 &clk_src_regs[3], false); 1024 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1025 dce120_clock_source_create(ctx, ctx->dc_bios, 1026 CLOCK_SOURCE_COMBO_PHY_PLL4, 1027 &clk_src_regs[4], false); 1028 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1029 dce120_clock_source_create(ctx, ctx->dc_bios, 1030 CLOCK_SOURCE_COMBO_PHY_PLL5, 1031 &clk_src_regs[5], false); 1032 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1033 1034 pool->base.dp_clock_source = 1035 dce120_clock_source_create(ctx, ctx->dc_bios, 1036 CLOCK_SOURCE_ID_DP_DTO, 1037 &clk_src_regs[0], true); 1038 1039 for (i = 0; i < pool->base.clk_src_count; i++) { 1040 if (pool->base.clock_sources[i] == NULL) { 1041 dm_error("DC: failed to create clock sources!\n"); 1042 BREAK_TO_DEBUGGER(); 1043 goto clk_src_create_fail; 1044 } 1045 } 1046 1047 pool->base.dmcu = dce_dmcu_create(ctx, 1048 &dmcu_regs, 1049 &dmcu_shift, 1050 &dmcu_mask); 1051 if (pool->base.dmcu == NULL) { 1052 dm_error("DC: failed to create dmcu!\n"); 1053 BREAK_TO_DEBUGGER(); 1054 goto res_create_fail; 1055 } 1056 1057 pool->base.abm = dce_abm_create(ctx, 1058 &abm_regs, 1059 &abm_shift, 1060 &abm_mask); 1061 if (pool->base.abm == NULL) { 1062 dm_error("DC: failed to create abm!\n"); 1063 BREAK_TO_DEBUGGER(); 1064 goto res_create_fail; 1065 } 1066 1067 1068 irq_init_data.ctx = dc->ctx; 1069 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1070 if (!pool->base.irqs) 1071 goto irqs_create_fail; 1072 1073 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1074 if (is_vg20) 1075 pipe_fuses = read_pipe_fuses(ctx); 1076 1077 /* index to valid pipe resource */ 1078 j = 0; 1079 for (i = 0; i < pool->base.pipe_count; i++) { 1080 if (is_vg20) { 1081 if ((pipe_fuses & (1 << i)) != 0) { 1082 dm_error("DC: skip invalid pipe %d!\n", i); 1083 continue; 1084 } 1085 } 1086 1087 pool->base.timing_generators[j] = 1088 dce120_timing_generator_create( 1089 ctx, 1090 i, 1091 &dce120_tg_offsets[i]); 1092 if (pool->base.timing_generators[j] == NULL) { 1093 BREAK_TO_DEBUGGER(); 1094 dm_error("DC: failed to create tg!\n"); 1095 goto controller_create_fail; 1096 } 1097 1098 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1099 1100 if (pool->base.mis[j] == NULL) { 1101 BREAK_TO_DEBUGGER(); 1102 dm_error( 1103 "DC: failed to create memory input!\n"); 1104 goto controller_create_fail; 1105 } 1106 1107 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1108 if (pool->base.ipps[i] == NULL) { 1109 BREAK_TO_DEBUGGER(); 1110 dm_error( 1111 "DC: failed to create input pixel processor!\n"); 1112 goto controller_create_fail; 1113 } 1114 1115 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1116 if (pool->base.transforms[i] == NULL) { 1117 BREAK_TO_DEBUGGER(); 1118 dm_error( 1119 "DC: failed to create transform!\n"); 1120 goto res_create_fail; 1121 } 1122 1123 pool->base.opps[j] = dce120_opp_create( 1124 ctx, 1125 i); 1126 if (pool->base.opps[j] == NULL) { 1127 BREAK_TO_DEBUGGER(); 1128 dm_error( 1129 "DC: failed to create output pixel processor!\n"); 1130 } 1131 1132 /* check next valid pipe */ 1133 j++; 1134 } 1135 1136 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1137 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1138 if (pool->base.engines[i] == NULL) { 1139 BREAK_TO_DEBUGGER(); 1140 dm_error( 1141 "DC:failed to create aux engine!!\n"); 1142 goto res_create_fail; 1143 } 1144 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1145 if (pool->base.hw_i2cs[i] == NULL) { 1146 BREAK_TO_DEBUGGER(); 1147 dm_error( 1148 "DC:failed to create i2c engine!!\n"); 1149 goto res_create_fail; 1150 } 1151 pool->base.sw_i2cs[i] = NULL; 1152 } 1153 1154 /* valid pipe num */ 1155 pool->base.pipe_count = j; 1156 pool->base.timing_generator_count = j; 1157 1158 if (is_vg20) 1159 res_funcs = &dce121_res_create_funcs; 1160 else 1161 res_funcs = &res_create_funcs; 1162 1163 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1164 goto res_create_fail; 1165 1166 /* Create hardware sequencer */ 1167 if (!dce120_hw_sequencer_create(dc)) 1168 goto controller_create_fail; 1169 1170 dc->caps.max_planes = pool->base.pipe_count; 1171 1172 for (i = 0; i < dc->caps.max_planes; ++i) 1173 dc->caps.planes[i] = plane_cap; 1174 1175 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1176 1177 bw_calcs_data_update_from_pplib(dc); 1178 1179 return true; 1180 1181 irqs_create_fail: 1182 controller_create_fail: 1183 clk_src_create_fail: 1184 res_create_fail: 1185 1186 destruct(pool); 1187 1188 return false; 1189 } 1190 1191 struct resource_pool *dce120_create_resource_pool( 1192 uint8_t num_virtual_links, 1193 struct dc *dc) 1194 { 1195 struct dce110_resource_pool *pool = 1196 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1197 1198 if (!pool) 1199 return NULL; 1200 1201 if (construct(num_virtual_links, dc, pool)) 1202 return &pool->base; 1203 1204 BREAK_TO_DEBUGGER(); 1205 return NULL; 1206 } 1207