1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 57 #include "vega10/DC/dce_12_0_offset.h" 58 #include "vega10/DC/dce_12_0_sh_mask.h" 59 #include "vega10/soc15ip.h" 60 #include "vega10/NBIO/nbio_6_1_offset.h" 61 #include "reg_helper.h" 62 63 #include "dce100/dce100_resource.h" 64 65 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #endif 81 82 enum dce120_clk_src_array_id { 83 DCE120_CLK_SRC_PLL0, 84 DCE120_CLK_SRC_PLL1, 85 DCE120_CLK_SRC_PLL2, 86 DCE120_CLK_SRC_PLL3, 87 DCE120_CLK_SRC_PLL4, 88 DCE120_CLK_SRC_PLL5, 89 90 DCE120_CLK_SRC_TOTAL 91 }; 92 93 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 94 { 95 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 96 }, 97 { 98 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 99 }, 100 { 101 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 } 112 }; 113 114 /* begin ********************* 115 * macros to expend register list macro defined in HW object header file */ 116 117 #define BASE_INNER(seg) \ 118 DCE_BASE__INST0_SEG ## seg 119 120 #define NBIO_BASE_INNER(seg) \ 121 NBIF_BASE__INST0_SEG ## seg 122 123 #define NBIO_BASE(seg) \ 124 NBIO_BASE_INNER(seg) 125 126 /* compile time expand base address. */ 127 #define BASE(seg) \ 128 BASE_INNER(seg) 129 130 #define SR(reg_name)\ 131 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 132 mm ## reg_name 133 134 #define SRI(reg_name, block, id)\ 135 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 136 mm ## block ## id ## _ ## reg_name 137 138 /* macros to expend register list macro defined in HW object header file 139 * end *********************/ 140 141 142 static const struct dce_dmcu_registers dmcu_regs = { 143 DMCU_DCE110_COMMON_REG_LIST() 144 }; 145 146 static const struct dce_dmcu_shift dmcu_shift = { 147 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 148 }; 149 150 static const struct dce_dmcu_mask dmcu_mask = { 151 DMCU_MASK_SH_LIST_DCE110(_MASK) 152 }; 153 154 static const struct dce_abm_registers abm_regs = { 155 ABM_DCE110_COMMON_REG_LIST() 156 }; 157 158 static const struct dce_abm_shift abm_shift = { 159 ABM_MASK_SH_LIST_DCE110(__SHIFT) 160 }; 161 162 static const struct dce_abm_mask abm_mask = { 163 ABM_MASK_SH_LIST_DCE110(_MASK) 164 }; 165 166 #define ipp_regs(id)\ 167 [id] = {\ 168 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 169 } 170 171 static const struct dce_ipp_registers ipp_regs[] = { 172 ipp_regs(0), 173 ipp_regs(1), 174 ipp_regs(2), 175 ipp_regs(3), 176 ipp_regs(4), 177 ipp_regs(5) 178 }; 179 180 static const struct dce_ipp_shift ipp_shift = { 181 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 182 }; 183 184 static const struct dce_ipp_mask ipp_mask = { 185 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 186 }; 187 188 #define transform_regs(id)\ 189 [id] = {\ 190 XFM_COMMON_REG_LIST_DCE110(id)\ 191 } 192 193 static const struct dce_transform_registers xfm_regs[] = { 194 transform_regs(0), 195 transform_regs(1), 196 transform_regs(2), 197 transform_regs(3), 198 transform_regs(4), 199 transform_regs(5) 200 }; 201 202 static const struct dce_transform_shift xfm_shift = { 203 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 204 }; 205 206 static const struct dce_transform_mask xfm_mask = { 207 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 208 }; 209 210 #define aux_regs(id)\ 211 [id] = {\ 212 AUX_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 216 aux_regs(0), 217 aux_regs(1), 218 aux_regs(2), 219 aux_regs(3), 220 aux_regs(4), 221 aux_regs(5) 222 }; 223 224 #define hpd_regs(id)\ 225 [id] = {\ 226 HPD_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 230 hpd_regs(0), 231 hpd_regs(1), 232 hpd_regs(2), 233 hpd_regs(3), 234 hpd_regs(4), 235 hpd_regs(5) 236 }; 237 238 #define link_regs(id)\ 239 [id] = {\ 240 LE_DCE120_REG_LIST(id), \ 241 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 242 } 243 244 static const struct dce110_link_enc_registers link_enc_regs[] = { 245 link_regs(0), 246 link_regs(1), 247 link_regs(2), 248 link_regs(3), 249 link_regs(4), 250 link_regs(5), 251 link_regs(6), 252 }; 253 254 255 #define stream_enc_regs(id)\ 256 [id] = {\ 257 SE_COMMON_REG_LIST(id),\ 258 .TMDS_CNTL = 0,\ 259 } 260 261 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 262 stream_enc_regs(0), 263 stream_enc_regs(1), 264 stream_enc_regs(2), 265 stream_enc_regs(3), 266 stream_enc_regs(4), 267 stream_enc_regs(5) 268 }; 269 270 static const struct dce_stream_encoder_shift se_shift = { 271 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 272 }; 273 274 static const struct dce_stream_encoder_mask se_mask = { 275 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_120_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 298 }; 299 300 #define audio_regs(id)\ 301 [id] = {\ 302 AUD_COMMON_REG_LIST(id)\ 303 } 304 305 static struct dce_audio_registers audio_regs[] = { 306 audio_regs(0), 307 audio_regs(1), 308 audio_regs(2), 309 audio_regs(3), 310 audio_regs(4), 311 audio_regs(5) 312 }; 313 314 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 315 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 316 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 317 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 318 319 static const struct dce_audio_shift audio_shift = { 320 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 321 }; 322 323 static const struct dce_aduio_mask audio_mask = { 324 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 325 }; 326 327 #define clk_src_regs(index, id)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCE_112(id),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E), 338 clk_src_regs(5, F) 339 }; 340 341 static const struct dce110_clk_src_shift cs_shift = { 342 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 343 }; 344 345 static const struct dce110_clk_src_mask cs_mask = { 346 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 347 }; 348 349 struct output_pixel_processor *dce120_opp_create( 350 struct dc_context *ctx, 351 uint32_t inst) 352 { 353 struct dce110_opp *opp = 354 dm_alloc(sizeof(struct dce110_opp)); 355 356 if (!opp) 357 return NULL; 358 359 if (dce110_opp_construct(opp, 360 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 361 return &opp->base; 362 363 BREAK_TO_DEBUGGER(); 364 dm_free(opp); 365 return NULL; 366 } 367 368 static const struct bios_registers bios_regs = { 369 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 370 }; 371 372 static const struct resource_caps res_cap = { 373 .num_timing_generator = 6, 374 .num_audio = 7, 375 .num_stream_encoder = 6, 376 .num_pll = 6, 377 }; 378 379 static const struct dc_debug debug_defaults = { 380 .disable_clock_gate = true, 381 }; 382 383 struct clock_source *dce120_clock_source_create( 384 struct dc_context *ctx, 385 struct dc_bios *bios, 386 enum clock_source_id id, 387 const struct dce110_clk_src_regs *regs, 388 bool dp_clk_src) 389 { 390 struct dce110_clk_src *clk_src = 391 dm_alloc(sizeof(*clk_src)); 392 393 if (!clk_src) 394 return NULL; 395 396 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 397 regs, &cs_shift, &cs_mask)) { 398 clk_src->base.dp_clk_src = dp_clk_src; 399 return &clk_src->base; 400 } 401 402 BREAK_TO_DEBUGGER(); 403 return NULL; 404 } 405 406 void dce120_clock_source_destroy(struct clock_source **clk_src) 407 { 408 dm_free(TO_DCE110_CLK_SRC(*clk_src)); 409 *clk_src = NULL; 410 } 411 412 413 bool dce120_hw_sequencer_create(struct dc *dc) 414 { 415 /* All registers used by dce11.2 match those in dce11 in offset and 416 * structure 417 */ 418 dce120_hw_sequencer_construct(dc); 419 420 /*TODO Move to separate file and Override what is needed */ 421 422 return true; 423 } 424 425 static struct timing_generator *dce120_timing_generator_create( 426 struct dc_context *ctx, 427 uint32_t instance, 428 const struct dce110_timing_generator_offsets *offsets) 429 { 430 struct dce110_timing_generator *tg110 = 431 dm_alloc(sizeof(struct dce110_timing_generator)); 432 433 if (!tg110) 434 return NULL; 435 436 if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) 437 return &tg110->base; 438 439 BREAK_TO_DEBUGGER(); 440 dm_free(tg110); 441 return NULL; 442 } 443 444 static void dce120_transform_destroy(struct transform **xfm) 445 { 446 dm_free(TO_DCE_TRANSFORM(*xfm)); 447 *xfm = NULL; 448 } 449 450 static void destruct(struct dce110_resource_pool *pool) 451 { 452 unsigned int i; 453 454 for (i = 0; i < pool->base.pipe_count; i++) { 455 if (pool->base.opps[i] != NULL) 456 dce110_opp_destroy(&pool->base.opps[i]); 457 458 if (pool->base.transforms[i] != NULL) 459 dce120_transform_destroy(&pool->base.transforms[i]); 460 461 if (pool->base.ipps[i] != NULL) 462 dce_ipp_destroy(&pool->base.ipps[i]); 463 464 if (pool->base.mis[i] != NULL) { 465 dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); 466 pool->base.mis[i] = NULL; 467 } 468 469 if (pool->base.irqs != NULL) { 470 dal_irq_service_destroy(&pool->base.irqs); 471 } 472 473 if (pool->base.timing_generators[i] != NULL) { 474 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 475 pool->base.timing_generators[i] = NULL; 476 } 477 } 478 479 for (i = 0; i < pool->base.audio_count; i++) { 480 if (pool->base.audios[i]) 481 dce_aud_destroy(&pool->base.audios[i]); 482 } 483 484 for (i = 0; i < pool->base.stream_enc_count; i++) { 485 if (pool->base.stream_enc[i] != NULL) 486 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 487 } 488 489 for (i = 0; i < pool->base.clk_src_count; i++) { 490 if (pool->base.clock_sources[i] != NULL) 491 dce120_clock_source_destroy( 492 &pool->base.clock_sources[i]); 493 } 494 495 if (pool->base.dp_clock_source != NULL) 496 dce120_clock_source_destroy(&pool->base.dp_clock_source); 497 498 if (pool->base.abm != NULL) 499 dce_abm_destroy(&pool->base.abm); 500 501 if (pool->base.dmcu != NULL) 502 dce_dmcu_destroy(&pool->base.dmcu); 503 504 if (pool->base.display_clock != NULL) 505 dce_disp_clk_destroy(&pool->base.display_clock); 506 } 507 508 static void read_dce_straps( 509 struct dc_context *ctx, 510 struct resource_straps *straps) 511 { 512 /* TODO: Registers are missing */ 513 /*REG_GET_2(CC_DC_HDMI_STRAPS, 514 HDMI_DISABLE, &straps->hdmi_disable, 515 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 516 517 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ 518 } 519 520 static struct audio *create_audio( 521 struct dc_context *ctx, unsigned int inst) 522 { 523 return dce_audio_create(ctx, inst, 524 &audio_regs[inst], &audio_shift, &audio_mask); 525 } 526 527 static const struct encoder_feature_support link_enc_feature = { 528 .max_hdmi_deep_color = COLOR_DEPTH_121212, 529 .max_hdmi_pixel_clock = 600000, 530 .ycbcr420_supported = true, 531 .flags.bits.IS_HBR2_CAPABLE = true, 532 .flags.bits.IS_HBR3_CAPABLE = true, 533 .flags.bits.IS_TPS3_CAPABLE = true, 534 .flags.bits.IS_TPS4_CAPABLE = true, 535 .flags.bits.IS_YCBCR_CAPABLE = true 536 }; 537 538 static struct link_encoder *dce120_link_encoder_create( 539 const struct encoder_init_data *enc_init_data) 540 { 541 struct dce110_link_encoder *enc110 = 542 dm_alloc(sizeof(struct dce110_link_encoder)); 543 544 if (!enc110) 545 return NULL; 546 547 if (dce110_link_encoder_construct( 548 enc110, 549 enc_init_data, 550 &link_enc_feature, 551 &link_enc_regs[enc_init_data->transmitter], 552 &link_enc_aux_regs[enc_init_data->channel - 1], 553 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 554 555 return &enc110->base; 556 } 557 558 BREAK_TO_DEBUGGER(); 559 dm_free(enc110); 560 return NULL; 561 } 562 563 static struct input_pixel_processor *dce120_ipp_create( 564 struct dc_context *ctx, uint32_t inst) 565 { 566 struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); 567 568 if (!ipp) { 569 BREAK_TO_DEBUGGER(); 570 return NULL; 571 } 572 573 dce_ipp_construct(ipp, ctx, inst, 574 &ipp_regs[inst], &ipp_shift, &ipp_mask); 575 return &ipp->base; 576 } 577 578 static struct stream_encoder *dce120_stream_encoder_create( 579 enum engine_id eng_id, 580 struct dc_context *ctx) 581 { 582 struct dce110_stream_encoder *enc110 = 583 dm_alloc(sizeof(struct dce110_stream_encoder)); 584 585 if (!enc110) 586 return NULL; 587 588 if (dce110_stream_encoder_construct( 589 enc110, ctx, ctx->dc_bios, eng_id, 590 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 591 return &enc110->base; 592 593 BREAK_TO_DEBUGGER(); 594 dm_free(enc110); 595 return NULL; 596 } 597 598 #define SRII(reg_name, block, id)\ 599 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 600 mm ## block ## id ## _ ## reg_name 601 602 static const struct dce_hwseq_registers hwseq_reg = { 603 HWSEQ_DCE120_REG_LIST() 604 }; 605 606 static const struct dce_hwseq_shift hwseq_shift = { 607 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 608 }; 609 610 static const struct dce_hwseq_mask hwseq_mask = { 611 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 612 }; 613 614 static struct dce_hwseq *dce120_hwseq_create( 615 struct dc_context *ctx) 616 { 617 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); 618 619 if (hws) { 620 hws->ctx = ctx; 621 hws->regs = &hwseq_reg; 622 hws->shifts = &hwseq_shift; 623 hws->masks = &hwseq_mask; 624 } 625 return hws; 626 } 627 628 static const struct resource_create_funcs res_create_funcs = { 629 .read_dce_straps = read_dce_straps, 630 .create_audio = create_audio, 631 .create_stream_encoder = dce120_stream_encoder_create, 632 .create_hwseq = dce120_hwseq_create, 633 }; 634 635 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 636 static const struct dce_mem_input_registers mi_regs[] = { 637 mi_inst_regs(0), 638 mi_inst_regs(1), 639 mi_inst_regs(2), 640 mi_inst_regs(3), 641 mi_inst_regs(4), 642 mi_inst_regs(5), 643 }; 644 645 static const struct dce_mem_input_shift mi_shifts = { 646 MI_DCE12_MASK_SH_LIST(__SHIFT) 647 }; 648 649 static const struct dce_mem_input_mask mi_masks = { 650 MI_DCE12_MASK_SH_LIST(_MASK) 651 }; 652 653 static struct mem_input *dce120_mem_input_create( 654 struct dc_context *ctx, 655 uint32_t inst) 656 { 657 struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); 658 659 if (!dce_mi) { 660 BREAK_TO_DEBUGGER(); 661 return NULL; 662 } 663 664 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 665 return &dce_mi->base; 666 } 667 668 static struct transform *dce120_transform_create( 669 struct dc_context *ctx, 670 uint32_t inst) 671 { 672 struct dce_transform *transform = 673 dm_alloc(sizeof(struct dce_transform)); 674 675 if (!transform) 676 return NULL; 677 678 if (dce_transform_construct(transform, ctx, inst, 679 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 680 transform->lb_memory_size = 0x1404; /*5124*/ 681 return &transform->base; 682 } 683 684 BREAK_TO_DEBUGGER(); 685 dm_free(transform); 686 return NULL; 687 } 688 689 static void dce120_destroy_resource_pool(struct resource_pool **pool) 690 { 691 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 692 693 destruct(dce110_pool); 694 dm_free(dce110_pool); 695 *pool = NULL; 696 } 697 698 static const struct resource_funcs dce120_res_pool_funcs = { 699 .destroy = dce120_destroy_resource_pool, 700 .link_enc_create = dce120_link_encoder_create, 701 .validate_with_context = dce112_validate_with_context, 702 .validate_guaranteed = dce112_validate_guaranteed, 703 .validate_bandwidth = dce112_validate_bandwidth, 704 .validate_plane = dce100_validate_plane 705 }; 706 707 static void bw_calcs_data_update_from_pplib(struct dc *dc) 708 { 709 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 710 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 711 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 712 int i; 713 unsigned int clk; 714 unsigned int latency; 715 716 /*do system clock*/ 717 if (!dm_pp_get_clock_levels_by_type_with_latency( 718 dc->ctx, 719 DM_PP_CLOCK_TYPE_ENGINE_CLK, 720 &eng_clks) || eng_clks.num_levels == 0) { 721 722 eng_clks.num_levels = 8; 723 clk = 300000; 724 725 for (i = 0; i < eng_clks.num_levels; i++) { 726 eng_clks.data[i].clocks_in_khz = clk; 727 clk += 100000; 728 } 729 } 730 731 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 732 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 733 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 734 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 735 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 736 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 737 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 738 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 739 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 740 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 741 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 742 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 743 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 744 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 745 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 746 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 747 eng_clks.data[0].clocks_in_khz, 1000); 748 749 /*do memory clock*/ 750 if (!dm_pp_get_clock_levels_by_type_with_latency( 751 dc->ctx, 752 DM_PP_CLOCK_TYPE_MEMORY_CLK, 753 &mem_clks) || mem_clks.num_levels == 0) { 754 755 mem_clks.num_levels = 3; 756 clk = 250000; 757 latency = 45; 758 759 for (i = 0; i < eng_clks.num_levels; i++) { 760 mem_clks.data[i].clocks_in_khz = clk; 761 mem_clks.data[i].latency_in_us = latency; 762 clk += 500000; 763 latency -= 5; 764 } 765 766 } 767 768 /* we don't need to call PPLIB for validation clock since they 769 * also give us the highest sclk and highest mclk (UMA clock). 770 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 771 * YCLK = UMACLK*m_memoryTypeMultiplier 772 */ 773 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 774 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 775 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 776 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 777 1000); 778 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 779 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 780 1000); 781 782 /* Now notify PPLib/SMU about which Watermarks sets they should select 783 * depending on DPM state they are in. And update BW MGR GFX Engine and 784 * Memory clock member variables for Watermarks calculations for each 785 * Watermark Set 786 */ 787 clk_ranges.num_wm_sets = 4; 788 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 789 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 790 eng_clks.data[0].clocks_in_khz; 791 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 792 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 793 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 794 mem_clks.data[0].clocks_in_khz; 795 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 796 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 797 798 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 799 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 800 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 801 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 802 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 803 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 804 mem_clks.data[0].clocks_in_khz; 805 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 806 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 807 808 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 809 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 810 eng_clks.data[0].clocks_in_khz; 811 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 812 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 813 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 814 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 815 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 816 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 817 818 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 819 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 820 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 821 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 822 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 823 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 824 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 825 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 826 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 827 828 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 829 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 830 } 831 832 static bool construct( 833 uint8_t num_virtual_links, 834 struct dc *dc, 835 struct dce110_resource_pool *pool) 836 { 837 unsigned int i; 838 struct dc_context *ctx = dc->ctx; 839 struct irq_service_init_data irq_init_data; 840 841 ctx->dc_bios->regs = &bios_regs; 842 843 pool->base.res_cap = &res_cap; 844 pool->base.funcs = &dce120_res_pool_funcs; 845 846 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 847 pool->base.pipe_count = res_cap.num_timing_generator; 848 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 849 850 dc->caps.max_downscale_ratio = 200; 851 dc->caps.i2c_speed_in_khz = 100; 852 dc->caps.max_cursor_size = 128; 853 dc->debug = debug_defaults; 854 855 /************************************************* 856 * Create resources * 857 *************************************************/ 858 859 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 860 dce120_clock_source_create(ctx, ctx->dc_bios, 861 CLOCK_SOURCE_COMBO_PHY_PLL0, 862 &clk_src_regs[0], false); 863 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 864 dce120_clock_source_create(ctx, ctx->dc_bios, 865 CLOCK_SOURCE_COMBO_PHY_PLL1, 866 &clk_src_regs[1], false); 867 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 868 dce120_clock_source_create(ctx, ctx->dc_bios, 869 CLOCK_SOURCE_COMBO_PHY_PLL2, 870 &clk_src_regs[2], false); 871 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 872 dce120_clock_source_create(ctx, ctx->dc_bios, 873 CLOCK_SOURCE_COMBO_PHY_PLL3, 874 &clk_src_regs[3], false); 875 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 876 dce120_clock_source_create(ctx, ctx->dc_bios, 877 CLOCK_SOURCE_COMBO_PHY_PLL4, 878 &clk_src_regs[4], false); 879 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 880 dce120_clock_source_create(ctx, ctx->dc_bios, 881 CLOCK_SOURCE_COMBO_PHY_PLL5, 882 &clk_src_regs[5], false); 883 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 884 885 pool->base.dp_clock_source = 886 dce120_clock_source_create(ctx, ctx->dc_bios, 887 CLOCK_SOURCE_ID_DP_DTO, 888 &clk_src_regs[0], true); 889 890 for (i = 0; i < pool->base.clk_src_count; i++) { 891 if (pool->base.clock_sources[i] == NULL) { 892 dm_error("DC: failed to create clock sources!\n"); 893 BREAK_TO_DEBUGGER(); 894 goto clk_src_create_fail; 895 } 896 } 897 898 pool->base.display_clock = dce120_disp_clk_create(ctx); 899 if (pool->base.display_clock == NULL) { 900 dm_error("DC: failed to create display clock!\n"); 901 BREAK_TO_DEBUGGER(); 902 goto disp_clk_create_fail; 903 } 904 905 pool->base.dmcu = dce_dmcu_create(ctx, 906 &dmcu_regs, 907 &dmcu_shift, 908 &dmcu_mask); 909 if (pool->base.dmcu == NULL) { 910 dm_error("DC: failed to create dmcu!\n"); 911 BREAK_TO_DEBUGGER(); 912 goto res_create_fail; 913 } 914 915 pool->base.abm = dce_abm_create(ctx, 916 &abm_regs, 917 &abm_shift, 918 &abm_mask); 919 if (pool->base.abm == NULL) { 920 dm_error("DC: failed to create abm!\n"); 921 BREAK_TO_DEBUGGER(); 922 goto res_create_fail; 923 } 924 925 irq_init_data.ctx = dc->ctx; 926 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 927 if (!pool->base.irqs) 928 goto irqs_create_fail; 929 930 for (i = 0; i < pool->base.pipe_count; i++) { 931 pool->base.timing_generators[i] = 932 dce120_timing_generator_create( 933 ctx, 934 i, 935 &dce120_tg_offsets[i]); 936 if (pool->base.timing_generators[i] == NULL) { 937 BREAK_TO_DEBUGGER(); 938 dm_error("DC: failed to create tg!\n"); 939 goto controller_create_fail; 940 } 941 942 pool->base.mis[i] = dce120_mem_input_create(ctx, i); 943 944 if (pool->base.mis[i] == NULL) { 945 BREAK_TO_DEBUGGER(); 946 dm_error( 947 "DC: failed to create memory input!\n"); 948 goto controller_create_fail; 949 } 950 951 pool->base.ipps[i] = dce120_ipp_create(ctx, i); 952 if (pool->base.ipps[i] == NULL) { 953 BREAK_TO_DEBUGGER(); 954 dm_error( 955 "DC: failed to create input pixel processor!\n"); 956 goto controller_create_fail; 957 } 958 959 pool->base.transforms[i] = dce120_transform_create(ctx, i); 960 if (pool->base.transforms[i] == NULL) { 961 BREAK_TO_DEBUGGER(); 962 dm_error( 963 "DC: failed to create transform!\n"); 964 goto res_create_fail; 965 } 966 967 pool->base.opps[i] = dce120_opp_create( 968 ctx, 969 i); 970 if (pool->base.opps[i] == NULL) { 971 BREAK_TO_DEBUGGER(); 972 dm_error( 973 "DC: failed to create output pixel processor!\n"); 974 } 975 } 976 977 if (!resource_construct(num_virtual_links, dc, &pool->base, 978 &res_create_funcs)) 979 goto res_create_fail; 980 981 /* Create hardware sequencer */ 982 if (!dce120_hw_sequencer_create(dc)) 983 goto controller_create_fail; 984 985 dc->caps.max_planes = pool->base.pipe_count; 986 987 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 988 989 bw_calcs_data_update_from_pplib(dc); 990 991 return true; 992 993 irqs_create_fail: 994 controller_create_fail: 995 disp_clk_create_fail: 996 clk_src_create_fail: 997 res_create_fail: 998 999 destruct(pool); 1000 1001 return false; 1002 } 1003 1004 struct resource_pool *dce120_create_resource_pool( 1005 uint8_t num_virtual_links, 1006 struct dc *dc) 1007 { 1008 struct dce110_resource_pool *pool = 1009 dm_alloc(sizeof(struct dce110_resource_pool)); 1010 1011 if (!pool) 1012 return NULL; 1013 1014 if (construct(num_virtual_links, dc, pool)) 1015 return &pool->base; 1016 1017 BREAK_TO_DEBUGGER(); 1018 return NULL; 1019 } 1020